Relevant bibliographies by topics / RPC – RISC Processor Core

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'RPC – RISC Processor Core'

Author: Grafiati
Published: 3 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "RPC – RISC Processor Core"

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ÖZKILBAÇ, Bahadır, and Tevhit KARACALI. "Design of 32-bit RISC Processor with IEEE754 Standard Floating-Point Unit in FPGA for Digital Signal Processing Applications." Erzincan Üniversitesi Fen Bilimleri Enstitüsü Dergisi 15, no. 3 (2022): 699–714. http://dx.doi.org/10.18185/erzifbed.1077921.

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The design of RISC processors, which are the key of digital signal processing applications, are increasing in reconfigurable hardware. FPGAs are suitable reconfigurable hardware for RISC processor design, with advantages such as parallel processing and low power consumption. In this study, the design of the 32-bit RISC processor in a FPGA is presented. The designed RISC processor contains IEEE754 standard floating-point number processing unit, which is executed in a one clock cycle. The verification of the processor is performed for the Zynq-7000 SoC Artix-7 FPGA chip in the Xilinx Vivado tool
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Poduel, Bikash, Prasanna Kansakar, Sujit R. Chhetri, and Shashidhar Ram Joshi. "Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL." Nepal Journal of Science and Technology 15, no. 1 (2015): 81–88. http://dx.doi.org/10.3126/njst.v15i1.12021.

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This paper is delineating the design and implementation of high performance, synthesizable 32-bit pipelined Reduced Instruction Set Computer (RISC) Core. The design of the Harvard Architecture based 32-bit RISC Core involves design of 32-bit Data-path Unit, Control Unit, 32-bit Instruction Memory, 32-bit Data Memory, Register file with each register of size 32 bit. The processor is divided into Fetch, Decode, Execute and Write Back block in order to implement a four-stage pipeline. A 2*16 LCD is connected to the processor IO block to show the instruction execution sequence for demonstration in
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Elangovan, Yuvaraj, Mandar Saraf, B. Satyanarayana, et al. "NIOS II soft-core processor and ethernet controller solution for RPC-DAQ in INO ICAL." Journal of Instrumentation 20, no. 01 (2025): P01021. https://doi.org/10.1088/1748-0221/20/01/p01021.

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Abstract This paper introduces a high-performance Soft-Core Processor based data acquisition system designed for handling Resistive Plate Chambers (RPCs). The DAQ consist of FPGA-based hardware equipped with Soft-Core Processor and embedded hardwired Ethernet controllers named RPC-DAQ, offering a versatile and fast network-enabled data acquisition solution. A soft processor, NIOS, is instantiated within an Intel Cyclone IV FPGA, overseeing control, communication, and data transfer with remote processing units. These integrated RPC-DAQ units, in substantial numbers, connect to a limited set of
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Serpa, Francisco Silva e., Alan Marcel Fernandes De Souza, Hélio Fernando Bentzen Pessoa Filho, and Kassio Derek Nogueira Cavalcante. "RISC processor implementation 32-bit MIPS-based: an approach to teaching and learning." Concilium 23, no. 19 (2023): 119–32. http://dx.doi.org/10.53660/clm-2074-23p21.

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This article describes the development of the design of a processor based on the RISC architecture, taking the 32-bit MIPS microprocessor as a basis. The RISC architecture, which stands for Reduced Instruction Set Computer, is characterized by having a reduced instruction set, aiming to optimize the processor's overall performance. The designed MIPS processor follows a 5-stage pipeline, which comprises the instruction fetch, instruction decode, execution, preparation and memory access phases. The main objective of this article is to carry out the structural development of the processor, using
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Xue, Wang, Liu, Lv, Wang, and Zeng. "An RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications." Micromachines 10, no. 8 (2019): 541. http://dx.doi.org/10.3390/mi10080541.

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Blockchain technology is increasingly being used in Internet of things (IoT) devices for information security and data integrity. However, it is challenging to implement complex hash algorithms with limited resources in IoT devices owing to large energy consumption and a long processing time. This paper proposes an RISC-V processor with memristor-based in-memory computing (IMC) for blockchain technology in IoT applications. The IMC-adapted instructions were designed for the Keccak hash algorithm by virtue of the extendibility of the RISC-V instruction set architecture (ISA). Then, an RISC-V pr
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Pratik, Katwate, Pardeshi Sanjay, and Tiwatane Vardhman. "PERFORMANCE ENHANCEMENT OF 8 BIT RISC ARCHITECTURE." JournalNX - a Multidisciplinary Peer Reviewed Journal RIT PG Con-18 (April 22, 2018): 209–12. https://doi.org/10.5281/zenodo.1413405.

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 In this paper we have selected PIC16A84 processor as base platform for the enhancement of its features. Selected processor is based on the 8bit RISC platform. The intention is to enhance the capabilities of the soft-core in terms of 16 bit arithmetic operations. Addition of new blocks tested by adding the new instruction in the instruction set. https://journalnx.com/journal-article/20150519
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Miyamori, Takashi, Jun Tanabe, Yasuhiro Taniguchi, et al. "Development of Image Recognition Processor Based on Configurable Processor." Journal of Robotics and Mechatronics 17, no. 4 (2005): 437–46. http://dx.doi.org/10.20965/jrm.2005.p0437.

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We developed an image recognition processor, “Visconti,” based on a configurable processor. Three VLIW processors that execute three instructions in parallel are integrated into a single chip with peripheral modules such as video I/Os and an SDRAM controller. Each VLIW processor has a RISC processor core and a VLIW coprocessor dedicated to image processing. The coprocessor executes SIMD instructions such as 8-parallel byte. Visconti was fabricated using 0.13μm CMOS technology, operates at 150MHz, and consumes about 1W. We present actual application examples of Visconti, onboard surveillance fo
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Li, Jiemin, Shancong Zhang, and Chong Bao. "DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA." Electronics 11, no. 1 (2021): 122. http://dx.doi.org/10.3390/electronics11010122.

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With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real
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Gschwind, M., V. Salapura, and D. Maurer. "FPGA prototyping of a RISC processor core for embedded applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9, no. 2 (2001): 241–50. http://dx.doi.org/10.1109/92.924027.

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Cheng, Yuan-Hu, Li-Bo Huang, Yi-Jun Cui, Sheng Ma, Yong-Wen Wang, and Bing-Cai Sui. "RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core." Journal of Computer Science and Technology 37, no. 6 (2022): 1307–19. http://dx.doi.org/10.1007/s11390-022-0910-x.

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Dissertations / Theses on the topic "RPC – RISC Processor Core"

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Yu, Chih-Hong, and 游志宏. "Register Renaming in X-86 Compatible, RISC-Core Superscalar Processor." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/87624653731328498894.

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碩士<br>國立臺灣大學<br>資訊工程學系研究所<br>85<br>As the demand for processing power increases, several different methods haveem erged that result in high-performance processing units. Nowadays, the supersca lar approach is a vesy popular technique for increasing the performanceof proc essors. The term superscalar refers to a processor architecture wheremultiple instructions are fetched and decoded from one standard instruction stream, but are executed simultaneously on separate functional units. It canget high perf or
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Fang, Leo, and 方耀弘. "A Redeced SIMD Technology for The Integration to ARM RISC Processor Core." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/d49759.

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碩士<br>逢甲大學<br>電機工程所<br>90<br>Information Appliances(IA) is an important technology because of its features of cheap and convenience. It means that the functions of PC will be replaced by other devices, such as smart phone, PDA, portable computer…, and so on. According to the system properties of IA, the leading IA products are designed by SOC(System On a Chip) chips which satisfy the restrictions of small-size、low-power consumption. The kernel of SOC is built by a embedded processor to provide high-performance processing capability under reasonable cost. Because of the implementation limitatio
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Book chapters on the topic "RPC – RISC Processor Core"

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Suh, Hyo-Joong, and Jeongmin Kim. "RISC/DSP Dual Core Wireless SoC Processor Focused on Multimedia Applications." In Embedded and Ubiquitous Computing – EUC 2005. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11596356_34.

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Martínez, Héctor, Francisco D. Igual, Rafael Rodríguez-Sánchez, Sandra Catalán, Adrián Castelló, and Enrique S. Quintana-Ortí. "Inference with Transformer Encoders on ARM and RISC-V Multicore Processors." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-69766-1_26.

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AbstractWe delve into the performance of transformer encoder inference on low-power multi-core processors from two perspectives: First, we conduct a detailed profile of the inference process for two members of the BERT family on a modern multi-core processor, identifying the main bottlenecks and opportunities for improvement. Second, we propose a number of accumulative optimisations for their primary building blocks. For that, we elaborate our own implementation of the general matrix multiplication (), which dynamically tunes several key parameters yielding relevant performance gains for trans
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Kalmath, Manjunath, Akshay Kulkarni, Saroja V. Siddamal, and Jayashree Mallidu. "Implementation of 32-bit ISA Five-Stage Pipeline RISC-V Processor Core." In Artificial Intelligence and Sustainable Computing. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-1653-3_19.

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"A RISC Design: Synthesis of the MIPS Processor Core." In Rapid Prototyping of Digital Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-72671-7_14.

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Ritt, Maria Eduarda Santos, and Douglas Reis Abdalla. "RELAÇÕES HEMATIMÉTRICAS COMO PREDITORES DE COMPLICAÇÕES GESTACIONAIS: UM PARADIGMA NA TRIAGEM DE RISCO MATERNO-FETAL." In Ciência, Cuidado e Saúde: contextualizando saberes - Vol.6. Editora Científica Digital, 2025. https://doi.org/10.37885/250319087.

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A gravidez, um processo fisiológico complexo, pode ser afetada por complicações como parto prematuro, pré-eclâmpsia e aborto, contribuindo para a morbimortalidade materno-fetal. Este estudo revisa a importância das relações hematimétricas – neutrófilo-linfócito (RNL), monócito-linfócito (RML) e plaqueta-linfócito (RPL) – como biomarcadores inflamatórios acessíveis na predição dessas condições. No parto prematuro, a RNL, RML e RPL refletem inflamação sistêmica associada a infecções e ruptura prematura de membranas, com potencial preditivo para triagem de risco. Na pré-eclâmpsia, elevações de RN
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Conference papers on the topic "RPC – RISC Processor Core"

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Rajyan, Abhinav, and Gaurav Saini. "SystemVerilog Based Design of an RV32I Compliant RISC-V Processor Core." In 2024 5th IEEE Global Conference for Advancement in Technology (GCAT). IEEE, 2024. https://doi.org/10.1109/gcat62922.2024.10923874.

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Abdelhamid, Riadh Ben, Vladislav Valek, and Dirk Koch. "SPARKLE: A 1,024-Core/16,384-Thread Single FPGA Many-Core RISC-V Barrel Processor Overlay." In 2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2024. http://dx.doi.org/10.1109/asap61560.2024.00032.

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Zhang, Shengnan, Yifan Zhao, Xinglong Yu, and Jun Han. "RISC-V Domain-Specific Processor for Accelerating SPHINCS+ on Multi-Core Architecture." In 2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT). IEEE, 2024. https://doi.org/10.1109/icsict62049.2024.10830991.

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Zhao, Tenghao, and Zhaohui Ye. "ZeroVex: A Scalable and High-performance RISC-V Vector Processor Core for Embedded Systems." In 2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2024. http://dx.doi.org/10.1109/asap61560.2024.00018.

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Abdelhamid, Riadh Ben, and Dirk Koch. "BRISKI: A RISC-V barrel processor approach for higher throughput with less resource tax." In 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2024. https://doi.org/10.1109/mcsoc64144.2024.00092.

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Yasmin, Samina, Muhammad Asim Naveed, Tassadaq Hussain, and Eduard Ayguade. "Detailed Analysis on the Micro-Architecture and Integration of Bit Manipulation Extensions in the SweRV EH1 Core of a RISC-V Processor and its Functional Verification." In 2024 21st International Bhurban Conference on Applied Sciences and Technology (IBCAST). IEEE, 2024. https://doi.org/10.1109/ibcast61650.2024.10877126.

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Sarkar, Pallabi, Reza Sedaghat, and Anirban Sengupta. "Application specific processor vs. microblaze soft core RISC processor." In the International Conference. ACM Press, 2011. http://dx.doi.org/10.1145/2007052.2007069.

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Salim, Ahmad Jamal, Sani Irwan Md Salim, Nur Raihana Samsudin, and Yewguan Soo. "Customized instruction set simulation for soft-core RISC processor." In 2012 IEEE Control and System Graduate Research Colloquium (ICSGRC). IEEE, 2012. http://dx.doi.org/10.1109/icsgrc.2012.6287132.

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Sethulekshmi R, Jazir S, Riyaz A. Rahiman, Ragipati Karthik, Abdulla M S, and Sree Swathy S. "Verification of a RISC processor IP core using SystemVerilog." In 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET). IEEE, 2016. http://dx.doi.org/10.1109/wispnet.2016.7566385.

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Islam, Md Ashraful, and Kenji Kise. "Efficient Resource Shared RISC-V Multicore Processor." In 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2021. http://dx.doi.org/10.1109/mcsoc51149.2021.00061.

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