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Dogan, Rabia. "System Level Exploration of RRAM for SRAM Replacement." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92819.
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Recently an effective usage of the chip area plays an essential role for System-on-Chip (SOC) designs. Nowadays on-chip memories take up more than 50%of the total die-area and are responsible for more than 40% of the total energy consumption. Cache memory alone occupies 30% of the on-chip area in the latest microprocessors. This thesis project “System Level Exploration of RRAM for SRAM Replacement” describes a Resistive Random Access Memory (RRAM) based memory organizationfor the Coarse Grained Reconfigurable Array (CGRA) processors. Thebenefit of the RRAM based memory organization, compared to the conventional Static-Random Access Memory (SRAM) based memory organization, is higher interms of energy and area requirement. Due to the ever-growing problems faced by conventional memories with Dynamic Voltage Scaling (DVS), emerging memory technologies gained more importance. RRAM is typically seen as a possible candidate to replace Non-volatilememory (NVM) as Flash approaches its scaling limits. The replacement of SRAMin the lowest layers of the memory hierarchies in embedded systems with RRAMis very attractive research topic; RRAM technology offers reduced energy and arearequirements, but it has limitations with regards to endurance and write latency. By reason of the technological limitations and restrictions to solve RRAM write related issues, it becomes beneficial to explore memory access schemes that tolerate the longer write times. Therefore, since RRAM write time cannot be reduced realistically speaking we have to derive instruction memory and data memory access schemes that tolerate the longer write times. We present an instruction memory access scheme to compromise with these problems. In addition to modified instruction memory architecture, we investigate the effect of the longer write times to the data memory. Experimental results provided show that the proposed architectural modifications can reduce read energy consumption by a significant frame without any performance penalty.
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Amer, Aya G. (Aya Galal Mahdy ElSayed). "SHARC : self-healing analog with RRAM and CNFETs." Thesis, Massachusetts Institute of Technology, 2019. https://hdl.handle.net/1721.1/122693.
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This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 49-50).
Next-generation applications require processing on massive amount of data in real-time, exceeding the capabilities of electronic systems today. This has spurred research in a wide-range of areas: from new devices to replace silicon-based field-effect transistors (FETs) to new circuit and system architectures with fine-grained and dense integration of logic and memory. However, isolated improvements in just one area is insufficient. Rather, enabling these next-generation applications will require combining benefits across all levels of the computing stack: leveraging new devices to realize new circuits and architectures. For instance, carbon nanotube (CNT) field-effect transistors (CNFETs) for logic and Resistive Random-Access Memory (RRAM) for memory are two promising emerging nanotechnologies for energy-efficient electronics. However, CNFETs suffer from inherent imperfections (such as of metallic CNTs, m-CNTs), which have prohibited realizing large-scale CNFET circuits in the past. This work proposes a circuit design technique that integrates and combines the benefits of both CNFETs with RRAM to realize three-dimensional (3D) circuits that are immune to m-CNTs. Leveraging this technique, we show the first experimental demonstration of CNFET-based analog mixed-signal circuits.
by Aya G. Amer.
S.M.
S.M. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
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Alayan, Mouhamad. "Étude des mémoires résistives (RRAM) à base d’HfO2 : caractérisation et modélisation de la fiabilité des cellules mémoire et des nouveaux dispositifs d'accès (Sélecteurs)." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT032/document.
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L'écart de vitesse entre le processeur et la mémoire vive est devenu un point faible pour les performances des systèmes. En raison de ces limitations, de nombreuses mémoires émergentes ont été proposées comme solutions alternatives à ces problèmes existant dans la hiérarchie mémoire. Les mémoires résistives (RRAM) sont considérées comme des candidats pour la « storage class memory » (SCM), les mémoires non volatiles embarquées (eNVM), et les systèmes neuromorphique. Cependant, les problèmes de fiabilité tels que la rétention de données sont encore en cours d'amélioration. De plus, pour obtenir des matrices mémoires de grande densité, la RRAM a besoin des sélecteurs qui seront intégrer en série avec elle dans une architecture un-sélecteur une-résistance (1S1R). Le sélecteur est nécessaire avec le point mémoire pour éliminer les problèmes des courants de fuite, qui gênent le bon fonctionnement de la matrice mémoire dans des architectures crossbar et verticales 3D.Dans cette thèse, notre objectif principal est de traiter les défis ci-dessus. Notre travail peut être divisé en deux parties principales : i) l'étude de la fiabilité des cellules RRAM basées sur HfO2 et ii) la caractérisation des opérations de base et des performances des cellules RRAM basées sur HfO2 et qui sont co-intégrées avec deux types différents des sélecteurs. Pour la partie fiabilité, nous avons étudié les effets du dopage aluminium (Al) sur la rétention de données des cellules RRAM à base de HfO2. Des dispositifs à simple et double couche avec différentes concentrations d'aluminium ont été fabriqués et testés. A partir des comportements électriques macroscopiques, comme la dégradation du diélectrique en fonction du temps (TDDB) et l’opération de forming avec des rampes de tension, on a extrait des propriétés microscopiques des matériaux tels que l'énergie d'activation nécessaire pour la rupture d’une liaison chimique à champ nul et le moment dipolaire des liaisons dans les matériaux testés. En utilisant ces paramètres microscopiques nous avons effectué tout au long de ce travail des simulations physiques pour comprendre les dynamiques de l’opération de forming ainsi que les mécanismes physiques impliqués pendant les opérations du dispositif mémoire. Deuxièmement, nous avons étudié l'immunité aux rayonnements de la RRAM à base de HfO2 pour les applications spatiales. Nos dispositifs RRAM ont été exposés à une énergie de 266 MeV d'ions lourds d'iode. Des analyses pré- et post-exposition ont été effectuées sur les états de la mémoire et les tensions de programmation pour étudier les effets de l'irradiation sur les caractéristiques du dispositif mémoire.Dans la partie des dispositifs d’accès, nous avons évalué deux types différents des sélecteurs. Une forte non-linéarité dans les caractéristiques courant / tension est obligatoire pour effectuer une lecture précise et une écriture à faible consommation. Dans le premier dispositif étudié, la sélectivité est introduite en ajoutant une couche d'oxyde dans l’empilement mémoire et qui agit comme une barrière tunnel. Le principal avantage de cette méthode est la facilité d’intégration de la barrière tunnel, par contre elle souffre d'une faible sélectivité (~ 10) et d'un faible courant de programmation qui dégrade la rétention de données. Deuxièmement, on a co-intégré avec l’RRAM un sélecteur OTS et le dispositif 1S1R a été entièrement caractérisé. Le sélecteur OTS offre une plus grande sélectivité par rapport à la barrière tunnel avec les possibilités d'augmenter fortement cette sélectivité par l'ingénierie des matériaux chalcogénures. Plus de 106 cycles de lecture ont été obtenu pour les dispositifs 1S1R en utilisant une stratégie de lecture innovante que nous avons suggérée pour éviter les lectures perturbatrices et réduire la consommation d'énergieThe performance gaps in nowadays memory hierarchy on the first hand between processor and main memory, on the other hand between main memory and storage have become a bottleneck for system performances. Due to these limitations, many emerging memories have been proposed as alternative solutions to fill out such concerns. The emerging non-volatile resistive random-access memories (RRAM) are considered as strong candidates for storage class memory (SCM), embedded nonvolatile memories (eNVM), enhanced solid-state disks, and neuromorphic computing. However, reliability challenges such as RRAM thermal stability and resistance variability are still under improvement processes. In addition, to achieve high integration densities the RRAM needs two terminal selector devices in one-selector one-resistor (1S1R) serial cell. The BEOL selector device enables suppression of the parasitic leakage paths, which hinder memory array operation in crossbar and vertical 3D architectures.In this PhD, our main focus is to address and treat the above challenges. Here, the work can be divided into two main parts: i) the investigation of the reliability of HfO2 based RRAM cells and ii) the characterization of the basis memory operations and performances of HfO2 based RRAM cells co-integrated with two different back end of line (BEOL) selector technologies.For the reliability part, we have investigated the effects of aluminum (Al) doping on data retention of HfO2 based RRAM cells. Single and double layer devices with different aluminum concentration were fabricated and tested. From macroscopic electrical characteristics, like time dependent dielectric breakdown (TDDB) and ramped voltage forming, microscopic properties of the materials such as the activation energy to break a bond at zero field and the dipole moment of the bond were extracted. These parameters have been used to shed new light on the mechanisms governing the forming process by means of device level simulations. Second, we have addressed the radiation immunity of HfO2 based RRAM for possible space applications as well. Our RRAM devices were exposed to 266 MeV Iodine heavy ions energy. Pre- and post-exposure analysis were carried out on the memory states and the programming voltages to study the effects of the irradiation on the memory characteristics. Throughout this work, we have performed physics based simulations to understand the dynamics of the forming process as well as the physical mechanisms involved during the memory operations.For the access devices part, we have evaluated two different types of selectors. For accurate reading and low power writing a strong selectivity in the current/voltage characteristics is required. In the first studied device, the selectivity is introduced by adding an oxide tunnel barrier. The main advantage of this strategy is that it is easy to integrate, however it suffers of low selectivity (~10) and low programming current. Second, an OTS based selector co-integrated with HfO2 based RRAM was fully characterized. OTS selector provides higher selectivity compared to the oxide tunnel barrier with the possibilities to strongly increase this selectivity by material engineering. Over 106 read cycles have been achieved on our 1S1R devices using an innovative read strategy that we have suggested to prevent disruptive read and to reduce the power consumption
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Parreira, Pedro Miguel Raimundo. "Nanocharacterisation of zirconia based RRAM devices deposited via PLD." Thesis, University of Glasgow, 2015. http://theses.gla.ac.uk/6877/.
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With CMOS technology reaching fundamental scaling limitations, innovative data storage technologies have been a topic of great academic and industrial interest. Emerging technologies, not all based in semiconductors, that exploit new variables like spin, polarisation, phase and resistance, are being investigated for their feasibility as data storage devices. One very promising technology is resistive switching random-access memory (RRAM). In RRAM devices memory operation relies on the change in resistance of a metal-insulator-metal structure, typically induced by ion migration combined with redox processes. Here, RRAM devices based on amorphous and crystalline zirconia have been prepared by means of pulsed laser deposition (PLD). The thesis starts with an overview of the commissioning of a new PLD system, with a focus on characterisation of the laser ablation plume, reduction of the density of “droplets” and development of the optimal system parameters, like temperature, oxygen pressure and laser fluence, for the preparation of zirconia based RRAM devices. For both amorphous and crystalline devices, titanium was used as an active electrode as it promotes the introduction of oxygen vacancies which are responsible for inducing resistive switching. In addition, growth of epitaxial Nb doped strontium titanate (Nb:STO) via PLD was achieved, as the high temperatures used during growth hinder the use of metallic bottom electrodes. Both types of RRAM devices have good performance figures, with ON/OFF ratios of 1000 and 10000 and endurance of more than 10000 cycles. Conduction mechanisms point to two different types of resistive switching: insulator-to-metal transition and trapping and de-trapping at the metal-oxide interfaces. Surprisingly, both conduction mechanisms were found to coexists on amorphous devices. Scanning transmission electron microscopy and electron energy loss spectroscopy were used to investigate how interfaces can influence resistive switching. Results indicate that titanium, in addition to introducing oxygen vacancies, creates an ohmic interface with zirconia which forces the resistive switching to take place on the inert metal-oxide Schottky interface, which was not described so far.
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Ellis, Noah. "Design, fabrication, and characterization of nano-scale cross-point hafnium oxide-based resistive random access memory." Thesis, Georgia Institute of Technology, 2016. http://hdl.handle.net/1853/55038.
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Non-volatile memory (NVM) is a form of computer memory in which the logical value (1 or 0) of a bit is retained when the computer is in its’ powered off state. Flash memory is a major form of NVM found in many computer-based technologies today, from portable solid state drives to numerous types of electronic devices. The popularity of flash memory is due in part to the successful development and commercialization of the floating gate transistor. However, as the floating gate transistor reaches its’ limits of performance and scalability, viable alternatives are being aggressively researched and developed. One such alternative is a memristor-based memory application often referred to as ReRAM or RRAM (Resistive Random Access Memory). A memristor (memory resistor) is a passive circuit element that exhibits programmable resistance when subjected to appropriate current levels. A high resistance state in the memristor corresponds to a logical ‘0’, while the low resistance state corresponds to a logical ‘1’. One memristive system currently being actively investigated is the metal/metal oxide/metal material stack in which the metal layers serve as contact electrodes for the memristor with the metal oxide providing the variable resistance functionality. Application of an appropriate potential difference across the electrodes creates oxygen vacancies throughout the thickness of the metal oxide layer, resulting in the formation of filaments of metal ions which span the metal oxide, allowing for electronic conduction through the stack. Creation and disruption of the filaments correspond to low and high resistance states in the memristor, respectively. For some time now, HfO2 has been researched and developed to serve as a high-k material for use in high performance CMOS MOSFETs. As it happens, HfO2-based RRAM devices have proven themselves as viable candidates for NVM as well, demonstrating high switching speed (< 10 ns), large OFF/ON ratio (> 100), good endurance (> 106 cycles), long lifetime, and multi-bit storage capabilities. HfO2-based RRAM is also highly scalable, having been fabricated in cells as small as 10 x 10 nm2 while still maintaining good performance. Previous work examining switching properties of micron scale HfO2-based RRAM has been performed by the Vogel group. However, a viable process for fabrication of nano-scale RRAM is required in order to continue these studies. In this work, a fabrication process for nano-scale cross-point TiN/ HfO2/TiN RRAM devices will be developed and described. Materials processing challenges will be addressed. The switching performance of devices fabricated by this process will be compared to the performance of similar devices from the literature in order to confirm process viability.
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Hanna, Drew E. "Developing RRAM-Based Approaches for Security and Provisioning of ICs." University of Cincinnati / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1617108121648124.
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Hijazi, Basma. "Design and optimization of low-power embedded resistive memory (RRAM)." Electronic Thesis or Diss., Aix-Marseille, 2020. http://www.theses.fr/2020AIXM0316.
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L’objectif de la thèse est de démontrer les avantages que peuvent apporter l’intégration de mémoires non volatiles résistives dans les applications embarquées basses consommation sur la base d’un circuit mémoire complet. Ces applications présentent des contraintes, largement supérieures aux contraintes habituelles, en termes d’ultra faible consommation et de sécurité (intégrité, confidentialité des données, notamment dans le domaine de l’e-santé). Un aspect important du travail de thèse est consacré à la fiabilité de ces mémoires aussi bien au niveau circuit qu’au niveau système. Cela passe par la mise en place de techniques de test embraquées au niveau circuit et l’utilisation de code de correcteurs d’erreurs niveau Système. Le sujet de thèse propose deux volets : il s'agit d'abord d'étudier les différentes cellules mémoires résistives les plus assujetties à une utilisation dans un système embarqué basse consommation. Le deuxième volet consistera à élaborer toute la circuiterie de mise en œuvre du plan mémoire construit à partir des cellules élémentaires. L’innovation apportée par cette étude est double : type de cellule mémoire étudié et l’évaluation de la fiabilité de ces mémoiresThe objective of the thesis is to demonstrate the advantages that the integration of resistive non-volatile memories can bring in low-power on-board applications on the basis of a complete memory circuit. These applications present constraints, far greater than the usual ones, in terms of ultra-low consumption and security (integrity, data confidentiality, especially in the field of e-health). An important aspect of the thesis work is devoted to the reliability of these memories both at the circuit level and at the system level. This requires the implementation of embedded test techniques at the circuit level and the use of system level error correcting code. The thesis subject has two components: it is first of all to study the different resistive memory cells most subject to use in a low consumption on-board system. The second part will consist of developing all the circuitry for implementing the memory plane built from elementary cells. The innovation brought by this study is twofold: type of memory cell studied and the evaluation of the reliability of these memories
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Kwon, Jonghan. "Electron Microscopy Based Characterization of Resistive Switches." Research Showcase @ CMU, 2016. http://repository.cmu.edu/dissertations/701.
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Random Access Memory (RRAM) has emerged as a leading candidate for nonvolatile memory storage. RRAM devices typically consist of a metal/insulator/metal (MIM) structure and exhibit switching of the device resistivity state (low-to-high, highto- low) by application of electrical bias. It is now widely accepted that shunting and rupturing of local conductive paths (filaments) directly determines the resistance state. The size and composition of these filaments are very much an open question, but are usually attributed to high local concentrations of oxygen vacancies. Although there has been a huge body of research conducted in this field, the fundamental nature of the conductive path and basic switching/failure mechanisms are still under debate. This is largely due to a lack of structural analysis of existing filament size and composition in actual devices. Since the non-volatile nature and device reliability issues (i.e. retention and endurance) are directly related to the irreversible structural transformations in the device, microstructural characterization is essential for eventual commercialization of RRAM. In this study, I investigated oxygen vacancy defect dynamics under electric filed essential for resistive switching and aim to identify size, location, and chemical nature of the conductive filaments in RRAM devices by using a variety of devices and materials characterization methods: in situ transmission electron microscopy (TEM), highresolution TEM (HRTEM), scanning TEM (STEM)-electron energy loss spectroscopy (EELS), electron holography, rapid thermal annealing (RTA), transient thermometry, and electro-thermal simulation. I adopt an in situ electrical biasing TEM technique to study microstructural changes occurring during resistive switching using a model TiO2-based RRAM device, and confirmed the device is switchable inside of the TEM column. I observed extension and contraction of {011} and {121}-type Wadsley defects, crystallographic shear faults, associated with resistive switching. More specifically, emission and adsorption of oxygen vacancies under different polarity of electrical biases at the fault bounding dislocations were identified. The motion of Wadsley defects was used to track oxygen vacancy migration under electric field. Also, the microstructural changes that occur when the device experiences low electric field (~104 V/cm) was reported, akin to read disturb. Crossbar type RRAM device stacks consisting of TiN/a-HfAlOx/Hf/TiN were investigated to estimate filament size, filament temperature, and its chemical footprint using HRTEM, transient thermometry and numerical simulation. In each of the switched devices, a single crystallite ~ 8-16 nm in size embedded in an amorphous HfAlOx matrix was found. The HfAlOx crystallization temperature (Tc) of 850 K was determined by combining RTA and HRTEM imaging. In parallel, the filament size has been determined by transient thermometry. The temperature profile extracted from these measurements suggested that the peak filament temperature was > 1500 K at the center, with the hot zone (T > Tc = 850 K) extending to a radius of 7 nm around the filament. These results were consistent with the HRTEM observations of the crystallite size. The potential filament location (crystallite) in the switching devices was analyzed by STEM-EELS and identification of the filament chemical nature identification has been attempted.
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Nguyen, Thinh H. "Study of Reflection Coefficient in Different Resistive States of HfO2-based RRAM." University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535702700125043.
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Kazar, Mendes Munique. "X-ray photoelectron spectroscopy investigations of resistive switching in Te-based CBRAMs." Thesis, Université Paris-Saclay (ComUE), 2018. http://www.theses.fr/2018SACLS285/document.
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Les mémoires à pont conducteur (CBRAM) sont une option actuellement étudiée pour la prochaine génération de mémoires non volatiles. Le stockage des données est basé sur la commutation de la résistivité entre les états de résistance élevée (HRS) et faible (LRS). Sous polarisation électrique, on suppose qu'un trajet conducteur est créé par la diffusion des ions de l'électrode active dans l'électrolyte solide. Récemment, une attention particulière a été portée sur les dispositifs contenant un élément semi-conducteur tel que le tellure, fonctionnant avec des courants réduits et présentant moins de défaillances de rétention. Dans ces « subquantum CBRAMs », le filament est censé contenir du tellure, ce qui donne une conductance de 1 atome (G₁atom) significativement réduite par rapport aux CBRAMs standard et permettant ainsi un fonctionnement à faible puissance. Dans cette thèse, nous utilisons la spectroscopie de photoélectrons par rayons X (XPS) pour étudier les réactions électrochimiques impliquées dans le mécanisme de commutation des CBRAMs à base de Al₂O ₃ avec des alliages ZrTe et TiTe comme électrode active. Deux méthodes sont utilisées: i) spectroscopie de photoélectrons par rayons X de haute énergie non destructive (HAXPES) pour étudier les interfaces critiques entre l'électrolyte (Al₂O ₃ ) et les électrodes supérieure et inférieure et ii) les faisceaux d'ions à agrégats gazeux (GCIB), une technique de pulvérisation qui conduit à une dégradation plus faible de la structure, avec un profilage en profondeur XPS pour évaluer les distributions des éléments en profondeur. Des mesures ToF-SIMS sont également effectuées pour obtenir des informations complémentaires sur la répartition en profondeur des éléments. Le but de cette thèse est de clarifier le mécanisme de changement de résistance et de comprendre les changements chimiques aux deux interfaces impliquées dans le processus de « forming » sous polarisation positive et négative ainsi que le mécanisme de « reset ». Pour cela, nous avons effectué une comparaison entre le dispositif vierge avec un état formé, i.e. l'échantillon après la première transition entre HRS et LRS et un état reset, i.e. l'échantillon après la première transition entre LRS et HRS.L'analyse du « forming » positif pour les dispositifs ZrTe / Al₂O ₃ a montré une libération de Te liée à l’oxydation de Zr due au piégeage de l'oxygène de l'Al₂O ₃ sous l’effet du champ électrique. D'autre part, pour les dispositifs TiTe / Al₂O ₃, la présence d'une couche importante d'oxyde de titane à l'interface avec l'électrolyte a provoqué une dégradation permanente de la cellule en polarisation positive. Pour le « forming » négatif, nos résultats montrent un mécanisme hybride, à savoir une combinaison de formation de lacunes d'oxygène dans l'oxyde provoquée par la migration de O2- entraîné par le champ électrique vers l'électrode inférieure et la libération de tellure pour former des filaments conducteurs. De plus, les résultats obtenus par profilométrie XPS et ToF-SIMS ont indiqué une possible diffusion de Te dans la couche d'Al₂O ₃. Lors du « reset », il y a une recombinaison partielle des ions oxygène avec les lacunes d'oxygène près de l'interface TiTe / AlAl₂O ₃ avec une perte de Te. Un mécanisme hybride a également été observé sur les dispositifs ZrTe / Al₂O ₃ pendant le « forming » négatif. En tenant compte du rôle important de la migration d'oxygène dans la formation / dissolution des filaments, nous discutons également des résultats obtenus par XPS avec polarisation électrique in- situ (sous ultravide) pour mieux comprendre le rôle de l'oxydation de surface et des interfaces dans la commutation résistiveConducting bridging resistive random accessmemories (CBRAMs) are one option currently investigated for the next generation of non volatile memories. Data storage is based on switching the resistivity between high (HRS) and low (LRS) resistance states. Under electrical bias,a conductive path is assumed to be created by ions diffusion from the active electrode into the solid electrolyte. Recently, special attention has been drawn to devices containing an elemental semiconductor such as tellurium, operating with reduced currents and less retention failures. In these subquantum CBRAM cells, the filament is thought to contain tellurium , yielding a 1-atomconductance (G₁atom) significantly reduced compared to standard CBRAMs and thus allowing low power operation. In this thesis, we use X-rayphotoelectron spectroscopy (XPS) to learn about electrochemical reactions involved in the switching mechanism of Al₂O₃ based CBRAMswith ZrTe and TiTe alloys as active electrode. Two methods are used: i) non-destructive Hard X-ray photoelectron spectroscopy (HAXPES) to investigate the critical interfaces between the electrolyte (Al₂O₃) and the top and bottom electrodes and ii) Gas Cluster Ion Beams (GCIB), a sputtering technique that leads to lower structure degradation, combined with XPS depth profiling to evaluate chemical depth distributions. To FSIMS measurements are also performed to get complementary in-depth chemical information.The aim of this thesis is to clarify the driving mechanism and understand the chemical changes at both interfaces involved in the forming process under positive and negative polarization as well as the mechanism of the reset operation. For that,we performed a comparison between as-grown state, i.e. the pristine device with a formed state,i.e. the sample after the first transition between HRS and LRS, and reset state, i.e. the sample after the first transition between LRS and HRS.Conducting bridging resistive random access memories (CBRAMs) are one option currently investigated for the next generation of non-volatile memories. Data storage is based on switching the resistivity between high (HRS) and low (LRS) resistance states. Under electrical bias,a conductive path is assumed to be created byions diffusion from the active electrode into the solid electrolyte. Recently, special attention has been drawn to devices containing an elemental semiconductor such as tellurium, operating with reduced currents and less retention failures. In these subquantum CBRAM cells, the filament is thought to contain tellurium , yielding a 1-atom conductance (G₁atom) significantly reduced compared to standard CBRAMs and thus allowing low power operation. In this thesis, we use X-ray photoelectron spectroscopy (XPS) to learn about electrochemical reactions involved in the switching mechanism of Al₂O₃ based CBRAMs with ZrTe and TiTe alloys as active electrode. Twomethods are used: i) non-destructive Hard X-rayphotoelectron spectroscopy (HAXPES) toinvestigate the critical interfaces between the electrolyte (Al₂O₃) and the top and bottom electrodes and ii) Gas Cluster Ion Beams (GCIB), a sputtering technique that leads to lower structure degradation, combined with XPS depth profiling to evaluate chemical depth distributions. To FSIMS measurements are also performed to get complementary in-depth chemical information.The aim of this thesis is to clarify the driving mechanism and understand the chemical changes at both interfaces involved in the forming process under positive and negative polarization as well as the mechanism of the reset operation. For that,we performed a comparison between as-grown state, i.e. the pristine device with a formed state,i.e. the sample after the first transition between HRS and LRS, and reset state, i.e. the sample after the first transition between LRS and HRS
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Valverde, Lucas. "Conception de cellules bipolaires commutables pour la technologie « Resistive Random Access Memory »." Mémoire, Université de Sherbrooke, 2014. http://hdl.handle.net/11143/6041.
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Avec le développement des technologies portables, les mémoires de type flash sont de plus en plus utilisées. Les compétences requises pour répondre au marché florissant augmentent chaque année. Cependant, les technologies actuelles sont basées sur l’intégration de transistors. Leurs performances impliquent un long temps d’écriture et des tensions d’opérations importantes.
La technologie Resistive Random Access Memory (RRAM) permet de répondre aux problématiques liées aux mémoires de type flash. La simplicité de fabrication de ces mémoires permet une forte densité d’intégration à faible coût. Également, les performances attendues par cette technologie dépassent les performances actuelles de Dynamic Random Access Memory (DRAM).
Les études réalisées actuellement au sein de la communauté scientifique permettent de déterminer les meilleures performances selon le choix des matériaux. Les premières études se concentraient sur l’oxyde de titane TiO2 en tant qu’isolant, puis avec l’augmentation de l’intérêt envers cette technologie le nombre d’oxydes étudiés s’est élargi. Les dispositifs conventionnels utilisent une couche d’oxyde comprise entre deux électrodes métalliques. En augmentant la densité de dispositifs dans des circuits en matrices croisées, l’isolation entre les points mémoires n’est pas garantie et les courants de fuites deviennent un facteur limitant. Pour éviter ces problèmes, le contrôle de chaque cellule est réalisé par un transistor, on parle d’architecture 1T1R avec n transistors nécessaires pour n points mémoires.
En 2008 Dubuc[1] propose un nouveau procédé de fabrication: le procédé nanodamascène. En adaptant ce procédé, et en disposant deux cellules dos à dos, nous créons un composant qui ne nécessite plus de transistor de contrôle [2]. Cela permet, en outre, de réduire les courants de fuite et simplifie l’adressage de chaque cellule. Les dispositifs sont incorporés dans une couche offrant une surface planaire. Il n’y a pas de limite technique à la superposition des couches, ce qui permet une haute densité d’intégration dans le Back-end-of-line du CMOS (Complementary Metal Oxyde Semiconductor), offrant de nouveaux horizons à la technologie RRAM.
Suivant les éléments précédents, mon projet de maîtrise a pour objectif de démontrer la possibilité de fabriquer des cellules RRAM en utilisant le procédé nanodamascène. Ce développement implique la fabrication, pour la première fois, de dispositifs micrométriques de type croisés et planaires en utilisant des architectures dont la fabrication est maîtrisée au sein du laboratoire. Cela permettra de mettre au point les différentes procédés de fabrication pour les deux types de dispositifs, de se familiariser avec les techniques de caractérisation électrique, d’acquérir des connaissances sur les matériaux actifs, et proposer des premiers dispositifs RRAM.
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Wu, Qian. "A nanoscale study of MOSFETs reliability and Resistive Switching in RRAM devices." Doctoral thesis, Universitat Autònoma de Barcelona, 2017. http://hdl.handle.net/10803/402233.
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El continuo escalado de la tecnología CMOS ha supuesto un gran reto en cuanto a la fiabilidad de dispositivos MOSFET se refiere debido al aumento del campo eléctrico en su interior, el cual ha dado lugar a la aparición de diferentes mecanismos de fallo. Entre los más importantes, destacan los que afectan al stack de puerta tales como Bias Temperature Instabilities (BTI) y channel hot carrier degradation (CHC). Por otro lado, la reversibilidad en la formación de filamentos conductores (CF) en dieléctricos de puerta ha demostrado ser una alternativa muy importante para aplicaciones de memoria no volátiles futuras, como por ejemplo la tecnología RRAM (Resistive Random Acces Memory), basada en el fenómeno de Resistive Switching (RS). Sin embargo, todavía queda por resolver numerosos retos tecnológicos, como los asociados a los electrodos, dado que el mecanismo de RS se ve fuertemente influenciado por las propiedades de sus materiales. Debido a sus excelentes propiedades, el uso de grafeno como electrodo podría ofrecer grandes ventajas. Sin embargo, la variabilidad y fiabilidad de los dispositivos basados en grafeno es todavía un tema pendiente de resolver. El objetivo de esta tesis es el estudio a la nanoescala de la fiabilidad de transistores MOSFET y del RS apra aplicaciones de memoria. Concretamente se han estudiado los siguientes tópicos. En primer lugar, se ha analizado el impacto de los estresses Bias Temperature Instability (BTI) y Channel Hot Carriers (CHC) en stacks de puerta de transistores MOSFET con CAFM. El CAFM ha demostrado que la degradación inducida durante un estrés NBTI es homogénea a lo largo del canal, mientras que el estrés CHC induce diferentes niveles de degradación, siendo mayor cerca del drenador y la fuente. En segundo lugar, se ha estudiado el impacto de estreses NBTI y CHC en MOSFETs mecánicamente estresados con SiGe en las regiones de drenador y fuente. Los resultados muestran que, aunque los dispositivos estresados mecánicamente tienen una mayor movilidad, son más sensibles a los estreses eléctricos CHC y NBTI. Este efecto se ha observado en mayor medida en dispositivos de canal corto. En los dispositivos estresados por CHC, esta mayor susceptibilidad al estrés eléctrico se ha relacionado con una densidad de defectos mayor cerca de las difusiones, de acuerdo con los datos obtenidos con CAFM. En tercer lugar, se han estudiado spots individuales a la nanoescala y a diferentes temperaturas en capas de SiON sin previo estrés eléctrico. Se han observado conmutaciones RTN entre dos estados de conductividad, que se han asociado a la captura/emisión de cargas en los defectos presentes en el dieléctrico. En cuarto lugar, se ha analizado a la nanoescala filamentos conductores (CFs) en estructuras Ni/HfO2/Si con Resistive Switching mediante CAFM. Se han observado diferencias en la conductividad del CF dependiendo del estado resistivo del dispositivo. Además, para los dos estados resistivos, la conducción a través del CF ha mostrado ser no homogénea. Finalmente, se ha estudiado las propiedades eléctricas y variabilidad de estructuras MIS capacitivas con grafeno como capa interficial entre el dieléctrico de HfO2 y el electrodo de puerta (dispositivos MGIS), así como su viabilidad como dispositivos RRAM. Se ha observado que, con la presencia de la capa interficial de grafeno, es posible medir varios ciclos de RS, mientras que en las estructuras MIS sin grafeno este comportamiento no se detectó. El análisis con CAFM ha mostrado que el grafeno evita la destrucción completa del dieléctrico durante el proceso de formación del CF, confirmando la función protectora del grafeno en estructuras MGIS.The continuous scaling down of CMOS technology has stood for a big challenge for reliability researchers, mainly due to the persistent increase of the electric fields in nanoscale devices, which can trigger different failure mechanisms. Among them, those related to the MOSFET gate dielectric such as Bias Temperature Instabilities (BTI) and channel hot carrier degradation (CHC), have a special relevance. On the other hand, the reversibility in the conductive filaments formation in dielectrics has demonstrated to be very promising for future non-volatile memory applications, as Resistive Random Access Memory (RRAM) technology, which is based on the Resistive Switching (RS) phenomenon. However, many technological issues are still open as those related to the electrodes, since the RS mechanism is strongly influenced by the electrode properties. Due to its special properties, graphene used as electrode in RRAM devices could offer great advantages. However, the graphene-based devices still suffer reliability and variability issues. This thesis addresses a nanoscale study of MOSFETs reliability and Resistive Switching in RRAM applications. The following are the main topics of the study. First, the gate oxide of MOSFETs has been analyzed after bias temperature instability (BTI) and channel hot-carrier (CHC) stresses with CAFM. The CAFM explicitly shows that while the degradation induced along the channel by a negative BTI stress is homogeneous, after a CHC stress different degradation levels can be distinguished, being higher close to source and drain. Second, strained MOSFETs with SiGe at the source/drain regions and different channel lengths have been studied, before and after CHC and NBTI stresses. The results show that although strained devices have a larger mobility, they are more sensitive to CHC and NBTI stresses. This effect has been observed to be larger in short channel devices. In CHC stressed devices, the higher susceptibility of strained MOSFETs to the stress has been related to a larger density of defects close to the diffusions, as suggested by CAFM data. Third, a CAFM has been used to study individual leaky spots at the nanoscale and at different temperatures on as-grown SiON layers. Switching between different conduction states have been measured in the form of Random Telegraph Noise during Constant Voltage Tests, which has been related to the trapping/detrapping of single charges in the defects present in the dielectric. The measurement of current maps at different Temperatures suggests that the detected leaky sites correspond to defects, whose activation depends on Temperature and that are randomly distributed in the gate area. Fourth, conductive filaments (CFs) in Ni/HfO2/Si resistive switching structures have been analyzed at the nanoscale by means of Conductive Atomic Force Microscopy (CAFM). Differences in the CF conductivity were measured depending on the resistive state of the device. Moreover, for both resistance states, non-homogeneous conduction across the CF area is observed, in agreement with a tree-shaped CF. Finally, the electrical properties and variability of capacitive MIS structures with graphene as interfacial layer between the HfO2 dielectric and the top electrode (MGIS devices), have been studied at device level and at the nanoscale. Their feasibility as RRAM devices was also evaluated. It was observed that, when graphene is present as an intercalated layer, several resistive switching cycles can be measured meanwhile the standard MIS structures cannot be switched. CAFM analysis showed that the graphene layer prevents the complete structural damage of the material during a forming process, confirming the protective role of graphene in a MGIS structure.
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Cabout, Thomas. "Optimisation technologique et caractérisation électrique de mémoires résistives OxRRAM pour applications basse consommation." Thesis, Aix-Marseille, 2014. http://www.theses.fr/2014AIXM4778/document.
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Aujourd'hui, le marché des mémoires non-volatile est dominé par la technologie Flash. Cependant, cette technologie est en passe d'atteindre ses limites de miniaturisation. Ainsi, dans le but de poursuivre la réduction des dimensions, de nouveaux concepts mémoires sont explorés. Parmi les technologies émergentes, la mémoire résistive OxRRAM basée sur la commutation de résistance d’une structure Métal/Isolant/Métal, cette technologie présente des performances prometteuses, supporte une réduction de ses dimensions critiques et offre une bonne compatibilité avec les filières CMOS. Toutefois, cette technologie mémoire n'en est qu'au stade du développement et se heurte à une compréhension que partielle des mécanismes de commutation de résistance.Ce travail de thèse s'intègre dans ce contexte et vise à apporter une contribution supplémentaire au développement de cette technologie. La première partie est consacrée à la sélection du meilleur couple électrodes/matériau actif. A l’aide d’une analyse des caractéristiques électriques de commutation, l’empilement TiNHfO2Ti est retenu pour être intégré dans une structure 1T1R. Une seconde partie présente la caractérisation électrique avancée de l’architecture mémoire 1T1R. L'influence des différents paramètres de programmation est analysée et les performances électriques sont évaluées. La dernière partie apporte des éléments d'analyse et de compréhension sur les mécanismes de commutation de résistance. La mesure, en fonction de la température, des caractéristiques électriques de commutation a permis d'analyser l'influence de la température et du champ électrique sur les mécanismes physiques à l'origine du changement de résistanceToday, non-volatile memory market is dominated by charge storage based technologies. However, this technology reaches his scaling limits and solutions to continue miniaturization meet important technological blocks. Thus, to continue scaling for advanced nodes, new non-volatile solutions are developed. Among them, oxide based resistive memories (OxRRAM) are intensively studied. Based on resistance switching of Metal/Isolator/Metal stack, this technology shows promising performances and scaling perspective but isn’t mature and still suffer from a lake of switching mechanism physical understanding.Results presented in this thesis aim to contribute to the development of OxRRAM technology. In a first part, an analysis of different materials constituting RRAM allow us to compare unipolar and bipolar switching modes and select the bipolar one that benefit from lower programming voltage and better performances. Then identified memory stack TiNHfO2Ti have been integrated in 1T1R structure in order to evaluate performances and limitation of this structure. Operating of 1T1R structure have been carefully studied and good endurance and retention performances are demonstrated. Finally, in the last part, thermal activation of switching characteristics have been studied in order to provide some understanding of the underling physical mechanisms. Reset operation is found to be triggered by local temperature while retention performances are dependent of Set temperature
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Li, Yibo. "Understanding the Mechanism of Failure in Low Temperature Zinc Oxide based RRAM Devices." University of Toledo / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1471864348.
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Ford, Andrew J. "LowPy: Simulation Platform for Machine Learning Algorithm Realization in Neuromorphic RRAM-Based Processors." University of Cincinnati / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1617105323741119.
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Ji, Li active 21st century. "SiOx-based resistive switching memory integrated in nanopillar structure fabricated by nanosphere lithography." Thesis, 2014. http://hdl.handle.net/2152/26200.
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A highly compact, one diode-one resistor (1D-1R) SiOx-based resistive switching memory device with nano-pillar architecture has been achieved for the first time using nano-sphere lithography. The average nano-pillar height and diameter are 1.3 μm and 130 nm, respectively. Low-voltage electroforming using DC bias and AC pulse response in the 50ns regime demonstrate good potential for high-speed, low-energy nonvolatile memory. Nano-sphere deposition, oxygen-plasma isolation, and nano-pillar formation by deep-Si-etching are studied and optimized for the 1D-1R configurations. Excellent electrical performance, data retention and the potential for wafer-scale integration are promising for future non-volatile memory applications.text
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Chiu, In Shiang, and 邱楹翔. "Fabrication of graphene and RRAM applications." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/jvr8gg.
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Chang, Chien-Le, and 張健樂. "Study on Multi Layer Graphene Oxide RRAM." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/62qj95.
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Ying-ChuanChen and 陳盈銓. "Resistive switching characteristics of sputtered TaOx RRAM." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/53292055814419816605.
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Kang, Hung-Sen, and 康閎森. "A Study on TeO2 Nanostructure RRAM Device." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/05581999738280561434.
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碩士國立臺灣大學
應用物理所
100
In this thesis, a resistive random-access memory was fabricated by using the tellurium dioxide. The nanostructure of the tellurium dioxide was grown on the p-type silicon substrate in a high-temperature furnace. Scanning electron microscopy, Photoluminescence and X-ray diffraction analysis were carried out to investigate the morphology and the crystalline structure of the grown tellurium dioxide, respectively. Two types of resistive random-access memory devices were fabricated by employing different materials, silver and aluminum, as the conducting layer. In this study, aluminum was coated as the electrodes by the thermal evaporation method. The resistive random-access memory device was constructed by sandwiching the tellurium layer between the p-type silicon substrate and the conducting layer. The measured current-voltage characteristics of the device with the aluminum conducting layer performed better than that with the silver one. To improve the device performance, annealing and extending the growth time of TeO2 nanostructure were attempted in this study, and the results show a positive outcome. Resistive random-access memory is a relatively new subject for solid state devices. Only a handful of experimental data are available to date. The results presented in this thesis indicate that the stability and persistence of the resistive random-access memory devices will be the fundamental challenges for its future development.
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Lin, Yen-Chuan, and 林妍君. "RRAM-Based Electronic Synaptic Device and Compact Model." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/ef2p36.
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碩士國立交通大學
電子工程學系 電子研究所
103
Human brain has been considered to be the most powerful “device” in the world. To realize low-power, high-density, and efficient parallel computation, researchers are actively investigating neuromorphic systems that operate in a similar manner of our brains. In the neuromorphic computation, synapse plays an important role in learning and memory. Therefore, to emulate the neuromorphic system, constructing an artificial electronic synapse is a critical step. Among all kinds of synaptic devices, resistive random access memory (RRAM), sometimes also called memristor, is one of the most promising candidates because of its 4F2 cell size, fast switching speed, and low power consumption. However, the variations of the SET and RESET operations in filamentary RRAM have been a critical issue to overcome. More importantly, it suffers from the sneak current issue when implementing a high-density three-dimensional (3D) array network,. In this thesis, we investigate a non-filamentary Ta/TaOx/TiO2/Ti RRAM as an artificial electronic synapse for future neuromorphic computation. The Ta/TaOx/TiO2/Ti double-layer RRAM has many outstanding advantages, including forming free, self-compliance, self-rectification, usage of fab-friendly materials, and gradual SET and RESET characteristics. Because the switching mechanism is different from that in filamentary RRAM, the variations of SET and RESET operations are greatly mitigated. Moreover, the proposed device can be used in 3D vertical arrays because the self-rectifying characteristics suppress the undesired sneak current. In Chapter 2, we summarized and demonstrated the basic synaptic characteristics in our two-dimensional (2D) synaptic RRAM. To mimic biological synapses. The spike-time-dependent-plasticity was measured using action-potential-like spike rather than regular square pulses. The potentiation and depression training processes demonstrates monotonic and analog synaptic weight changes and reproducible learning behaviors. Memory retention in our device lasts for minutes to hours, representing the transition from short-term memory to long-term memory. In Chapter 3, we construct an analytical compact model of our Ta/TaOx/TiO2/Ti device based on the general definition of memristors and the physical switching mechanism of the device. The compact model can be used in circuit-level simulation, and is essential for building large-scale neuromorphic computing systems. The proposed model was verified by the good agreement with the experiments in a finite programming voltage range of potentiation and depression and STDP. In Chapter 4, we further construct a 3D vertical synaptic device that is critical in constructing future high-density 3D neuron networks similar to our brains. In addition to excellent synaptic characteristics similar to its 2D counterpart, such as stable and tunable potentiation and depression training, the energy consumption per spike can be as low as a few fJ because of the extremely low operating current in the nanoscale device. The energy consumption is comparable to biological synapses and much lower than previous artificial synapses with an energy consumption of at least a few hundred fJ. With all of the advantages reported in this thesis, the proposed device could be as powerful as biological synapses and shows promising potential for future neuromorphic systems.
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Wang, Yu-Fen, and 王鈺芬. "Numerical simulation of RRAM and electronic synaptic device." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/w445ss.
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碩士國立交通大學
電子工程學系 電子研究所
103
In order to continue improving performance of large-scale information systems, it is essential to revolutionize the present memory and storage hierarchy where a large access time gap exists between DRAM and hard disks. Storage class memory (SCM) is proposed to fill the access time gap and significantly improve the system performance. Another critical issue of large-scale information systems is the power consumption. To achieve human-level intelligence, the required power consumption is as high as 1.4 MW by using the most advanced supercomputer, while the power consumption of human brain is merely 10 W. Aiming for energy-efficient, fault-tolerant and high-performance information systems, electronic synaptic devices for neuromorphic computing now attract significant attention. Among many emerging devices for storage class memory and electronic synapse, it is widely believed that RRAM is an extremely competitive candidate. For SCM, a comprehensive understanding of RRAM switching mechanism is the foundation of studying resistive-switching variation, thermal effect, current noise, retention/endurance degradation, and device optimization. For electronic synaptic devices, although there have been a few models proposed to explain the device behavior, most of them are oversimplified and cannot be applied for dynamic response, device optimization strategy, and simulation of large-scale neuromorphic computing systems. In this thesis, two numerical models are constructed for RRAM physical simulation. One is TiN/HfO2/Pt filamentary RRAM, and the other is Ta/TaOx/TiO2/Ti non-filamentary RRAM. The filamentary RRAM model is constructed based on the percolation theory. The model considers trap-assisted-tunneling current, oxygen ion migration, generation/recombination of oxygen vacancies, and Joule heating. The transient defect patterns of forming, SET, and RESET are investigated to explain the resistive switching. The I-V characteristics and Weibull distribution of SET voltage are also simulated. Furthermore, the Ta/TaOx/TiO2/Ti non-filamentary RRAM model is constructed based on homogeneous barrier modulation mechanism. The model considers WKB tunneling current limited by the TaOx barrier, Poisson equation, and continuity equation of ion migration. The transient oxygen ion and vacancy profiles during SET and RESET are investigated to explain the resistive switching and self-rectifying I-V curves. The multi-level RESET and film-thickness dependence are also successfully simulated. Furthermore, the Ta/TaOx/TiO2/Ti non-filamentary RRAM model is applied to simulate various electronic synaptic characteristics, including potentiation, depression, spike-timing-dependent plasticity, and paired-pulse facilitation, and show excellent agreements with the experiment data.
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Lin, Tzu-Ping, and 林子評. "Numerical Modeling of Filamentary and Non-filamentary RRAM." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/zjfvvq.
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碩士國立交通大學
電子工程學系 電子研究所
104
The discrepancy of access time between memories and hard disk drives becomes significant because of the device scaling. To bridge the access time gap, the storage class memory (SCM) was proposed. Among various candidates, the resistive switching random access memory (RRAM) is one of the most promising. On July 2015, Intel and Micron launched the Xpoint memory technology speculatively based on RRAM, highlighting its strong potential in the future. However, the complete model of RRAM to elucidate device properties such as resistive switching and conduction mechanism is still under active research. In this thesis, we built two numerical models for both filamentary and non-filamentary RRAMs. The filamentary RRAM model based on kinetic Monte Carlo (KMC) ions migration and percolation theory describes the interaction between oxygen ions and vacancies in the TiN/HfOx/Pt device. This model can interpret the formation and rupture of the conduction path in HfOx and thus the I-V characteristics. On the other hand, the non-filamentary RRAM model described electron (carrier) trapping/detrapping in the Ta/TaOx/TiO2/Ti device. Furthermore, the permittivity modulation in TiO2 depending on the carrier concentration leads to different voltage drops across the TaOx and TiO2 layers, and thus different high and low resistance states. Both models show good agreements with the measurement results. The characteristics of filamentary and non-filamentary RRAMs can be reasonably depicted. We believe that these studies would benefit further investigations and applications of RRAM.
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CHEN, TING-YU, and 陳廷譽. "γ-APTES-based organic RRAM Fabrication and Characterization." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/a7swuj.
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碩士國立暨南國際大學
電機工程學系
104
Abstract The main theme of this thesis is to investigate using organic dielectric material (3-aminopropyl) triethoxysilane (3-aminopropyl- triethoxysilane, γ-APTES) plus zinc oxide nanoparticles resistance (ZnO nanoparticles, ZnO NPs) as the dielectric material in an MIM structure for the application of resistive switching memory. The effect of variousγ-APTES thicknesses and different device structures on the resistive switching characteristics is explored. In this work, all the devices were fabricated on fluorinated tin oxide conductive glass (FTO) substrate. The dielectric materials were prepared by mixing the (3-aminopropyl) triethoxysilane with different concentrations and zinc oxide nanoparticles. Then, the mixed layers were deposited separately onto the cleaned FTO glass substrate by spin coating. Following that, a Ti layer by E-gun evaporation or a Al layer by thermal evaporation was deposited onto the dielectric layser as top electrode. Three different device structures were finally obtained: Al / γ-APTES / FTO, Al / γ-APTES +NPs / FTO, Ti / γ-APTES / FTO. After completion of the device fabrication, semiconductor parameter analyzer Agilent-4156B was used to measure their current - voltage (I-V) characteristics. The Ti or Al top electrode was biased positively and FTO bottom electrode biased negatively during the measurement. It is found that the lower the γ-APTES concentration is, the better resistive switching characteristics including better stability, higher resistance of high resistance state(RHRS) to resistance of low resistance state ( RLRS) ratios Althought the RHRS to RLRS ratio becomes smaller after adding ZnO NPs withγ-APTES, the device exhibits better stability than the device without adding ZnO NPs. Unipolar resistive switching characteristics are found inγ-APTES-based MIM structures.
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Sounak, Kumar Ray, and 尚恩. "Investigation of Transparent CeO2/ZnO Bi-Layer RRAM." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/7498y8.
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碩士國立交通大學
電機資訊國際學程
105
In recent times the concept of resistance based switching devices have drawn considerable amount of attention as the next non-volatile memory. The advantages it of Resistive Random Access memory is believed to be on fast operation, high density, small size , low power consumption and simple structure. In the present research work, we have studied the non-volatile memory characteristics of Transparent resistive random access memory (RRAM) devices, which have been fabricated and tested in the laboratory The Transparent RRAM has bi-stable switching characteristics, which exhibit two states of different resistances for logic levels. Compared to conventional memory devices, it has higher speed, lower power requirements and higher integration density making it potentially attractive for next-generation memory systems. The fabrication process of the device is CMOS compatible, having a simple MIM structure (in our case its bilayer) and requiring low processing temperature. This transparent memory device has been fabricated on glass substrate coated with Indium Tin Oxide (ITO). RF magnetron sputtering has been used to deposit a layer of ZnO on it followed by a layer of CeO2 and finally top electrodes have been formed using ITO. We used the top electrodes namely ITO to check their role on the device characteristics. Thereafter, the physical, electrical and reliability characteristics of the devices have been studied in detail. The conduction and switching mechanisms of the devices have been investigated. Finally the summary of the research study highlighting the potential of the device for future applications and scope for further work is presented.
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Liao, Hsin-Wei, and 廖信煒. "Microscopic Simulation of Switching Mechanism of RRAM Devices." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/93540296265936792085.
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Lin, Ku-Feng, and 林谷峰. "A Process Variation Tolerant Sensing Circuit for RRAM." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/07120249367383025169.
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碩士國立清華大學
電機工程學系
98
In recent years, higher and higher read/write speed is also required for high-performance portable equipment. Emerging NVMs have the potential to overcome the write performance and scalability limits of currently dominant Flash memories. The write time of RRAM can be less than 10ns, the read time will be bottleneck for high-speed applications. Besides, the read BL bias of RRAM cells has to be lower than 0.3V to prevent disturb, however, BL voltage of conventional current sensing circuit is sensitive to process and temperature variations. In addition, the reference cell resistance variation will cause read failure due to reference current variation. In this work, we propose a process variation tolerant read circuits featuring detection and compensation of process and temperature variations to avoid read disturbance, narrow-distribution reference generation scheme reduces the probability of read failure, and BL charging speed enhancement scheme shortens BL charging time. The proposed schemes enable high-speed and reliable read operation. An asynchronous 4M-bit RRAM testchip were fabricated in 0.18μm, 5-metal CMOS technology and ITRI resistive device technology with a nominal supply voltage of 1.8V for read circuits. We measured the current distribution of 2048 cells and 512 reference generators, the reduction of reference current variation is about 45% compared to normal LRS cell current distribution. The measured read time of random access and burst access are 7.2ns and 3.6ns respectively.
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"RRAM-based PUF: Design and Applications in Cryptography." Master's thesis, 2015. http://hdl.handle.net/2286/R.I.34831.
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abstract: The recent flurry of security breaches have raised serious concerns about the security of data communication and storage. A promising way to enhance the security of the system is through physical root of trust, such as, through use of physical unclonable functions (PUF). PUF leverages the inherent randomness in physical systems to provide device specific authentication and encryption.
In this thesis, first the design of a highly reliable resistive random access memory (RRAM) PUF is presented. Compared to existing 1 cell/bit RRAM, here the sum of the read-out currents of multiple RRAM cells are used for generating one response bit. This method statistically minimizes any early-lifetime failure due to RRAM retention degradation at high temperature or under voltage stress. Using a device model that was calibrated using IMEC HfOx RRAM experimental data, it was shown that an 8 cells/bit architecture achieves 99.9999% reliability for a lifetime >10 years at 125℃ . Also, the hardware area overhead of the proposed 8 cells/bit RRAM PUF architecture was smaller than 1 cell/bit RRAM PUF that requires error correction coding to achieve the same reliability.
Next, a basic security primitive is presented, where the RRAM PUF is embedded in the cryptographic module, SHA-256. This architecture is referred to as Embedded PUF or EPUF. EPUF has a security advantage over SHA-256 as it never exposes the PUF response to the outside world. Instead, in each round, the PUF response is used to change a few bits of the message word to produce a unique message digest for each IC. The use of EPUF as a key generation module for AES is also shown. The hardware area requirement for SHA-256 and AES-128 is then analyzed using synthesis results based on TSMC 65nm library. It is shown that the area overhead of 8 cells/bit RRAM PUF is only 1.08% of the SHA-256 module and 0.04% of the AES-128 module. The security analysis of the PUF based systems is also presented. It is shown that the EPUF-based systems are resistant towards standard attacks on PUFs, and that the security of the cryptographic modules is not compromised.Dissertation/Thesis
Masters Thesis Electrical Engineering 2015
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Tzeng, Bo-Shian, and 曾柏憲. "The research of scaling down in HfO2 RRAM." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/37227324143261981509.
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碩士國立中央大學
化學工程與材料工程研究所
100
Resistance Random Access Memory (RRAM) is the most simplified structure of memory, and it can be easily scaled down. RRAM has many advantages such as non-volatile property, high speed operation, low power consumption, low cost, and high data density. RRAM is the best candidate for high density device in the next generation. In this study, we used Ni/HfO2/Si as contact hole and crossbar structure, and used different electrode sizes to scale down. But it showed “forming fail” and “reset fail” in tiny scale. Nevertheless, using thicker TMO can reduce Vforming and enhance reliability in the device. At the same time, we also realized that the instrumental compliance was not fully dependable, so it had overshoot current which could damage the device. We must use 1D1R or 1T1R structure to avoid the overshoot current. Besides, the device can use different compliance to separate the oxygen filament (OF) and metal filament (MF). When using the OF mode with different top electrode materials, it had lower power consumption. So we can reduce “forming fail” and “reset fail” probability.
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廖昱程. "CMOS Logic-Compatible High Density 3D Via RRAM." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/47851367771092444245.
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Lin, Jia-Wei, and 林佳緯. "High Accuracy RRAM-Based Binary Neural Network Training." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/g5t559.
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碩士國立交通大學
電子研究所
107
Deep learning is getting popular at the edge devices to provide better services. However, its high computational complexity and memory bandwidth makes real time execution on the traditional Von Neuman architecture very challenging even with the low complexity binary neural network model. A promising solution, in-memory computing, computes directly in memory with high parallelism and reduces the data transmission time, especially with the emerging new device such as Resistive Random Access Memory (RRAM) due to its small area and low power nature. However, RRAM devices suffers from the non-ideal state switching and variation characteristics, which could seriously affects the performance of neural networks, even with the on-device training. To solve above problem, we first analyze the non-ideal device effect on the network training performance and propose to combine residual network architectures, more channel width, and 3x3 kernel size for better training on non-ideal devices. Furthermore, we systematically determine the hyper-parameters of RRAM-based BNNs with bad probability updating curve. This training strategy makes it get better training results. Besides, device variation due to non-uniformity of the process will make training process unstable and thus get a worse results. To overcome this problem, we propose hybrid RRAM-based BNNs to combine the benefits of both digital computation and RRAM-based computation. Moreover, we use a longer training period with the above determined hyper-parameters to further improve the tolerance on the C2C variation. With the designs mentioned above, we can improve the accuracy of RRAM-based BNN from 57.39% to 83.69% even though the devices are in a worst condition.
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Wu, Shu-Ching, and 吳書慶. "Characteristics of Rapid Thermal Annealed ZnO Resistive RAM (RRAM)." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/76075963447617095829.
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碩士逢甲大學
電子工程所
99
Presently, RRAM uses costly metals like Platinum (Pt) and Gold (Au) as the electrodes, this thesis focuses on cheaper metals like aluminum (Al) so as to increase the possibility for mass production. The experiments are split into two parts. Firstly, using a zinc (Zn) target undergoing reactive sputtering deposition of the zinc oxide (ZnOx) thin film with gas flow ratio of Ar:O2 to be 2, 3 and 5, respectively and a further annealing process in nitrogen (N2) environment. It was observed that the sample with Ar:O2=5 was most stable despite the number of switching cycles to be the least, with operating voltage less than 3V, and a long retention time of 104 s. Ohmic conduction was observed in the low resistance state (LRS), and space charge limit current (SCLC) conduction for its high resistance state (HRS). Secondly, using a ZnO ceramic target undergoing reactive RF magnetron sputtering deposition with doping of different metals and a further annealing process with and without nitrogen to compare the characteristics of the Al/(Al-doped ZnO)/Al and the Al/(Ti-doped ZnO)/Al RRAM structures. It can be observed that the former structure undergoing annealing reveals lower leakage current, switching cycles of 144, better switching stability, operating voltage less than 4.5V, and a retention time of 104 s. It can also be seen that it is ohmic conduction in both its HRS and LRS. For the study of stack structure of ZrO2/Al2O3/ZrO2 (ZAZ) high-k gate dielectric, various temperatures of post dielectric deposition annealing (PDA) or post metal deposition annealing (PMA) were used to study the characteristics of ZAZ high-k gate dielectric. From the electrical and capacitance-voltage (C-V) curve analysis, PMA500°C treatment reveals the higher dielectric constant than that of as-deposited sample (38 vs. 25).
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Chang, Wei-Chen, and 張緯宸. "Investigate the Effect of Ti Incorporation on NiO RRAM." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/06458419759954809393.
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碩士國立交通大學
電子研究所
98
Abstract For the coming of digital generation, nonvolatile memory (NVM) plays an important role in our life, especially for portable electronic products, such as the mobile phone, digital camera, and notebook etc. However, the problems of scaling limit for NVM are getting worse and serious for the CMOS technology under 40 nm [1-3]. Because the problems such as the retention time of NVM memory, scaling thickness of tunnel oxide, and the high program/erase (P/E) voltage increase the electrical field in tunnel oxide layer would deteriorate the endurance etc, the next-generation NVM memory is imperative. Therefore, the next-generation nonvolatile memories such as FeRAM, PCRAM, RRAM etc, have attracted extensive attention due to the conventional memories that approaching their scaling limits. Resistive switching phenomena have been observed in many materials, which can be roughly categorized into four groups (1) organic molecular materials, (2) solid state electrolytes (or called programmable metallization cell), (3) perovskite structures such as SrZrO3 (SZO), SrTiOx and Pr0.7Ca0.3MnO3, and (4) transition metal oxides (TMOs) such as NiO, TiO2, ZrO2, Cu2O, and etc. Base on the cheaper and simple structure of Ni material, Samsung have been investigated NiO RRAM for many years since 2004. There are still many important unresolved problems, including the original resistive switching mechanisms and the reliability issues (such as endurance test, reset failure, and variations of resistive switching parameters), which are all needed to be identified before realizing commercial applications. The major goals of the dissertation are to give more insights into these issues and find solutions to them. Here, we focus on the NiO RRAM and investigate for application. In our experiment, we fabricated successful NiO RRAM at high temperature depositional conditions at first, according to the different process of sample; we measured the electrical properties and thermal effect etc. After that, we try to fabricate NiO RRAM at RT by Ti incorporation for comparing and investigating the role of Ti in NiO RRAM. Finally, we have successfully fabricated NiO RRAMs using NiO deposited at 560℃ and Ti-doped NiO deposited at room temperature by dc reactive sputtering. Accordingly, we compare the NiO and Ti-doped NiO samples at all kind of characteristics. Based on the XRD and XPS analyses, it was found that the NiO (200) orientation and the suppression of the Ni2O3 state play important roles on the switching properties of the Ti-doped NiO RRAM. However, the retention of high resistance state in the Ti-doped NiO RRAM is degraded by the excess non-lattice oxygen defects.
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Wang, Tai-fang, and 王泰方. "Electrode Effect and Device Scaling of ALD Bilayer RRAM." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/45617699920946071678.
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碩士國立交通大學
電子研究所
105
Abstract We are living in an era of information explosion. The development of cloud storage/ computing and mobile internet drives the strong demand for more powerful data center facilities. The strong demand on increasing storage ability indicates the market of nonvolatile memory is permanent and broad, no matter based on commercial or personal users’ requirements. Because the knowledge that human being creating is growing in an exponential speed. The demand of more powerful and affordable memory device stimulated the active research of new generation memory device in the world. At present time, mass data storage in data centers still strongly relies on HDD, thanks to its high reliability and cheap price. In recent years, because of the considerable technology improvement on SSD and its significant cost reduction after successfully commercialization, some performance-sensitive critical system nodes start deploying the SSD technology. Recent advances of 3D-VNAND spearheaded by Samsung, intel, and Toshiba become another hot technology. The research on memory device is in an unprecedented progress. However, NAND has its inherent shortcomings: long access time(>1μs), large operational voltage(>10V), poor endurance (<106 cycles), device scaling limitation(>15nm). All of these generate significant interests on the development of next-generation nonvolatile memory. Among the numerous new-generation nonvolatile memory technologies, resistive random access memory gradually emerges as the most promising one because of its simple structure (metal-insulator-metal), fast switching speed(<10ns), excellent potential for future scaling(<10nm). Furthermore, a 3D VRRAM structure, which could be a serious contender of 3D-VNAND, has been demonstrated. In this thesis, based on Atomic Layer Deposition(ALD) process, HfO2/TiO2 bilayer RRAM devices were successfully fabricated. The top electrode was found to be a critical knob for tuning device electrical properties. Different work functions and reactiveness of metals were considered to find a suitable top electrode material. In addition, comprehensive measurement protocols of pulse measurements were established using waveform generator/fast measurement unit(WGFMU). Based on the Ni electrode and Al doped TiO2 film, the scalability of ALD bilayer RRAM was investigated. The process optimization improves many aspects of our ultra-thin ALD bilayer RRAM device based on non-filamentary switching mechanism, including the thinnest oxide layer (6nm), small operation voltage(<3V), good endurance (>107 cycles). This work shows the proposed device is a suitable device for analog synaptic devices or storage class memory application. Future development directions are also presented in this thesis.
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Chi-HsienChang and 張啟賢. "A Robust Sense Amplifier for 3D Vertical RRAM Macros." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/23883329305981282634.
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Chen, Jyun-hao, and 陳君豪. "Process Development of Metallic Oxide Films for Nonvolatile RRAM." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/93578360598096574360.
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碩士雲林科技大學
光學電子工程研究所
98
The advantages of resistive memory (RRAM) include low power consumption, low voltage operation, high-speed read and write, structure simplification, non-destructive read and non-volatile, suitable for mass production, and compatible with semiconductor BEOL, that makes the resistive memory as the leading candidate for the next generation of non-volatile memories. However, there are still no evident interpretations for the resistive switching mechanisms up to date. In this study, RF magnetron sputtering was used to fabricate the tantalum oxide (Ta2O5) film which acts as the dielectric layer in the resistive memory, and the titanium nitride (TiN) film which acts as the lower electrode in the resistive memory. Two photolithography steps were used to define the size of the resistive memory between 0.2 ~ 8μm. The platinum (Pt) was used as the other electrode to form the Pt/Ta2O5/TiN structure in the RRAM devices. In this work, bipolar resistive switching mechanism of the RRAM has been identified with the electrical measurements. Different process gases have been examined to observe their effects to the resistive switching mechanism of the RRAM. The operating voltage, endurance, and retention time of the RRAM devices have also been investigated.
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Feng, Jun-Jea, and 馮俊傑. "Electrical analysis in MgO thin film based RRAM device." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/93534185198717773291.
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碩士銘傳大學
電子工程學系碩士班
99
In this work, metal-insulator-metal (MIM) capacitors with MgO dielectrics were fabricated and investigated for non-volatile memory application. MgO thin films were prepared by radio frequency magnetron sputtering. The dominant conduction mechanism in the dielectric thin film is the hopping conduction at electric field higher than about 0.25 MV/cm at high resistive state. Meanwhile, the dominant conduction mechanism in the dielectric is the Ohmic conduction at electric field lower than about 0.2 MV/cm at low resistive state. The reliability characteristics of Pt/MgO/Pt devices were studied including endurance, data retention and reading durability. And the resistance switching model was discussed and observed by DC electric characteristics.
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-Yu, Tse, and 林則余. "Resistance Switching Characteristics of Zirconium Oxide Resistive RAM (RRAM)." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/02095413327082937616.
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Lee, Cheng-Hung, and 李承鴻. "Investigation on ZrO2-based RRAM with metal-oxide selector." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/8zrt8f.
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Xu, You-Lin, and 許宥林. "Switching characteristics and mechanisms of the Oxide-based RRAM." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/78bhsh.
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碩士國立中山大學
材料與光電科學學系研究所
107
Researches has reported that ITO electrode can effectively improve the performance of RRAM device, we intend to introduce ITO layer into the switching layer to realize the performance improvement. Additional, the relatively insulated In2O3 film, which have the ITO characteristic, has been the candidate to sever as the insert layer. Compared with single layer HfO2-based RRAM, the performance of Pt/HfO2/In2O3/TiN memory was effectively improved, including reducing operation current as well as enlarging the memory window . Based on the I-V curve fitting analysis, the conduction mechanism changed, infer that is attributed to the defect in In2O3 thin film . In particular, Both the HRS current and LRS current decreased with the increase of the forming current which would be beneficial for the design of low power device. Possible RS mechanisms and model aiming to explain the impact of forming current on the RS characteristics was also deduced. In recent years, resistive random access memory(RRAM) has been extensively studied due to its potential of small unit size (increased density), low operating voltage, low energy consumption, simple structure, non-destructive reading, fast operation, long data storage time and reliable operation. Nowadays, among the materials with resistive switching (RS) characteristics, binary metal oxides based RRAM, have been hotly investigated, owing to the advantages of simple composition, low operating power, fast switching speed. As we all know, silicon oxide (SiO2) has been widely applied in many electronic devices due to its excellent compatibility with integrated circuit (IC) processes. Unfortunately, for the RRAM application, there is no any RS behavior occurred in SiO2 layer. It was reported recently that Ni doped into SiO2 by co-sputtering at room temperature was taken as the RS layer of RRAM, and the device showed good characteristics. In this work, we choose another transition metal hafnium (Hf) as the dopant element into the SiO2 layer to investigate the RRAM characteristics. Undoubtedly, Hf doping SiO2, is rather compatible with IC processes and expected to be widely applied in the memory products. Based on the conducting filament (CF) theory, the switching behavior of RRAM is dependent on the CF morphology, formation (disruption) in SET (RESET) process, which in turn influences the performance of the device. In fact, SET process is decisive to the CF. Therefore, if we control one parameters of the CF condition, different RS behavior will be extracted. In this study, we will discuss the impact of SET current on the RS characteristics of Pt / Hf：SiO2 / TiN RRAM. As the transistor shrinks, the withstand voltage becomes smaller. For the memory, the forming voltage is also necessary to be reduced. Therefore, the thinner component of the intermediate layer is used to reduce the forming voltage, and the thinner component of the middle layer is also changed. The current limiting experiment was used to analyze and found that the electrical components were different from the thicker layers in the middle layer. Therefore, the two thickness components were compared, and it was found that the thickness of the intermediate layer affected the degree of the chain reaction, resulting in different resistance wires, which in turn affected Switch characteristics.
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詹為量. "Investigation of Resistive Switching Characteristics of a-AlZnSnO Based RRAM." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/zs9c95.
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Chia-JungShih and 施家絨. "RF Sputter Deposition of NbOx Thin Films for RRAM Applications." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/dq6b4e.
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ZHANG, YU-XUAN, and 張煜軒. "Fabrication of ITO-Based Point-Contact RRAM and Improvement Thereof." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/3bq8c4.
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碩士國立高雄應用科技大學
電子工程系
105
Point-contact Al/ITO structures were fabricated to investigate their resistive switching (RS) properties in air. The control Al/ITO sample needs a very large current (about 608 mA) to induce joule heat and to form an interface layer between Al and ITO, which initializes the RS. The resistance state of the control sample can be reversibly switched between a low-resistance state (LRS) and a high-resistance state (HRS) by voltage sweeping. The resistance states can remain for a long time without power supply, which can be used for non-volatile memory (NVM) applications. According to resistance switching behavior and temperature coefficient of LRS resistance, the switching mechanism is dominated by oxygen vacancies. However, the large forming current caused high power consumption and unstable switching behavior. A low forming current and a stable oxygen status are very important for a stable RS. Several methods such as plasma treatments, thermal annealing, and metal materials, were used in this study to improve the RS properties. Oxygen and argon plasma treatments were adopted to modify the ITO surface. After plasma treatment, oxygen status of the ITO surface was changed, and thus a lower current was needed to form the interface layer. Hence, the RS was more stable than that of the control sample. Post metal annealing was also used to form an interface layer and thus the forming current was very low. Thus, the RS of the thermal-anneal sample was stable. The thermal-annealing sample has good retention (>104 s) and good endurance (>100 cycles), which is suitable for NVM applications.
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Lin, Huan-Min, and 林桓民. "Study of Cu Role in the TiO2-Based RRAM Devices." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/12317446240431562630.
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碩士國立交通大學
電子研究所
100
Resistance random access memory (RRAM) has been regarded as a new generation memory. Owing to the simple structure and fabrication process, it has a great potential to replace the traditional flash memory and become the most popular memory in future. RRAMs show the well performance in many respects, however, it still has drawbacks such as no certain mechanism, short endurance, and unstable current in high resistive state (HRS). In this thesis, we proposed two methods to improve the performance of titanium dioxide (TiO2) based RRAM devices with the application of copper. First, we demonstrated the RRAM device fabricated by the oxidized copper electrode and the titanium dioxide active layer. The copper electrode has been oxidized by a rapid thermal oxidation (RTO) system, and formed the cupric (CuO), cuprous (Cu2O) and the metallic Cu in the oxidized electrode. The formed CuO serve as the Cu ions blocker and control the conduction filaments (CFs) . On the other hand, the formed Cu2O and the metallic Cu could play the role of Cu ions source for constructing the CFs. We could control the amounts of Cu ions to reduce the residual Cu ions in the active layer and the HRS current by adjusting the ratio of three compositions (CuO, Cu2O and Cu) in the electrode. Furthermore, the electrode surface roughness would affect the repeatability of the SET/RESET process. The CFs path could be constructed at several fixed positions because the enhanced local electric field at the tips during the RTO process. Consequently, we optimized the endurance and the ratio of low resistive state current to high resistive state current via an appropriate RTO process. The optimization samples in this work achieve 3 orders of LRS/HRS current ratio, endurance of 1000 cycles, and retention of 10000 seconds. Secondly, the RRAM devices fabricated by the co-deposited TiO2:Cu active layer and the platinum electrode have also been demonstrated in this research. The TiO2:Cu active layers were deposited by the co-sputtering titanium and copper targets with 30% oxygen partial pressure of the argon-oxygen mixed sputtering gases. The ratio of the compositions Cu to Ti in the active layer could be adjusted by the variable sputtering powers. Thus, the TiO2:Cu samples might exhibit lower SET/RESET voltage than the RTO Cu/TiO2 samples by the appropriate proportion of mixed CuO, Cu2O and Cu in the TiO2 active layer. It is because the Cu drift lengths for constructing the CFs is shorter than the RTO Cu/TiO2 samples. TiO2:Cu sample has the optimization condition when the co-sputtering power is 190W of Ti and 10W of Cu. It achieved 1 orders of LRS/HRS current ratio, endurance of 1000 cycles, and retention of 10000 seconds, with the operation SET/RESET voltages of -5V/2V. In this thesis, the simple-processed RTO Cu/TiO2 and co-deposited TiO2:Cu samples could achieve the good performances of RRAMs. Furthermore, the ratio of CuO, Cu2O and Cu compositions played the important role in the characteristics of the TiO2-based RRAM with copper according to ours results and discussion.
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Lu, Yueh-Po, and 盧岳伯. "Characterization of Switching in ZrOx /HfOx Bi-layer RRAM Devices." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/88655115523819006448.
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碩士中華大學
電機工程學系碩士班
99
Well progressive elaboration of infrastructure plus highly commercial progress of potable electrical product leading the tremendous market growth of nonvolatile memory market. In nearly years, conventional Flash is approaching very difficult issues related their continued scaling down because of its intrinsic storage mechanism. And it is essential to find out next generation NVM device. In this paper, we success demonstrate resistive switching behavior of ZrOx/HfOx bi-layer insulator in MIM structured memory device, those materials are extensively adopted in High-K CMOS process, and each material has various reaches in RRAM field. We also perform ZrOx /HfOx bi-layer annealing cause to lower operation condition and also identify the mechanism of which device can be explained by SCLC theory using double-logarithmic plot fitting to experiment result.
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Chen, Chan-Cheng, and 陳展承. "Electrical properties of NiO bipolar Resistive Random Access Memory (RRAM)." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/02010823156764631397.
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碩士國立臺灣大學
物理研究所
100
In this thesis, a resistive random-access memory was fabricated by using the nickel oxide, grown by thermal evaporation followed by an annealing process at different temperatures, as the dielectric layer sandwiched between the p-type silicon substrate and the aluminum contact. Atomic force microscopy and X-ray diffraction analysis were carried out for the investigation on the surface morphology and the crystalline structure of the grown nickel oxide, respectively. It was revealed that the annealing temperature and the oxygen flow were crucial to the electrical property of the nickel oxide layer. From the experimental results, it was found that the values of high-resistive and low-resistive states will increase with the incremental annealing temperature but decrease with the increasing oxygen flow rate at the optimized annealing temperature. It was also observed that the surface morphology is the key factor for stabilizing the operation of the resistive random-access memory. The results indicated that a nickel oxide film with a rougher surface morphology will greatly improve the lifetime and the reliability of the device. Resistive random-access memory is presently a developing subject for solid state devices and aimed to replace dynamic random-access memory and flash memory. The results in this thesis indicate that the stability and persistence of the resistive random-access memory devices will be the fundamental challenges for its future development.
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林杰融. "Adjustable Low-frequency Noise Generator by Nano-scale Contact RRAM." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/87237424776219538708.
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碩士國立清華大學
電子工程研究所
101
According to the prediction of Moore’s law, the number of components in integrated circuits double every two years. Performance betters with decreasing cost per chip for scaling down of device. It is accurate even for now. However, there are many new challenges when gate length scales from 0.18µm down to 10nm. One of the key issues is how to deal with the increasing impact of low frequency noise on scaled device. The low frequency noise , which received more and more attention in recent years, causes the unpredictable results in memory and RF circuits. On the other hand, low frequency noise is directed to unique applications, such as random number generator, artificial neural network, stochastic resonance, and temperature detector, etc. In this paper, we present a novel low frequency noise generator with voltage control modulation based on contact resistive random access memory (CRRAM), which has small area and full compatibility with advanced CMOS logic process. The 1/f noise and random telegraph noise(RTN) characteristics of CRRAM has been investigated for possible application as a noise generation source. An adjustable noise generator has been demonstrated to provide noise power at levels changed several decades for applications in stochastic neuromorphic computation.
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Hsu, Ching-Hui, and 許沁卉. "Investigation of Resistive Switching Characteristics of a-IGZO based RRAM." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/96870774217831623741.
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碩士國立交通大學
顯示科技研究所
101
Recently, nonvolatile memory (NVM) has been widely used in electronic devices. Nowadays, the prevailing NVM is Flash memory. However, it is generally believed that the conventional Flash memory will approach its scaling limit within about a decade. The resistive random access memory (RRAM) is emerging as one of the potential candidates for future memory replacement because of its high storage density, low power consumption as well as simple structure. The purpose of this thesis is to develop a reliable a-InGaZnO based resistive switching memory. We investigate the resistive switching characteristics of TiN/T i/IGZO/Pt structure and TiN/IGZO/Pt structure. The device with TiN/Ti/IGZO/Pt structure exhibits stable bipolar resistive switching. The impact of inserting a Ti interlayer is studied by material analyses. The device shows excellent resistive switching properties. For example, the DC sweep endurance can achieve over 1,000 times; and the pulse induced switching cycles can reach at least 10,000 times. In addition, we demonstrate the possibility of MLC operation for the device. By controlling the compliance current, multi-level operation can be achieved. Furthermore, the impact of different sputtering ambient, the temperature instability, and the conduction mechanisms are also investigated. According to our experiments, we propose a model to explain the resistive switching phenomenon observed in our devices. Finally, because the whole fabricating process of the RRAM device is under room temperature, it holds the potential for flexible electronics applications. The TiN/Ti/IGZO/Pt RRAM device is fabricated on flexible stainless steel to test its flexibility and mechanical endurance. 
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Chung, Yu-Wen, and 鍾宇雯. "Investigation of a Novel Contact RRAM and Flash Hybrid Memory." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/94421395103350263964.
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碩士國立清華大學
電子工程研究所
102
Recent years, the small volume and large capacity storage devices have become a popular research with the popularization of electronic products. Flash is the mainstream non-volatile memory the present day, which have suffered from leakage and high operation voltage with the process scale down. However, these challenges advance the more new research about new memory. This thesis has proposed a Novel Contact RRAM and Flash Hybrid Memory (FCRRAM) which is fabricated by advances 50nm flash memory process. This memory cell is fully compatible with flash process. The deposited TiON RRAM film is sandwiched by tungsten contact and heavy doped n-type silicon in 1D+1R structure. With proper operation, CRRAM can switch between high resistance state and low resistance state and flash can independently inject and remove electrons in floating gate by Fowler-Nordheim (FN) tunneling. Therefore, this memory can have MLC density with SLC reliability and performance to realize high density application. In addition, excellent FCRRAM cell performance including 10M endurance, stable data retention under 150oC for 1000 hours, and cell immunity from disturbance support this new memory to be a promising candidate for high density storage application.
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Mai, Syuan-Hao, and 麥軒豪. "Characteristics of TiOx Based RRAM Device Fabricated by Thermal Oxidation." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/18614296664718260561.
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碩士國立東華大學
電機工程學系
99
Most of the proposed TiOx-based resistive random access memory (RRAM) devices were fabricated by RF sputtering or atom layer deposition. However, in this thesis, the TiOx film was prepared by thermal oxidation method. The thermal oxidation method has many advantages such as low cost and simple fabrication process. First, a 50-nm-thick Ti metal film was thermally oxidized into a TiOx film in O2 ambiance at 550oC for 15min. After that, the TiOx film was annealed at 600oC for 1min by rapid thermal annealing. Then, the crystallization and the microstructure of the TiOx film were determined by X-ray diffraction and scanning electron microscopy, respectively. Finally, the effect of Al and Cu top electrode on resistive switching properties of the TiOx-based RRAM device was investigated. The Al/TiOx/Pt and the Cu/TiOx/Pt devices show bipolar switching characteristics. According to the experimental results, the Al/TiOx/Pt device, in comparison with Cu/TiOx/Pt device, exhibits good resistive switching properties, such as good endurance (over 300 cycles), low reset voltage, low set voltage, and large current ratio. In this case, the redox reaction at the Al top electrode and TiOx film interface leading to the good resistive switching properties are discussed. In the thesis, chapter 1 is the introduction and research motivation. Chapter 2 introduces the next generation non-volatile memories and the development of RRAM. Chapter 3 presents the device fabricating process and the electrical measurement methods. Chapter 4 discusses the effect of Al and Cu top electrodes on TiOx-based RRAM device. Chapter 5 is the conclusions of the most important results.