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Dissertations / Theses on the topic 'Rsa decryption'
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1
Lisoněk, David. "Šifrování SMS pro mobilní komunikaci." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2008. http://www.nusl.cz/ntk/nusl-235448.
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This thesis deals with encryption of short text message (SMS) in mobile communication. Introduction is dedicated to overview of the parts of GSM radiotelephone nets and SMS messages transfer . Next chapter is reserved for description of cryptographic methods especially symetric and asymetric encryptografic aproaches. A design of a SMS messages encryption and decryption techniques is in next. For SMS encryption and sign, there is used the asymetric cypher RSA. Encryption use OAEP padding schema. The public key is saved in certificate. The Symbian OS has been choosen as a suitable platform for programming of mobile devices.
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Joseph, George. "Design and implementation of high-speed algorithms for public-key cryptosystems." Diss., Pretoria : [s.n.], 2005. http://upetd.up.ac.za/thesis/available/etd-06092005-122043.
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Alzaabi, Mohamed Abdulla Hasan Saif. "New cryptanalysis and modelling for wireless networking." Thesis, University of Hertfordshire, 2015. http://hdl.handle.net/2299/17115.
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High data rates and interoperability of vender devices have made WiMAX a prime desire for use worldwide. WiMAX is based on the IEEE 802.16 standard. IEEE 802.16a, b, c & d versions were updated within three years of the first launch of WiMAX. However, during those early years reports were published that highlighted the security weaknesses of the standard. These weaknesses prompted the IEEE to issue a new version, 802.16e to tackle the security issues. Despite this security enhancement, WiMAX remains vulnerable. This research project looks at the vulnerability of WiMAX 802.16e Subscriber Station/Mobile Station authentication at the initial entry and proposes approaches to the prevention of Denial of Service (DoS) attacks at this point in order to secure the Media Access Control (MAC) layer from such threats. A new protocol has been designed and developed to provide confidentiality, authentication and integrity to WiMAX users. This new protocol is integrated with Z algorithm (an algorithm described later in this paper) to provide: • Confidentiality of management messages • Message Authentication code • ID to provide for message integrity and user authentication. A simulation package was also required, to prove that a linear load of DoS attack would disable or exhaust the capacity of the base station of a WiMAX network, as well as providing other simulation functions. The freely available simulation tool NIST (NIST IPSec (Internet Protocol Security) and IKE (Internet Key Exchange) Simulation) is oriented towards fixed network communications (NIIST, 2003). There are no other relevant simulation tools; hence the purpose of this research project is to develop a new tool to simulate WiMAX security vulnerabilities and test the new protocol.
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Luque, González Jorge, and Fernandez Ignacio Arenchaga. "Data Encryption on a Network." Thesis, Linnéuniversitetet, Institutionen för datavetenskap, fysik och matematik, DFM, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-9352.
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In this project you can find a study about different encryption algorithms, which are use to safeguard the information on messages over the network. We have developed a client-server application which will send information through the network which has to be secured. There are two kinds of encryption algorithms, the symmetric and the asymmetric key algorithms. Both were used to establish the communication, the asymmetric algorithm (RSA) is used to set up a symmetric key and then, all the communication process is done only with the symmetric algorithm (Blowfish).En este proyecto encontraras un estudio sobre diferentes algoritmos de encriptación, que son usados para salvaguardar la información en mensajes por la red. Además hemos desarrollado una aplicación cliente-servidor que enviara información a través de la red de forma segura. Hay dos tipos de algoritmos de encriptación, los simétricos y los asimétricos. Ambos tipos de algoritmos son utilizados para establecer la comunicación, el asimétrico (RSA) es utilizado para establecer la clave del simétrico y a partir de entonces se utilizara exclusivamente el algoritmo simétrico (Blowfish).
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Scarlato, Michele. "Sicurezza di rete, analisi del traffico e monitoraggio." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2012. http://amslaurea.unibo.it/3223/.
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Il lavoro è stato suddiviso in tre macro-aree.
Una prima riguardante un'analisi teorica di come funzionano le intrusioni, di quali software vengono utilizzati per compierle, e di come proteggersi (usando i dispositivi che in termine generico si possono riconoscere come i firewall).
Una seconda macro-area che analizza un'intrusione avvenuta dall'esterno verso dei server sensibili di una rete LAN.
Questa analisi viene condotta sui file catturati dalle due interfacce di rete configurate in modalità promiscua su una sonda presente nella LAN.
Le interfacce sono due per potersi interfacciare a due segmenti di LAN aventi due maschere
di sotto-rete differenti. L'attacco viene analizzato mediante vari software.
Si può infatti definire una terza parte del lavoro, la parte dove vengono analizzati i file
catturati dalle due interfacce con i software che prima si occupano di analizzare i dati di
contenuto completo, come Wireshark, poi dei software che si occupano di analizzare i dati di
sessione che sono stati trattati con Argus, e infine i dati di tipo statistico che sono stati trattati
con Ntop.
Il penultimo capitolo, quello prima delle conclusioni, invece tratta l'installazione di Nagios, e
la sua configurazione per il monitoraggio attraverso plugin dello spazio di disco rimanente su
una macchina agent remota, e sui servizi MySql e DNS. Ovviamente Nagios può essere
configurato per monitorare ogni tipo di servizio offerto sulla rete.
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Chang, Chien-Cheng, and 張建誠. "The Design of a RSA Encryption/Decryption Circuit." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/61393486894775458082.
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碩士國立臺灣科技大學
電子工程系
88
The RSA encryption algorithm is widely used in communication and data security system. It takes much time to perform because of the RSA algorithm using more than 512-bit word lengths to guarantee security. Developing a high speed RSA encryption circuit which takes less gate count and can carry out its layout easily, will be a challenge. In this thesis, a 1024-bit RSA encryption circuit that is constructed by two 1024-bit adders is proposed. Based on the consideration of speed and regularity, a 1024-bit hierarchical carry skip adder consisting of 8 bits ripple adders is proposed. The adder only takes 9.4ns to perform a 1024-bit addition with 0.35μm SPQM cell library. The resulting RSA circuit can output a 10240-bit encrypted message every 22ms at the operating frequency of 72 MHz. Its die size is 3.7x3.7mm^2 and consumes 633mw. Moreover, the design of the proposed RSA circuit is modularized in a bit-sliced manner so that it can be expanded easily to a longer word length.
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Jwo, Hung-Ming, and 卓宏洺. "Research of RSA Encryption/Decryption Based on Embedded System." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/tcf94z.
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碩士國立臺灣科技大學
電子工程系
94
Human life gets more and more dependent on internet as it grows rapidly. By means of internet, we can not only transfer text, audio, and video data, but also buy goods and pay for them. But in a public domain like internet, private personal information can be captured easily and therefore encryption is necessary to prevent captured data readable. Based on a developing platform with Samsung S3C2410 as its CPU, this thesis develops a internet transfer application that encrypts files with RSA before sending out via internet, and decrypts them after receiving at receiver end. RSA is currently the most popular public key cryptographic system. It's quite appropriate to use when transferring private information under public domain and it can also be used for digital signature and identification certification. S3C2410, a touch-panel-supported CPU produced by Samsung, is considered suitable for mobile devices such as PDA. Linux, the operating system we use on the developing platform, is capable of great portability, efficient network transfer, support for a great deal of peripherals, and short time to market, and most important of all is that it's open source.
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陳嘉耀. "An Efficient Decryption Method for RSA Cryptosystem And Implementation." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/71835300207564971666.
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Bih-Ching, Yeh. "512-bit RSA Public Key Data Encryption/Decryption Chip Design." 1997. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611290358.
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Zeng, Xi-Zhe, and 曾希哲. "The Design and Analysis of a RSA Encryption/Decryption Chip." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/36112321014998661900.
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碩士國立海洋大學
電機工程學系
88
The role of cryptography is more important to prevent the computer- and communication-based crime in recent years. Many applications of cryptographic methods have been proposed recently from electronic mail, trading, and banking to network security. In this thesis, the implementation of a 512 bits public key cryptosystem of RSA encryption/decryption chip is presented based on the Montgomery algorithm to simplify the complexity of exponential modular operation in RSA algorithm. The architecture of chip includes two components: modular and multiplier that are implemented based on the 257 bits pipelining systolic array to achieve a low die area. We applied the VHDL (VHSIC Hardware Description Language) to accomplish its design entry. This chip completed by using FPGA (Field Programmable Gate Array). It’s clock rate can reach 43.5 MHz and the baud rate is 28.2 Kbits/sec.
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Chen, Taoan, and 陳道安. "The Implement of a 1536 bits RSA Encryption/Decryption Chip." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/51664063897658558255.
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碩士國立海洋大學
電機工程學系
89
It is obviously that security issues will play an important role in the majority of future computer and communication systems. Cryptographic algorithms and their software/hardware implementations are the major tools to achieve the system security. In this thesis, a 1536 bits RSA encryption/decryption chip based on the Montgomery algorithm is presented. The main structure of this chip includes an encryption/decryption module and a 64K*32 SRAM. The 32 bits encryption/ decryption module is implemented using Altera EFP10K200SRC240-1. Based on the same structure, a 1536 bits encryption/decryption module can be constructed easily using Altera EP20k400EBC 652-1 and has the expected 8.86 Kbps baud rate at the 40.83 clock rate.
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Huang, Ching-Min, and 黃靖閔. "Design and Implementation of 1024-bit Systolic RSA Encryption/Decryption Chip." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/24237273771142804259.
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碩士國立臺灣大學
電機工程學研究所
88
With the increasing popularity of electronic communications, data security is becoming a more and more important issue. There are two main types of cryptosystems. One is private-key cryptosystem, and the other is public-key cryptosystem. The most famous and popular public-key cryptosystem is RSA scheme. RSA scheme is composed of large bit-length modular multiplication and modular exponentiation in principle. Because of the high complexity of modular exponentiation, it is very difficult to factor it and obtain the private-key from the public-key. Montgomery suggested an efficient method for faster modular multiplication, and the algorithm is suitable for hardware implementation. Many paper proposed modified Montgomery''s algorithms to achieve better hardware usage and less operation time. Our RSA encryption/decryption chip basically follows the modified Montgomery''s algorithm proposed by Yang in 1998. This chip is composed of five units: serial-parallel multiplier, modulus systolic array, RAM controller, RAM module, and exponentiation controller. All 1024-bit data computations are divided into 32-bit data processing. The chip is implemented using 0.35um 1P4M CMOS technology.
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Lai, SUAN-YUAN, and 賴士元. "The Design and Verification of a RSA Encryption/Decryption Intellectual Porperty." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/41241755407620563913.
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碩士國立臺灣科技大學
電子工程系
93
The success of high-performance computers and high-speed networking brings us a high-speed information-exchanging network. People begin to setup electric commercial platform and transfer important information on the Internet. Since the Internet is a public channel, the networking security becomes an important issue now. In order to prevent the information from being stolen or modified by unauthorized ones, we need some high security device to protect our information on networking systems. In this paper, we focus on the architecture design of a 1024-bit RSA encryption/decryption algorithm. The resulting IP has been verified by both FPGA and standard cell library. It can operate at 72 MHz, the area is 3.1 x 3.1 mm2, and bit rate is 35 kbps when it is realized by COMPASS 0.35 μm standard cells. The resulting chip can operate at 33 MHz, the area is 16,321 LCELLs, and bit rate is 17 kbps when it is realized by Altera FPGA device (EP20K600EBC652-1).
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Hsu, Rui-Ming, and 許瑞銘. "ISA Interface Card Design and Implementation for Scalable RSA Encryption/Decryption System." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/05476263004293254903.
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博士元智大學
電機工程研究所
88
In this thesis we present an ISA interface prototype card, which can work on PC, to process the RSA algorithm-based encryption/decryption system of scalable 512, 1024, and 2048 bits. With powerful hardware computation capability, this card executes the complex encryption/decryption operations, relieving the workload of the CPU, which in traditional implementation does the job by software, and thus promoting the processing performance on high security network communication. The designed interface card provides multiple key-pairs application for user. It includes the following parts: an RSA circuit to execute the modular exponentiation operations for RSA encryption/decryption and digital signature; the Key Generator circuit implements RSA key pair generation; the DES circuit makes the DES encryption/decryption for generated private key; on-board memory provides the storage of multiple key pairs; on-board battery provides the off-line power for memory; on-board processor controls the operation flow of internal circuit. It communicates with host using the traditional ISA interface. The working frequency is set to 20MHz, which is supported by on-board oscillator.
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Wu, Tsung-Han, and 吳宗翰. "Design of Timing-Error-Tolerant VLSI Circuits for RSA Encryption and Decryption." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/p868td.
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碩士國立東華大學
電機工程學系
102
As the feature size of chips shrinks with semiconductor technology advancing, the size of transistors and their operating voltage keep decreasing. One of the major problems with advanced semiconductor technology is timing errors caused by process variation and device aging. With such problems, conventional worst-case designs suffer poor system performance. This thesis proposes an aggressive design technique for VLSI circuits for RSA encryption and decryption for tolerating timing errors. We have developed a methodology of designing reconfigurable VLSI circuits for RSA encryption and decryption that can tolerate timing errors. The reconfigurable VLSI circuits for RSA encryption and decryption are resilient to any timing errors occurring at any stage and any time. When the timing error occurs, the system reconfigures the buffer cells of VLSI circuits for RSA encryption and decryption with little performance degradation. We have applied our technique to the VLSI circuits for RSA encryption and decryption designs. The implementation results show that our proposed designs achieve tolerance of timing errors with reasonable cost.
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Lin, Lokar J. Y., and 林政義. "The Design and Implementation of a 2048-bit RSA Encryption/Decryption Chip." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/07215889004767923673.
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碩士國立海洋大學
電機工程學系
91
Security and privacy is an important issue in the future. Cryptogra-phy is one of the key features of security. Using hardware implementation can provide faster and more secure solution than software implementation. Recently, the Internet is so popular in the world and the required bandwidth is as large as possible. The encryption of the digital data becomes more important. The powerful RSA cryptosystem can not only secure the data but also provide the function of the digital signature. This paper presents the design and implementation of a 2048-bit (about 617 decimal digits) RSA public key cryptosystem based on modified Montgomery algorithm achieving comparable clock cycles of current rele-vant works but with smaller die size. We use binary method for the modular exponentiation and adopt Walter algorithm for the modular multiplication to simplify the computa-tional complexity, together with systolic array concept for electric circuit designs effectively lower the die size. We applied the concept of systolic array to design this 2048-bit RSA encryption/decryption chip by using VHDL. The cryptosystem was imple-mented with the TSMC 0.35 μm process and its die size is 3.29×3.29 μm2. Average baud rate can reach 10.84 Kbps under a 100 MHz clock.
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Castell-Castell, Nikolaus, and Tom Tietken. "Possibilities to identify prime numbers without RSA decryption algorithm and to decipher RSA encryptions indirectly (using a special list)." 2021. https://slub.qucosa.de/id/qucosa%3A74372.
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Hsieh, Yong-Hsiang, and 謝永強. "Design and Implementation of an RSA Encryption/Decryption Processor for IC Smart Card." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/70312224310795702384.
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碩士國立臺灣大學
電機工程學研究所
87
As internet becomes popular today, more and more services will operate on internet, e.g., internet market, electronic bank, and electronic government. These services require high data security in network communication, such that encryption of data transfering between server and client is necessary. Higher data security indicates more complex cryptography computation. Two cryptosystems are using today for internet services, one is the symmetric-key cryprtosystem, and another is the public-key cryptosystem. The symmetric-key cryptosystem is used for information transfer, and the public-key cryptosystem is used for identification. For example, DES (Data Encryption Standard) algorithm is known as a symmetric-key cryptosystem, and RSA (Rivest-Shamir-Adelman) algorithm is a public-key cryptosystem. Though these two algorithms generate good data security, the amount of computations is very large, such that a general central processing unit (CPU) cannot timely complete the computations, and a hardware processor is required to assist CPU. In this Thesis, an RSA encryption/decryption processor is designed to assist a core microprocessor to compute the cryptographic operations. In order to satisfy the restriction of peak current and power consumption in IC Smart Card, a full custom design is used. Using the processor to compute a 1024-bit RSA data requires 0.4s on average.
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Chen, Jian-Kao, and 陳建國. "The Design of a 512-bit RSA Encryption/Decryption Chip with Novel Architecture." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/72618033934475815352.
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碩士淡江大學
電機工程學系
87
The application of the Internet is amazing and amusing. Nowadays, we can buy many items from the network, and life seems easier than several years ago. However, due to the opening characteristics of the internet the safety problems are always concerned by people. Everybody hates his/her credit card to be stolen by the network hiker. Therefore, the safety problem of the network is one of the most important problems needed to be solved nowadays. The most efficient solution is to use cryptographic to encode and decode the transmitted data. RSA cryptosystem is the best cryptographic that we have ever known. In the RSA cryptosystem, we need two keys, public key and private key, and we can associate these two keys to get safety data. The safety depends on the length of the key, and usually the longer the key the more safety the data will be. Generally we need at least a 512-bit key. The processing of the key is composed of many modulo multiplication and modulo addition. Due to the large number, the operation speed can not be real time by the software approach. Because of the development and advancing technology of the VLSI process, the RSA cryptosystem can be implemented in a VLSI chip. In the reported RSA cryptosystem architecture or chip, the hardware cost is still very high. In this thesis, we will try to use a new architecture to design the RSA chip. The gate count of this RSA chip is moderate but the speed is very fast.
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Lin, Chang-Cheng, and 林丈棖. "The Design and Implementation of a 512~2048 bit Scalable RSA Encryption/Decryption System." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/60502011058267231901.
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碩士元智大學
電機與資訊工程研究所
87
In this thesis we design a 512-bit to 2048-bit scalable RSA public key encryption/decryption system. The H algorithm is used to translate the modular exponentiation in a RSA cryptosystem into a sequence of Montgomery’s operations. And we can combine several 16-bit Montgomery’s modules into a complete Montgomery’s unit which can achieve n-bit Montgomery’s operation, where n can be any bit number of keys. The Montgomery’s Unit is designed in a fully pipelined architecture. Its complexity of time is O(n). And the Control Unit is designed in 256-bit, 512-bit, 1024-bit, and 2048-bit modes. It’s a complete RSA cryptosystem when the Control Unit is combined with a modularized Montgomery’s Unit with suitable bit length. The system clock is set to 25MHz. From the simulation result of Altera CPLD 6K series, it takes about 3*n2 clocks to finish an operation of a n-bit RSA encryption or decryption. For example, each encryption or decryption will take about 3*5122 clocks to calculate in a 512-bit RSA cryptosystem.
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Chang, Ming-Yi, and 張明義. "The Design and Implementation of an Encryption/Decryption chip Based on The RSA Scheme." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/22485824805327026083.
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碩士國立台灣工業技術學院
電子工程技術研究所
85
With the continuous growth of communication networks, data security is becoming more and more important. In this thesis, we design and implement a 128 bits encryption/decryption chip based on the RSA scheme. The main structure of the chip is a synchronous ring-pipelined system, containing two computing circuits: modulo and multiplier. These two circuits are designed with the serial RSD (redundant signed digit) full adder to achieve a high performance and the minimum hardware cost. The chip has been realized by using cell-based library technique. It occupies 4096x3265 um?chip area and has 97.7kbits/sec throughput for 128-b words at 125MHz. The power consumption is 1.66W. Based on the same structure, a 512 bits encryption/ decryption chip can be constructed easily and has the expected throughput 24.4kbits/sec at the same clock rate. The area for this chip is 6660x6640 um.
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Lin, Yu Shiang, and 林郁翔. "Efficient Constrained Multiple Sequence Alignment Tool and Parallel RSA Decryption Algorithm for Many-core GPUs with CUDA." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/30327752282957062719.
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碩士長庚大學
資訊工程學系
100
In this paper, we use CUDA technology to accelerate two applications by the computing resources of GPU which are the constrained multiple sequence alignment and accelerate the large integer factorization for RSA decryption. Multiple sequence alignments with constrains has become an important problem in the computational biology. The concept of constrained sequence alignment is proposed to incorporate the biologist’s domain knowledge into sequence alignments such that the user-specified residues/segments are aligned together in the alignment results. RE-MuSiC is a newest tool with the regular expression constrains and useful for a wide range of biological applications. However, the computation time of RE-MuSiC is large for a large amount of sequences or long sequences and this problem limits the application usage. Therefore, in this paper, a tool, GPU-REMuSiC v1.0, was proposed to reduce the computation time of RE-MuSiC by using the GPU with CUDA. GPU-REMuSiC v1.0 can achieve 29× speedups for overall computation time by the experimental results. The other application is about the cryptography. Cryptography is an important technique among various applications. RSA is a public-key cryptography algorithm to use a pair (N, E) as the public key and D as the private key. The N is the product of two large prime numbers p and q that are kept secret. It is very hard and no known polynomial time algorithms can be used to extract p and q from a large number N. Therefore, in this paper, we proposed an efficient parallel RSA decryption algorithm for many-core GPUs with CUDA. The experimental results showed that the proposed GPU-based algorithm can achieve 1197.5x average speedup compared with the CPU-based algorithm, and within a reasonable time to find out the result of factoring large numbers.