Relevant bibliographies by topics / RTL Design

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'RTL Design'

Author: Grafiati
Published: 4 June 2021
Last updated: 11 September 2023

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Journal articles on the topic "RTL Design"

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Jenihhin, Maksim, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, JorgeHernan Meza Escobar, and Heinz-Dietrich Wuttke. "Automated Design Error Localization in RTL Designs." IEEE Design & Test 31, no. 1 (February 2014): 83–92. http://dx.doi.org/10.1109/mdat.2013.2271420.

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SEMBA, Shogo, Hiroshi SAITO, Masato TATSUOKA, and Katsuya FUJIMURA. "Optimization Methods during RTL Conversion from Synchronous RTL Models to Asynchronous RTL Models." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E103.A, no. 12 (December 1, 2020): 1417–26. http://dx.doi.org/10.1587/transfun.2020vlp0004.

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Noji, Tamotsu, Keisuke Shimizu, Hideyuki Hamada, and Akira Nakamura. "Design and implementation of synthesis prediction in RTL design." Systems and Computers in Japan 27, no. 11 (1996): 41–52. http://dx.doi.org/10.1002/scj.4690271104.

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Madineni, Mukesh Chowdary, Mario Vega, and Xiaokun Yang. "Parameterizable Design on Convolutional Neural Networks Using Chisel Hardware Construction Language." Micromachines 14, no. 3 (February 24, 2023): 531. http://dx.doi.org/10.3390/mi14030531.

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This paper presents a parameterizable design generator on convolutional neural networks (CNNs) using the Chisel hardware construction language (HCL). By parameterizing structural designs such as the streaming width, pooling layer type, and floating point precision, multiple register–transfer level (RTL) implementations can be created to meet various accuracy and hardware cost requirements. The evaluation is based on generated RTL designs including 16-bit, 32-bit, 64-bit, and 128-bit implementations on field-programmable gate arrays (FPGAs). The experimental results show that the 32-bit design achieves optimal hardware performance when setting the same weights for estimating the quality of the results, FPGA slice count, and power dissipation. Although the focus is on CNNs, the approach can be extended to other neural network models for efficient RTL design.
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Jain, Nitika. "RTL Design of CISC CPU IP Core." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (June 30, 2022): 4620–24. http://dx.doi.org/10.22214/ijraset.2022.45067.

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Abstract: Recent developments on programmable logic technology had promoted the microprocessor design task from big companies targeting the mass market to the everyday designer as intellectual property (IP) cores toward the system on-a-chip (SOC) approach. This paper shows the VHDL IP 8-bit CISC microprocessor core development which is intended as an open core for teaching applications in the digital systems laboratory. The core is fully open and therefore, the user can have access to all internal signals as well as the opportunity to make changes to the structure itself which is very useful when lecturing microprocessor design. The main advantages of the present core, compared with commercially available equivalent cores, are that it is not vendor sensitive allowing its implementation in almost any FPGA family and being an open core, it can be fully monitored and modified to fit specific design constrains. Several tests were performed to the microprocessor core, including an embedded microcontroller with RAM, ROM and I/O capabilities. The present development includes a meta-assembler and linker to embed user programs in a ROM, which is automatically generated as a VHDL description
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Mück, T. R., and A. A. Fröhlich. "Aspect-oriented RTL HW design using SystemC." Microprocessors and Microsystems 38, no. 2 (March 2014): 113–23. http://dx.doi.org/10.1016/j.micpro.2013.12.002.

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Badawy, W. "Principles of verifiable RTL design [Book Review]." IEEE Circuits and Devices Magazine 18, no. 1 (January 2002): 26–27. http://dx.doi.org/10.1109/mcd.2002.981298.

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SEMBA, Shogo, and Hiroshi SAITO. "Conversion from Synchronous RTL Models to Asynchronous RTL Models." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A, no. 7 (July 1, 2019): 904–13. http://dx.doi.org/10.1587/transfun.e102.a.904.

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Kwon, Bo-Seung, Sang-Won Jung, Young-Dan Noh, Jong-Sik Lee, and Young-Shin Han. "RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool." Telecom 4, no. 1 (December 29, 2022): 15–30. http://dx.doi.org/10.3390/telecom4010002.

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DEVS (Discrete Event System Specification) is widely used in modeling and simulation fields to design, validate, and implement complex response systems. DEVS provides a robust formalism for system design using event-driven, state-based models with explicitly defined temporal information. We extend the RTL-DEVS model based on DEVS formalism to enable part of Verilog simulation in DEVS-based simulation tools. The simulation based on RTL-DEVS methodology, which imitates Verilog’s testbench and behavioral module, confirmed through experiments that RTL simulation can be performed sufficiently through the code elaboration process. In multiple simulation results, Verilog simulation and RTL-DEVS-based simulation were able to output equivalent results under limited conditions. DEVS formalism-based modeling can be extended to other DEVS-based simulators when using model-type exchange tools, and this means that the advanced functions or classes of RTL simulation tools can be applied using higher-level language tools.
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Gowda, Madhura Rame, and Jamuna Jamuna. "Fault simulation for design for testability inserted designs." Indonesian Journal of Electrical Engineering and Computer Science 29, no. 2 (February 1, 2023): 658. http://dx.doi.org/10.11591/ijeecs.v29.i2.pp658-668.

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<p>Systematic design for testability (DFT) is a technique to enhance the testability of design so that it is further organized and self-regulating. The objective of systematic DFT is to enhance a circuit's operability and evidence. This can be performed in a variety of ways. The scan pattern method is the extremely predominant, and it modifies the design's internal sequential circuitry. In this manuscript, frequently used industry standard functional register-transfer level (RTL) designs are chosen. Structured DFT approach is adopted to do scan insertion and automatic test pattern generation (ATPG) to enhance the testability. Proposed methodology provides the controllability and observability for the clocks and reset used in chosen RTL designs by eliminating S rule and D rule violations by adding test logic. Also able to insert stuck at faults and achieve fault coverage of 97.78% and test coverage of 99.26% for DFT architecture for Wallace tree multiplier design, and found different classes of faults as testable and untestable faults and also performed fault simulation for the intended designs to detect fault from the created deterministic patterns.</p>
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Dissertations / Theses on the topic "RTL Design"

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Kevorkov, Ruslan. "Sounding Rocket ExperimentElectronics – RTL Design and Validation." Thesis, KTH, Rymd- och plasmafysik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-149252.

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The Infrared Spectroscopy to Analyse the middle Atmosphere Composition (ISAAC) is an experimental module designed by KTH students. It consists of a Rocket Mounted Unit (RMU) and two Free-Falling Units (FFU) carried inside. The main objective of the experiment is to demonstrate ability of one FFU to track the other and to carry out measurements in cooperation. This Master’s thesis covers the development and implementation of the ejection system as well as data acquisition for the ISAAC experiment to have well-timed ejection of the FFUs and data for a post-flight analysis. Ejection control and communication is implemented in a Field-Programmable Gate Array (FPGA) using VHDL hardware description language. Newly developed firmware verification and the post-flight analysis results are also presented in the report. The ISAAC experiment was launched on May 29 from Esrange, Kiruna onboard the REXUS15 rocket.
ISAAC (Infrared Spectroscopy to Analyse the Middle Atmosphere Composition) är en raketmonterad experimentmodul designad av studenter på KTH. Modulen består av en raketmonterad modul benämnd RMU (Rocket Mounted Module), i vilken två mindre fritt fallande enheter benämnda FFU (Free Falling Units) sitter monterade. Huvudmålet med experimentet är att demonstrera förmågan för den ena FFU:n att spåra den andra FFU:n samt förmågan att genomföra koordinerade mätningar. Detta examensarbete behandlar utvecklandet och implementationen av utskjutningssystemet samt datainsamlingen för ISAAC -experimentet. Dessa delar görs för att kunna genomföra utskjutningen vid en lämplig tidpunkt samt få data till efterbehandling. Utskjutningskontroll samt kommunikatio n är implementerade i en FPGA (Field Programmable Gate Array) i det hårdvarubeskrivande språket VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language). Verifikation av nyutvecklad inbyggd programvara samt analysresultat av data från uppskjutningen presenteras också. Uppskjutningen av ISAAC-experimentet skedde den 29:e maj 2014 från rymdbasen Esrange i Kiruna ombord på raketen REXUS15.
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Jangid, Anuradha. "Verifying IP-Cores by Mapping Gate to RTL-Level Designs." Case Western Reserve University School of Graduate Studies / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=case1385975878.

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Shrestha, Gyanendra. "Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/44889.

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Globalization of semiconductor design and manufacturing has led to a concern of trust in the final product. The components may now be designed and manufactured from anywhere in the world without the direct supervision of the buyer. As a result, the hardware designs and fabricated chips may be vulnerable to malicious alterations by an adversary at any stage of VLSI design flow, thus compromising the integrity of the component. The effect of any modifications made by the adversary can be catastrophic in the critical applications. Because of the stealthy nature of such insertions, it is extremely difficult to detect them using traditional testing and verification methods. Therefore, the trust of the hardware systems require a new approach and have drawn much attention in the hardware security community. For many years, the researchers have developed sophisticated techniques to detect, isolate and prevent malicious attacks in cyber security community assuming that the underlying hardware platform is extremely secure and trustworthy. But the hardware may contain one or more backdoors that can be exploited by software at the time of operation. Therefore, the trust of the computing system cannot be guaranteed unless we can guarantee the trust of the hardware platform. A malicious insertion can be very stealthy and may only involve minor modification in the hardware design or the fabricated chip. The insertion may require rare or specific conditions in order to be activated. The effect may be denial of service, change of function, destruction of chip, leakage of secret information from cryptographic hardware etc. In this thesis, we propose a novel technique for the detection of malicious alteration(s) in a third party soft intellectual property (IP) using a clever combination of sequential equivalence checking (SEC) and automatic test generation. The use of powerful inductive invariants can prune a large illegal state space, and test generation helps to provide a sensitization path for nodes of interest. Results for a set of hard-to-verify designs show that our method can either ensure that the suspect design is free from the functional effect of any malicious change(s) or return a small group of most likely malicious signals.
Master of Science
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Nilsson, Jesper. "Mixed RTL and gate-level power estimation with low power design iteration." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1685.

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In the last three decades we have witnessed a remarkable development in the area of integrated circuits. From small logic devices containing some hundred transistors to modern processors containing several tens of million transistors. However, power consumption has become a real problem and may very well be the limiting factor of future development. Designing for low power is therefore increasingly important. To accomplice an efficient low power design, accurate power estimation at early design stage is essential. The aim of this thesis was to set up a power estimation flow to estimate the power consumption at early design stage. The developed flow spans over both RTL- and gate-level incorporating Mentor Graphics Modelsim (RTL-level simulator), Cadence PKS (gate- level synthesizer) and own developed power estimation tools. The power consumption is calculated based on gate-level physical information and RTL- level toggle information. To achieve high estimation accuracy, real node annotations is used together with an own developed on-chip wire model to estimate node voltage swing.

Since the power estimation may be very time consuming, the flow also includes support for low power design iteration. This gives efficient power estimation speedup when concentrating on smaller sub- parts of the design.

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Puri, Prateek. "Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/55815.

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Over the last two decades, chip design has been conducted at the register transfer (RT) Level using Hardware Descriptive Languages (HDL), such as VHDL and Verilog. The modeling at the behavioral level not only allows for better representation and understanding of the design, but also allows for encapsulation of the sub-modules as well, thus increasing productivity. Despite these benefits, validating a RTL design is not necessarily easier. Today, design validation is considered one of the most time and resource consuming aspects of hardware design. The high costs associated with late detection of bugs can be enormous. Together with stringent time to market factors, the need to guarantee the correct functionality of the design is more critical than ever. The work done in this thesis tackles the problem of RTL design validation and presents new frameworks for functional test generation. We use branch coverage as our metric to evaluate the quality of the generated test stimuli. The initial effort for test generation utilized simulation based techniques because of their scalability with design size and ease of use. However, simulation based methods work on input spaces rather than the DUT's state space and often fail to traverse very narrow search paths in large input spaces. To encounter this problem and enhance the ability of test generation framework, in the following work in this thesis, certain design semantics are statically extracted and recurrence relationships between different variables are mined. Information such as relations among variables and loops can be extremely valuable from test generation point of view. The simulation based method is hybridized with Z3 based symbolic backward execution engine with feedback among different stages. The hybridized method performs loop abstraction and is able to traverse narrow design paths without performing costly circuit analysis or explicit loop unrolling. Also structural and functional unreachable branches are identified during the process of test generation. Experimental results show that the proposed techniques are able to achieve high branch coverage on several ITC'99 benchmark circuits and their modified variants, with significant speed up and reduction in the sequence length.
Master of Science
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Ravinath, Vinodh. "Design and Implementation of Single Issue DSP Processor Core." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10160.

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Micro processors built specifically for digital signal processing are DSP processors. DSP is one of the core technologies in rapidly growing applications like communications and audio processing. The estimated growth of DSP processors in the last 6 years is over 40%. The variety of DSP capable processors for various applications also increased with the rising popularity of DSP processors. The design flow and architecture of such processors are not commonly available to students for learning.

This report is a structured approach to design and implementation of an embedded DSP processor core for voice, audio and video codec. The report focuses on the design requirement specification, senior instruction set and assembly manual release, micro architecture design and implementation of the core. Details about the core verification are also included in this report. The instruction set of this processor supports running basic kernels of BDTI benchmarking.

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Niu, Xinwei. "System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design." FIU Digital Commons, 2012. http://digitalcommons.fiu.edu/etd/888.

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Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.
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Motschull, Jan Even. "TV-Design als wichtiger Faktor für Programmverbindungen im deutschen Fernsehen Analysen und Vergleich zwischen den Vollprogrammsendern RTL, ProSieben und dem Spartensender VIVA zur Ermittlung von designerischen Grundsätzen im Fernsehen /." [S.l. : s.n.], 2005. http://deposit.ddb.de/cgi-bin/dokserv?idn=974085839.

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Prado, Rafael Nunes de Almeida. "Desenvolvimento de uma arquitetura em hardware prototipada em FPGA para aplica??es gen?ricas utilizando redes neurais artificiais embarcadas." Universidade Federal do Rio Grande do Norte, 2011. http://repositorio.ufrn.br:8080/jspui/handle/123456789/15342.

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Made available in DSpace on 2014-12-17T14:55:47Z (GMT). No. of bitstreams: 1 RafaelNAP_DISSERT.pdf: 1349793 bytes, checksum: 6843077c7952b1e58788ef395d9822e6 (MD5) Previous issue date: 2011-02-22
This work proposes hardware architecture, VHDL described, developed to embedded Artificial Neural Network (ANN), Multilayer Perceptron (MLP). The present work idealizes that, in this architecture, ANN applications could easily embed several different topologies of MLP network industrial field. The MLP topology in which the architecture can be configured is defined by a simple and specifically data input (instructions) that determines the layers and Perceptron quantity of the network. In order to set several MLP topologies, many components (datapath) and a controller were developed to execute these instructions. Thus, an user defines a group of previously known instructions which determine ANN characteristics. The system will guarantee the MLP execution through the neural processors (Perceptrons), the components of datapath and the controller that were developed. In other way, the biases and the weights must be static, the ANN that will be embedded must had been trained previously, in off-line way. The knowledge of system internal characteristics and the VHDL language by the user are not needed. The reconfigurable FPGA device was used to implement, simulate and test all the system, allowing application in several real daily problems
Prop?e uma arquitetura em hardware, descrita em VHDL, desenvolvida para embarque de redes neurais artificiais, do tipo Multilayer Perceptron (MLP). Idealiza que, nessa arquitetura, as aplica??es com RNA tenham facilidade no procedimento de embarque de uma rede neural MLP em hardware, bem como permitam f?cil configura??o de v?rios tipos de redes MLP em campo, com diferentes topologias (quantidade de neur?nios e camadas). Uma rede de comunica??o foi desenvolvida para fazer reuso de neur?nios artificiais. A defini??o da arquitetura MLP que o sistema proposto ir? se configurar e executar depende de uma entrada de dados espec?fica, a qual define a quantidade de neur?nios, camadas e tipos de fun??es de ativa??o em cada neur?nio. Para permitir essa maleabilidade de configura??es nas RNA, um conjunto de componentes digitais (datapath) e um controlador foram desenvolvidos para executar instru??es que definir?o a arquitetura da rede MLP. Desta forma, o hardware funcionar? a partir de uma entrada de instru??es previamente conhecidas por um usu?rio, as quais indicar?o as caracter?sticas de uma determinada rede MLP, e o sistema ir? garantir a execu??o da MLP desejada a partir dos neur?nios artificiais desenvolvidos para o sistema, pelo controlador e pelos componentes do datapath, a rede de comunica??o interligar? os neur?nios e auxilia no reuso dos mesmos. Separadamente, os pesos e bias ter?o de estar fixos, ou seja, a rede neural a ser embarcada j? deve estar treinada de maneira off-line (realizada antecipadamente em software). A arquitetura vislumbra que o operador n?o necessite conhecer o dispositivo internamente, nem tampouco ter conhecimento sobre linguagem VHDL. O dispositivo reconfigur?vel e de prototipagem r?pida FPGA foi escolhido para implementa??o, simula??o e testes oportunizando aplicar o sistema a problemas reais do nosso cotidiano
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Láník, Jan. "La réduction de consommation dans les circuits digitaux." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAM016/document.

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Le sujet de cette thèse est la réduction de consommation dans les circuits digitaux, et plus particulièrement dans ce cadre les méthodes basées sur la réduction de la fréquence de commutation moyenne, au niveau transistor. Ces méthodes sont structurelles, au sens où elles ne sont pas liées à l’optimisation des caractéristiques physique du circuit mais sur la structure de l’implémentation logique, et de ce fait parfaitement indépendantes de la technologie considérée. Nous avons développé dans ce cadre deux méthodes nouvelles. La première est basée sur l’optimisation de la structure de la partie combinatoire d’un circuit pendant la synthèse logique. La seconde est centrée sur la partie séquentielle du circuit. Elle consiste en la recherche de conditions permettant de détecter qu’un sous-circuit devient inactif, de sorte à pouvoir désactiver ce sous-circuit en coupant la branche correspondante de l’arbre d’horloge, et utilise des méthodes formelles pour prouver que la fonctionnalité du circuit n’en serait pas affectée
The topic of this thesis are methods for power reduction in digital circuits by reducing average switching on the transistor level. These methods are structural in the sense that they are not related to tuning physical properties of the circuitry but to the internal structure of the implemented logic an d therefore independent on the particular technology. We developed two novel methods. One is based on optimizing the structure of the combinatorial part of a circuit during synthesis. The second method is focused on sequential part of the circuit. It looks for clock gating conditions that can be used to disable idle parts of a circuit and uses formal methods to prove that the function of the circuit will not be altered
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Books on the topic "RTL Design"

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Chu, Pong P. RTL Hardware Design Using VHDL. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2006. http://dx.doi.org/10.1002/0471786411.

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Churiwala, Sanjay, and Sapan Garg. Principles of VLSI RTL Design. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9296-3.

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Chu, Pong P. RTL Hardware Design Using VHDL. New York: John Wiley & Sons, Ltd., 2006.

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Vahid, Frank. Digital design, with RTL design, VHDL, and Verilog. 2nd ed. Hoboken, NJ: Wiley, 2011.

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Vahid, Frank. Digital design, with RTL design, VHDL, and Verilog. 2nd ed. Hoboken, NJ: John Wiley, 2010.

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Digital design, with RTL design, VHDL, and Verilog. 2nd ed. Hoboken, NJ: John Wiley, 2010.

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Register transfer level (RTL) hardware design using VHDL. Hoboken, NJ: J. Wiley & Sons, 2006.

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Churiwala, Sanjay. Principles of VLSI RTL design: A practical guide. New York: Springer, 2011.

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Chu, Pong P. RTL hardware design using VHDL: Coding for efficiency, portability, and scalability. Hoboken, NJ: Wiley-Interscience, 2006.

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Keating, Michael. Simple art of SoC design: Closing the gap between RTL and ESL. New York: Springer, 2011.

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Book chapters on the topic "RTL Design"

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Simpson, Philip. "RTL Design." In FPGA Design, 51–78. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_8.

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Simpson, Philip Andrew. "RTL Design." In FPGA Design, 91–139. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7_10.

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Keating, Michael. "Simplifying RTL Design." In The Simple Art of SoC Design, 15–26. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8586-6_2.

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Taraate, Vaibbhav. "RTL Design Guidelines." In Advanced HDL Synthesis and SOC Prototyping, 25–50. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8776-9_3.

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Foster, Harry, Adam Krolnik, and David Lacey. "Specifying RTL Properties." In Assertion-Based Design, 57–99. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4419-9228-4_3.

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Taraate, Vaibbhav. "ASIC RTL Synthesis." In Digital Logic Design Using Verilog, 255–75. New Delhi: Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2791-5_10.

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Lee, Weng Fook. "RTL Coding Guideline." In Learning from VLSI Design Experience, 159–74. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-03238-8_8.

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Churiwala, Sanjay, and Sapan Garg. "Ensuring RTL Intent." In Principles of VLSI RTL Design, 21–41. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9296-3_2.

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Taraate, Vaibbhav. "RTL Design and Verification." In Advanced HDL Synthesis and SOC Prototyping, 51–62. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8776-9_4.

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Taraate, Vaibbhav. "RTL Design Strategies for Complex Designs." In Digital Logic Design Using Verilog, 269–94. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3199-3_12.

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Conference papers on the topic "RTL Design"

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Kahng, Andrew B., Ravi Varadarajan, and Zhiang Wang. "RTL-MP." In ISPD '22: International Symposium on Physical Design. New York, NY, USA: ACM, 2022. http://dx.doi.org/10.1145/3505170.3506731.

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Ghasempouri, Tara, Alessandro Danese, Graziano Pravadelli, Nicola Bombieri, and Jaan Raik. "RTL Assertion Mining with Automated RTL-to-TLM Abstraction." In 2019 Forum for Specification and Design Languages (FDL). IEEE, 2019. http://dx.doi.org/10.1109/fdl.2019.8876941.

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Rashid, Md Imtiaz, and Benjamin Carrion Schafer. "MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR." In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2023. http://dx.doi.org/10.23919/date56975.2023.10136925.

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Deepika and Nidhi Goel. "RTL design of reconfigurable multiplier." In 2015 International Conference on Soft Computing Techniques and Implementations (ICSCTI). IEEE, 2015. http://dx.doi.org/10.1109/icscti.2015.7489532.

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Swan, S. "SystemC transaction level models and RTL verification." In 2006 Design Automation Conference. IEEE, 2006. http://dx.doi.org/10.1109/dac.2006.229170.

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Tasker, S., and R. S. Nikhil. "Beyond RTL: advanced digital system design." In 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06). IEEE, 2006. http://dx.doi.org/10.1109/vlsid.2006.52.

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Qian, Hao, and Yangdong Deng. "Accelerating RTL simulation with GPUs." In 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2011. http://dx.doi.org/10.1109/iccad.2011.6105404.

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Parthasarathy, G., M. K. Iyer, K. T. Cheng, and R. Brewer. "Structural search for RTL with predicate learning." In 2005 42nd Design Automation Conference. IEEE, 2005. http://dx.doi.org/10.1109/dac.2005.193851.

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Bombieri, Nicola, Franco Fummi, and Graziano Pravadelli. "Abstraction of RTL IPs into embedded software." In the 47th Design Automation Conference. New York, New York, USA: ACM Press, 2010. http://dx.doi.org/10.1145/1837274.1837283.

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Skarvada, Jaroslav, Zdenek Kotasek, and Tomas Herrman. "Power Conscious RTL Test Scheduling." In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.78.

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Reports on the topic "RTL Design"

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Ukkusuri, Satish, Lu Ling, Tho V. Le, and Wenbo Zhang. Performance of Right-Turn Lane Designs at Intersections. Purdue University, 2021. http://dx.doi.org/10.5703/1288284317277.

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Right-turn lane (RTL) crashes are among the most key contributors to intersection crashes in the US. Different right turn lanes based on their design, traffic volume, and location have varying levels of crash risk. Therefore, engineers and researchers have been looking for alternative ways to improve the safety and operations for right-turn traffic. This study investigates the traffic safety performance of the RTL in Indiana state based on multi-sources, including official crash reports, official database, and field study. To understand the RTL crashes' influencing factors, we introduce a random effect negative binomial model and log-linear model to estimate the impact of influencing factors on the crash frequency and severity and adopt the robustness test to verify the reliability of estimations. In addition to the environmental factors, spatial and temporal factors, intersection, and RTL geometric factors, we propose build environment factors such as the RTL geometrics and intersection characteristics to address the endogeneity issues, which is rarely addressed in the accident-related research literature. Last, we develop a case study with the help of the Indiana Department of Transportation (INDOT). The empirical analyses indicate that RTL crash frequency and severity is mainly influenced by turn radius, traffic control, and other intersection related factors such as right-turn type and speed limit, channelized type, and AADT, acceleration lane and AADT. In particular, the effects of these factors are different among counties and right turn lane roadway types.
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Streicher, Jürgen, Angela Wroblewski, Klaus Schuch, and Sybille Reidl. RTI Policy Note on Evaluating Social Innovations. Fteval - Austrian Platform for Research and Technology Policy Evaluation, July 2021. http://dx.doi.org/10.22163/fteval.2021.519.

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Expectations of research, technology and innovation (RTI) policy are shifting towards effectively addressing major societal challenges. Due to its potential to increase innovative dynamics, to develop new knowledge and create new solutions, social innovation is increasingly promoted. This raises questions about (potential) effects and impacts of social innovation. The assessment of impacts is a rather new topic in this field, respective research is still in its early stages. This paper proposes to focus on the change of social practices within RTI ecosystems when assessing social innovation. The ecosystem approach is not only a helpful concept to analyse the emergence and diffusion of social innovation in a specific context, it can also be used to support and guide policy design. Implication for evaluation design are discussed and analytical categories presented. A set of measurement dimensions is proposed that can be used in evaluation designs and for future research.
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Schock, Alfred, T. Hamrick, V. Sankarankandath, and M. Shirbacheh. Design and Structural Analysis of Mars Rover RTG. Office of Scientific and Technical Information (OSTI), September 1989. http://dx.doi.org/10.2172/1033418.

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Schock, Alfred, and Chuen T. Or. Effect of Fuel and Design Options on RTG Performance versus PFF Power Demand. Office of Scientific and Technical Information (OSTI), August 1994. http://dx.doi.org/10.2172/1033364.

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Schock, Alfred, Chuen T. Or, and Emanuel A. Skrabek. Thermal and Electrical Analysis of MARS Rover RTG, and Performance Comparison of Alternative Design Options. Office of Scientific and Technical Information (OSTI), September 1989. http://dx.doi.org/10.2172/1033406.

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Riter, Karmann, Anthony Clint Clayton, Kelley Rountree, and Prakash Doraiswamy. Solar Station for an Off-the-Grid Air Quality Sensor System. RTI Press, June 2023. http://dx.doi.org/10.3768/rtipress.2023.mr.0051.2306.

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Air quality monitoring is a rapidly growing area of citizen science, or community science (CS), thanks to the availability of low-cost sensors. Contributing to a crowdsourced data platform (e.g., http:// purpleair .com/ map) is usually easy in urban areas, where there is access to uninterrupted electricity and wireless internet (Wi-Fi). However, there are sometimes security restrictions on Wi-Fi or a lack of exterior power outlets. Also, rural regions, particularly in low- and middle-income countries, often lack electricity and Wi-Fi continuity. RTI International has designed and distributed a solar power and Wi-Fi station that can adequately power both a small air quality sensor (e.g., PurpleAir PA-II) and a Wi-Fi hotspot to overcome these challenges. The station housing can accommodate a battery, a controller, and a cell phone or another type of Wi-Fi hotspot device. This paper discusses the need for such a station; a design for the current station, including parts list; suggestions for modifications in various use cases; and design factors to consider, including amount of sunlight per day, intended number of operational days under cloudy conditions, season, and total power requirements. This method is intended to be open source and a starting point for citizen scientists and CS projects.
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Martinez, Kimberly D., and Gaojian Huang. Exploring the Effects of Meaningful Tactile Display on Perception and Preference in Automated Vehicles. Mineta Transportation Institute, October 2022. http://dx.doi.org/10.31979/mti.2022.2164.

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There is an existing issue in human-machine interaction, such that drivers of semi-autonomous vehicles are still required to take over control of the vehicle during system limitations. A possible solution may lie in tactile displays, which can present status, direction, and position information while avoiding sensory (e.g., visual and auditory) channels overload to reliably help drivers make timely decisions and execute actions to successfully take over. However, limited work has investigated the effects of meaningful tactile signals on takeover performance. This study synthesizes literature investigating the effects of tactile displays on takeover performance in automated vehicles and conducts a human-subject study to design and test the effects of six meaningful tactile signal types and two pattern durations on drivers’ perception and performance during automated driving. The research team performed a literature review of 18 articles that conducted human-subjects experiments on takeover performance utilizing tactile displays as takeover requests. Takeover performance in these studies were highlighted, such as response times, workload, and accuracy. The team then conducted a human-subject experiment, which included 16 participants that used a driving simulator to present 30 meaningful vibrotactile signals, randomly across four driving sessions measuring for reaction times (RTs), interpretation accuracy, and subjective ratings. Results from the literature suggest that tactile displays can present meaningful vibrotactile patterns via various in-vehicle locations to help improve drivers’ performance during the takeover and can be used to assist in the design of human-machine interfaces (HMI) for automated vehicles. The experiment yielded results illustrating higher urgency patterns were associated with shorter RTs and higher intuitive ratings. Also, pedestrian status and headway reduction signals presented shorter RTs and increased confidence ratings compared to other tactile signal types. Finally, the signal types that yielded the highest accuracy were the surrounding vehicle and navigation signal types. Implications of these findings may lie in informing the design of next-generation in-vehicle HMIs and future human factors studies on human-automation interactions.
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Deteresa, S., W. Stein, and V. R. Yagi. Design Analysis of Resin Transfer Molding (RTM) of Fiber Composite Panels Final Report CRADA No. TC-333-92. Office of Scientific and Technical Information (OSTI), March 2018. http://dx.doi.org/10.2172/1430941.

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Deteresa, S., and W. Stein. Design Analysis of Resin Transfer Molding (RTM) of Fiber Composite Panels Final Report CRADA No. TC-333-92. Office of Scientific and Technical Information (OSTI), December 1996. http://dx.doi.org/10.2172/756982.

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Singh, Priyadarshini. Ideas, Policies and Practices: Tracing the Evolution of Elementary Education Reform in India since 1975s. Research on Improving Systems of Education (RISE), January 2023. http://dx.doi.org/10.35489/bsg-rise-2023/pe05.

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This study examines four key reform policies and programs of the Indian education system: DPEP (1994), SSA (2000), RTE (2010) and NEP (2020). Each of these has a rich and nuanced body of research to which our study contributes a unique tracing of the key ideas, debates, and stakeholders. This longue durée of reform will shed light on the histories of current reform options and if they will indeed meet the call of the times to address the learning crisis. We use the political settlements approach to understand the contestation of ideas and actors which finally determine the policy design and the implementation strategies. We unpack the iterative dynamics between ideas and actors to highlight why our reform design looks the way it does and what kind of spaces exist for transformative change particularly to ensure learning.
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