Journal articles: 'RTL Design'

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Jenihhin, Maksim, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, JorgeHernan Meza Escobar, and Heinz-Dietrich Wuttke. "Automated Design Error Localization in RTL Designs." IEEE Design & Test 31, no. 1 (February 2014): 83–92. http://dx.doi.org/10.1109/mdat.2013.2271420.

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SEMBA, Shogo, Hiroshi SAITO, Masato TATSUOKA, and Katsuya FUJIMURA. "Optimization Methods during RTL Conversion from Synchronous RTL Models to Asynchronous RTL Models." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E103.A, no. 12 (December 1, 2020): 1417–26. http://dx.doi.org/10.1587/transfun.2020vlp0004.

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Noji, Tamotsu, Keisuke Shimizu, Hideyuki Hamada, and Akira Nakamura. "Design and implementation of synthesis prediction in RTL design." Systems and Computers in Japan 27, no. 11 (1996): 41–52. http://dx.doi.org/10.1002/scj.4690271104.

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Madineni, Mukesh Chowdary, Mario Vega, and Xiaokun Yang. "Parameterizable Design on Convolutional Neural Networks Using Chisel Hardware Construction Language." Micromachines 14, no. 3 (February 24, 2023): 531. http://dx.doi.org/10.3390/mi14030531.

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This paper presents a parameterizable design generator on convolutional neural networks (CNNs) using the Chisel hardware construction language (HCL). By parameterizing structural designs such as the streaming width, pooling layer type, and floating point precision, multiple register–transfer level (RTL) implementations can be created to meet various accuracy and hardware cost requirements. The evaluation is based on generated RTL designs including 16-bit, 32-bit, 64-bit, and 128-bit implementations on field-programmable gate arrays (FPGAs). The experimental results show that the 32-bit design achieves optimal hardware performance when setting the same weights for estimating the quality of the results, FPGA slice count, and power dissipation. Although the focus is on CNNs, the approach can be extended to other neural network models for efficient RTL design.

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Jain, Nitika. "RTL Design of CISC CPU IP Core." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (June 30, 2022): 4620–24. http://dx.doi.org/10.22214/ijraset.2022.45067.

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Abstract: Recent developments on programmable logic technology had promoted the microprocessor design task from big companies targeting the mass market to the everyday designer as intellectual property (IP) cores toward the system on-a-chip (SOC) approach. This paper shows the VHDL IP 8-bit CISC microprocessor core development which is intended as an open core for teaching applications in the digital systems laboratory. The core is fully open and therefore, the user can have access to all internal signals as well as the opportunity to make changes to the structure itself which is very useful when lecturing microprocessor design. The main advantages of the present core, compared with commercially available equivalent cores, are that it is not vendor sensitive allowing its implementation in almost any FPGA family and being an open core, it can be fully monitored and modified to fit specific design constrains. Several tests were performed to the microprocessor core, including an embedded microcontroller with RAM, ROM and I/O capabilities. The present development includes a meta-assembler and linker to embed user programs in a ROM, which is automatically generated as a VHDL description

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Mück, T. R., and A. A. Fröhlich. "Aspect-oriented RTL HW design using SystemC." Microprocessors and Microsystems 38, no. 2 (March 2014): 113–23. http://dx.doi.org/10.1016/j.micpro.2013.12.002.

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Badawy, W. "Principles of verifiable RTL design [Book Review]." IEEE Circuits and Devices Magazine 18, no. 1 (January 2002): 26–27. http://dx.doi.org/10.1109/mcd.2002.981298.

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SEMBA, Shogo, and Hiroshi SAITO. "Conversion from Synchronous RTL Models to Asynchronous RTL Models." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A, no. 7 (July 1, 2019): 904–13. http://dx.doi.org/10.1587/transfun.e102.a.904.

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Kwon, Bo-Seung, Sang-Won Jung, Young-Dan Noh, Jong-Sik Lee, and Young-Shin Han. "RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool." Telecom 4, no. 1 (December 29, 2022): 15–30. http://dx.doi.org/10.3390/telecom4010002.

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DEVS (Discrete Event System Specification) is widely used in modeling and simulation fields to design, validate, and implement complex response systems. DEVS provides a robust formalism for system design using event-driven, state-based models with explicitly defined temporal information. We extend the RTL-DEVS model based on DEVS formalism to enable part of Verilog simulation in DEVS-based simulation tools. The simulation based on RTL-DEVS methodology, which imitates Verilog’s testbench and behavioral module, confirmed through experiments that RTL simulation can be performed sufficiently through the code elaboration process. In multiple simulation results, Verilog simulation and RTL-DEVS-based simulation were able to output equivalent results under limited conditions. DEVS formalism-based modeling can be extended to other DEVS-based simulators when using model-type exchange tools, and this means that the advanced functions or classes of RTL simulation tools can be applied using higher-level language tools.

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Gowda, Madhura Rame, and Jamuna Jamuna. "Fault simulation for design for testability inserted designs." Indonesian Journal of Electrical Engineering and Computer Science 29, no. 2 (February 1, 2023): 658. http://dx.doi.org/10.11591/ijeecs.v29.i2.pp658-668.

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<p>Systematic design for testability (DFT) is a technique to enhance the testability of design so that it is further organized and self-regulating. The objective of systematic DFT is to enhance a circuit's operability and evidence. This can be performed in a variety of ways. The scan pattern method is the extremely predominant, and it modifies the design's internal sequential circuitry. In this manuscript, frequently used industry standard functional register-transfer level (RTL) designs are chosen. Structured DFT approach is adopted to do scan insertion and automatic test pattern generation (ATPG) to enhance the testability. Proposed methodology provides the controllability and observability for the clocks and reset used in chosen RTL designs by eliminating S rule and D rule violations by adding test logic. Also able to insert stuck at faults and achieve fault coverage of 97.78% and test coverage of 99.26% for DFT architecture for Wallace tree multiplier design, and found different classes of faults as testable and untestable faults and also performed fault simulation for the intended designs to detect fault from the created deterministic patterns.</p>

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Varga, László, Gábor Hosszú, and Ferenc Kovács. "Design Procedure Based on VHDL Language Transformations." VLSI Design 14, no. 4 (January 1, 2002): 349–54. http://dx.doi.org/10.1080/10655140290011159.

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One of the major problems within the VHDL based behavioral synthesis is to start the design on higher abstraction level than the register transfer level (RTL). VHDL semantics was designed strictly for simulation, therefore it was not considered as high-level synthesis language. A novel synthesis procedure was developed, which uses the methodology of high level synthesis. It starts from an abstract VHDL model and produces an RTL VHDL description through successive language transformations while preserving the VHDL standard simulation semantics. The steps of the synthesis do not use graph representation or other meta-language, but apply the standard VHDL only. This VHDL representation is simulatable and accessible, functional verification can be performed by simulation at any time, and the simulation results can be used to guide the synthesis process. The output VHDL format is suitable to continue the design flow with RTL based synthesis tools.

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Safieddine, Maya H., Fadi A. Zaraket, Rouwaida Kanj, Ali El-Zein, and Wolfgang Roesner. "Verification at RTL Using Separation of Design Concerns." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 8 (August 2019): 1529–42. http://dx.doi.org/10.1109/tcad.2018.2848589.

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Yoneda, Tomokazu, and Hideo Fujiwara. "Design for consecutive transparency method of RTL circuits." Systems and Computers in Japan 37, no. 2 (February 2006): 1–10. http://dx.doi.org/10.1002/scj.20417.

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Perali, Sri Phanindra, Nithin Krishna Madadi, and Rohith Reddy. "RTL Implementation of AMBA AHB Protocol using Verilog." International Journal for Research in Applied Science and Engineering Technology 11, no. 4 (April 30, 2023): 4056–63. http://dx.doi.org/10.22214/ijraset.2023.51179.

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Abstract: The enactment of a computer system heavily depends on the design of its bus interconnect. A poorly designed system bus can hinder the transmission of instructions and data between the processor and memory or between peripheral devices and memory. To address these challenges, the Advanced Microcontroller Bus Architecture (AMBA) provides an open standard for connecting and managing functional blocks in a System-on-Chip (SoC). This architecture allows for developing multi-processor designs with many controllers and peripherals while ensuring the system is designed correctly the first time. Furthermore, the AMBA specifications are royalty-free and platform-independent. They can be used with any processor architecture. The project will provide an RTL view and an extracted design summary of the AMBA AHB module at the system-on-chip level. The AMBA High-performance Bus (AHB) is another part of the AMBA family of conventions. The AHB is designed to support highperformance, high-clock system modules and serves as the system's high-performance backbone bus. The AHB enables the efficient connection of low-power peripheral functions to processors, on-chip memories, and external off-chip memory interfaces. All signal transitions in the AHB relate only to the rising clock edge, allowing AHB peripherals to be easily integrated into any design flow. The project also describes the AMBA AHB design and implementation using Verilog, with read/write operations implemented using the Xilinx simulator.

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Tatas, K., K. Siozios, A. Bartzas, C. Kyriacou, and D. Soudris. "A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC." International Journal of Adaptive, Resilient and Autonomic Systems 4, no. 3 (July 2013): 1–24. http://dx.doi.org/10.4018/jaras.2013070101.

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This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach.

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Bruno, M., A. Macii, and M. Poncino. "RTL power estimation in an HDL-based design flow." IEE Proceedings - Computers and Digital Techniques 152, no. 6 (2005): 723. http://dx.doi.org/10.1049/ip-cdt:20045181.

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Adler, John, and Andreas Veneris. "Leveraging Software Configuration Management in Automated RTL Design Debug." IEEE Design & Test 34, no. 5 (October 2017): 47–53. http://dx.doi.org/10.1109/mdat.2017.2713391.

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Papachristou, C. A., M. Nourani, and M. Spining. "A multiple clocking scheme for low-power RTL design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7, no. 2 (June 1999): 266–76. http://dx.doi.org/10.1109/92.766754.

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Ludwig, Tobias, Joakim Urdahl, Dominik Stoffel, and Wolfgang Kunz. "Properties First—Correct-By-Construction RTL Design in System-Level Design Flows." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 10 (October 2020): 3093–106. http://dx.doi.org/10.1109/tcad.2019.2921319.

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Ma, De, Kai Huang, Si Wen Xiu, Xiao Lang Yan, Jiong Feng, Jian Lin Zeng, and Hai Tong Ge. "An Automatic SoC Design Methodology for Integration and Verification." Advanced Materials Research 383-390 (November 2011): 2222–30. http://dx.doi.org/10.4028/www.scientific.net/amr.383-390.2222.

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The increasing complexity of current SoC design brings a great challenge to SoC designer for fast SoC RTL integration and effective verification. In this paper, an automatic SoC integration methodology based on IP-XACT standard is proposed as a complete and effective solution for low-level RTL simulation, FPGA emulation and ASIC implementation. A bottom-up approach is adopted for design integration and verification from component level, to SoC core level, and then to final chip level. The three-core MPSoC case study not only gives the detailed usage and analysis on the proposed methodology, but also shows its efficiency to integrate a complex SoC design and its feasibility for correct SoC implementation.

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Yim, Joon-Seo, Chang-Jae Park, In-Cheol Park, and Chong-Min Kyung. "Design Verification of Complex Microprocessors." Journal of Circuits, Systems and Computers 07, no. 04 (August 1997): 301–18. http://dx.doi.org/10.1142/s021812669700022x.

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As the complexity of microprocessors increases, functional verification becomes more difficult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional verification methodology, especially for compatible microprocessor designs. To guarantee perfect compatibility with previous microprocessors, we developed three C models in different abstraction levels, i.e. Polaris, MCV and StreC. An instruction behavioral level C model (Polaris) is verified using the slowed-down PC. In the implemetation of micro-architecture, a micro-operational level model (MCV) and RTL model (StreC) are co-simulated with consistency checking between these two models. The simulation speed of C models makes it possible to test the "real-world" application programs on the RTL design with a software board model (VPC). To increase the confidence level of verifications, Profiler reports the verification coverage of the test program, which is fed-back to the automatic test program generator (Pandora). The Restartability feature also helps to significantly reduce the total simulation time. Using the proposed verification methodology, we designed and verified the HK486, an Intel 80486 pin-compatible microprocessor successfully.

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Ravi, S., Suprovab Mandal, and Harish M. Kittur. "Design and Verification of High Performance Standard Cells for Clock Network Applications." Advanced Science Letters 24, no. 8 (August 1, 2018): 5877–83. http://dx.doi.org/10.1166/asl.2018.12213.

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Standard cell libraries are required by all CAD tools for chip planning. Standard cell libraries contain primitive cells required for advanced configuration. Be that as it may, more crucial cells that have been infrequently upgraded can likewise be incorporated. The principle reason for the CAD tools is to actualize the alleged RTL- to-GDS stream. Design and verification of standard cells (clock path) the advanced clock buffers and inverters present superior performance compared to the existed clock buffers and inverters. The RTL synthesis report shows that timing slack, numbers of inverters and power consumption have been reduced by 65.9%, 80.5% and 5.1% respectively.

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Lan, Mengqiao, Libo Huang, Ling Yang, Sheng Ma, Run Yan, Yongwen Wang, and Weixia Xu. "Late-Stage Optimization of Modern ILP Processor Cores via FPGA Simulation." Applied Sciences 12, no. 23 (November 29, 2022): 12225. http://dx.doi.org/10.3390/app122312225.

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Late-stage (post-RTL implementation) optimization is important in achieving target performance for realistic processor design. However, several challenges remain for modern out-of-order ILP (instruction-level-parallelism) processors, such as simulation speed, flexibility, and complexity problems. This paper restudy FPGA simulation as an effective performance simulation method and proposes FPGA-enhanced design flow as an effective method to address these problems. It features a late-stage aware RTL design that parameterizes various potential design options induced from early-stage optimization. This flow enables the feasibility of late-stage design space exploration. To resolve the performance accuracy of the FPGA system for peripheral designs, reference models are introduced. With an example implementation of out-of-order core running up to 80 MHz, the experimental results show that the proposed method is practical and allows the fine-grain optimization of the processor core to be more effective.

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Kumar, Jayanand Asok, and Shobha Vasudevan. "Formal Probabilistic Timing Verification in RTL." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 5 (May 2013): 788–801. http://dx.doi.org/10.1109/tcad.2012.2232706.

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Silveira, George Sobral, Alisson V. Brito, Helder F. de A. Oliveira, and Elmar U. K. Melcher. "Open SystemC Simulator with Support for Power Gating Design." International Journal of Reconfigurable Computing 2012 (2012): 1–8. http://dx.doi.org/10.1155/2012/793190.

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Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique has been executed in a Register-Transfer Level (RTL) abstraction, based on the Common Power Format (CPF) and the Unified Power Format (UPF). The purpose of this paper is to present an OSCI SystemC simulator with support to the power gating design. This simulator is an alternative to assist the functional verification accomplishment of systems modeled in RTL. The possibility of controlling the retention and isolation of power gated functional block (PGFB) is presented in this work, turning the simulations more stable and accurate. Two case studies are presented to demonstrate the new features of that simulator.

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Noll, Kyle R., Jeffrey S. Weinberg, Mateo Ziu, Ronald J. Benveniste, Dima Suki, and Jeffrey S. Wefel. "Neurocognitive Changes Associated With Surgical Resection of Left and Right Temporal Lobe Glioma." Neurosurgery 77, no. 5 (August 26, 2015): 777–85. http://dx.doi.org/10.1227/neu.0000000000000987.

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Abstract BACKGROUND: Little is known regarding the neurocognitive impact of temporal lobe tumor resection. OBJECTIVE: To clarify subacute surgery-related changes in neurocognitive functioning (NCF) in patients with left (LTL) and right (RTL) temporal lobe glioma. METHODS: Patients with glioma in the LTL (n = 45) or RTL (n = 19) completed comprehensive pre- and postsurgical neuropsychological assessments. NCF was analyzed with 2-way mixed design repeated-measures analysis of variance, with hemisphere (LTL or RTL) as an independent between-subjects factor and pre- and postoperative NCF as a within-subjects factor. RESULTS: About 60% of patients with LTL glioma and 40% with RTL lesions exhibited significant worsening on at least 1 NCF test. Domains most commonly impacted included verbal memory and executive functioning. Patients with LTL tumor showed greater decline than patients with RTL tumor on verbal memory and confrontation naming tests. Nonetheless, over one-third of patients with RTL lesions also showed verbal memory decline. CONCLUSION: In patients with temporal lobe glioma, NCF decline in the subacute postoperative period is common. As expected, patients with LTL tumor show more frequent and severe decline than patients with RTL tumor, particularly on verbally mediated measures. However, a considerable proportion of patients with RTL tumor also exhibit decline across various domains, even those typically associated with left hemisphere structures, such as verbal memory. While patients with RTL lesions may show even greater decline in visuospatial memory, this domain was not assessed. Nonetheless, neuropsychological assessment can identify acquired deficits and help facilitate early intervention in patients with temporal lobe glioma.

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Jang, Seojin, Wei Liu, Sangun Park, and Yongbeom Cho. "Automatic RTL Generation Tool of FPGAs for DNNs." Electronics 11, no. 3 (January 28, 2022): 402. http://dx.doi.org/10.3390/electronics11030402.

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With the increasing use of multi-purpose artificial intelligence of things (AIOT) devices, embedded field-programmable gate arrays (FPGA) represent excellent platforms for deep neural network (DNN) acceleration on edge devices. FPGAs possess the advantages of low latency and high energy efficiency, but the scarcity of FPGA development resources challenges the deployment of DNN-based edge devices. Register-transfer level programming, hardware verification, and precise resource allocation are needed to build a high-performance FPGA accelerator for DNNs. These tasks present a challenge and are time consuming for even experienced hardware developers. Therefore, we propose an automated, collaborative design process employing an automatic design space exploration tool; an automatic DNN engine enables the tool to reshape and parse a DNN model from software to hardware. We also introduce a long short-term memory (LSTM)-based model to predict performance and generate a DNN model that suits the developer requirements automatically. We demonstrate our design scheme with three FPGAs: a zcu104, a zcu102, and a Cyclone V SoC (system on chip). The results show that our hardware-based edge accelerator exhibits superior throughput compared with the most advanced edge graphics processing unit.

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Pundir, Nitin, Sohrab Aftabjahani, Rosario Cammarota, Mark Tehranipoor, and Farimah Farahmandi. "Analyzing Security Vulnerabilities Induced by High-level Synthesis." ACM Journal on Emerging Technologies in Computing Systems 18, no. 3 (July 31, 2022): 1–22. http://dx.doi.org/10.1145/3492345.

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High-level synthesis (HLS) is essential to map the high-level language (HLL) description (e.g., in C/C++) of hardware design to the corresponding Register Transfer Level (RTL) to produce hardware-independent design specifications with reduced design complexity for ASICs and FPGAs. Adopting HLS is crucial for industrial and government applications to lower development costs, verification efforts, and time-to-market. Current research practices focus on optimizing HLS for performance, power, and area constraints. However, the literature does not include an analysis of the security implications carried through HLS-generated RTL translations (e.g., from an untimed high-level sequential specification to a fully scheduled implementation). This article demonstrates the evidence of security vulnerabilities that emerge during the HLS translation of a high-level description of system-on-chip (SoC) intellectual properties to their corresponding RTL. The evidence provided in this manuscript highlights the need for (a) guidelines for high-level programmers to prevent these security issues at the design time and (b) automated HLS verification solutions that cover security in their optimization flow.

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Ameur, Noura Ben, Nouri Masmoudi, and Mourad Loulou. "FPGA-Based Design Δ–Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit." Journal of Circuits, Systems and Computers 24, no. 03 (February 10, 2015): 1550037. http://dx.doi.org/10.1142/s0218126615500371.

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This paper, focus on synthesis design of a Δ–Σ digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio DAC. The features of the design are high-precision, fast processing and low-cost. The related work is done with the MATLAB & QUARTUS II simulators.

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Laurent, J., C. Deleuze, F. Pebay-Peyroula, and V. Beroulle. "Bridging the Gap between RTL and Software Fault Injection." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (May 11, 2021): 1–24. http://dx.doi.org/10.1145/3446214.

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Protecting programs against hardware fault injection requires accurate software fault models. However, typical models, such as the instruction skip, do not take into account the microarchitecture specificities of a processor. We propose in this article an approach to study the relation between faults at the Register Transfer Level (RTL) and faults at the software level. The goal is twofold: accurately model RTL faults at the software level and materialize software fault models to actual RTL injections. These goals lead to a better understanding of a system's security against hardware fault injection, which is important to design effective and cost-efficient countermeasures. Our approach is based on the comparison between results from RTL simulations and software injections (using a program mutation tool). Various analyses are included in this article to give insight on the relevance of software fault models, such as the computation of a coverage and fidelity metric, and to link software fault models to hardware RTL descriptions. These analyses are applied on various single-bit and multiple-bit injection campaigns to study the faulty behaviors of a RISC-V processor.

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Newman, Linda L., and Ann B. Smit. "Some Effects of Variations in Response Time Latency on Speech Rate, Interruptions, and Fluency in Children's Speech." Journal of Speech, Language, and Hearing Research 32, no. 3 (September 1989): 635–44. http://dx.doi.org/10.1044/jshr.3203.635.

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The present study was designed to examine adult-child interactions during conversation with respect to the effects of adult paralinguistic speech variations on the speech production of children. Four 4-year-old children served as subjects. A single-subject A-B-A design with counterbalancing and replication was implemented. Each subject participated in three 15-min conversations with an experimenter. The independent variable was the interspeaker pause time—the response time latency (RTL). During the 15-min conversations, the experimenter used either a 1-s or a 3-s RTL when responding to the child. RTL was measured for each subject in each condition. Data analysis revealed that each child's RTL was significantly longer when the experimenter's RTL was 3 s than when it was 1 s, and all differences between all conditions reached significance for these subjects. Other dependent variables included speech rate, the frequency of disfluencies, and the frequency of interruptions produced by the subjects within each condition. All 4 subjects varied the frequency of disfluencies and interruptions. However, each child varied rate and disfluencies in a highly individualistic manner.

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Obert, James, and Tom J. Mannos. "ASIC STA Path Verification Using Semi-Supervised Learning." International Journal of Semantic Computing 13, no. 02 (June 2019): 229–44. http://dx.doi.org/10.1142/s1793351x19400105.

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To counter manufacturing irregularities and ensure ASIC design integrity, it is essential that robust design verification methods are employed. It is possible to ensure such integrity using ASIC static timing analysis (STA) and machine learning. In this research, uniquely devised machine and statistical learning methods which quantify anomalous variations in Register Transfer Level (RTL) or Graphic Design System II (GDSII) format are discussed. To measure the variations in ASIC analysis data, the timing delays in relation to path electrical characteristics are explored. It is shown that semi-supervised learning techniques are powerful tools in characterizing variations within STA path data and have much potential for identifying anomalies in ASIC RTL and GDSII design data.

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Sato, Tomoaki, Sorawat Chivapreecha, Phichet Moungnoul, and Kohji Higuchi. "RCA on FPGAs Designed by RTL Design Methodology and Wave-Pipelined Operation." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 11, no. 1 (May 9, 2017): 10–19. http://dx.doi.org/10.37936/ecti-cit.2017111.65680.

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Field-programmable gate arrays (FPGAs) are used in various systems with reconfigurable functions. Conventional FPGAs have been developed using a transistor level description for minimizing routing delay. Although FPGAs developed with a register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors advanced their development. They should be shown to operate with practical throughput. For this purpose, circuits on these device need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) was designed and the throughput of the RCA was evaluated. The resulting throughput was applicable to network processors. Additionally, a wave-pipelined operation without changing the RCA revealed that the problem of routing delay in FPGA developed by RTL methodology was mitigated. The contributions of this paper are to clarify that a 4-bit adder can be implemented on FPGAs and their throughput can be improved by wave-pipelined operations.

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Skripnichenko, M. N., and I. A. Lipatov. "DESIGN AND VERIFICATION FLOW OF MULTI-STAGE SIGMA-DELTA ADC DIGITAL CORE." Issues of radio electronics, no. 8 (August 20, 2018): 56–63. http://dx.doi.org/10.21778/2218-5453-2018-8-56-63.

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There is a need for analog-to-digital converters with high signal-to-noise ratio and large signal bandwidth to solve a number of radiolocation problems. Developing such ADC is a challenge in the analog core, digital core and verification. The design flow of the digital core must take into account the possibility of changing the analog core specification at any design stage, provide the ability to quickly obtain the synthesizable RTL code of the device and conduct its functional verification. Automation tools were used to reduce the time spent on development and verification. This article describes the developed software package that generates the synthesizable RTL code and the verification environment configurations for each stage of development of the analog core of the multi-stage sigma-delta ADC.

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Zhong, L., S. Ravi, A. Raghunathan, and N. K. Jha. "RTL-Aware Cycle-Accurate Functional Power Estimation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 10 (October 2006): 2103–17. http://dx.doi.org/10.1109/tcad.2005.859504.

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Alpaslan, Elif, Yu Huang, Xijiang Lin, Wu-Tung Cheng, and Jennifer Dworak. "On Reducing Scan Shift Activity at RTL." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 7 (July 2010): 1110–20. http://dx.doi.org/10.1109/tcad.2010.2049057.

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Pal, Debjit, Spencer Offenberger, and Shobha Vasudevan. "Assertion Ranking Using RTL Source Code Analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 8 (August 2020): 1711–24. http://dx.doi.org/10.1109/tcad.2019.2921374.

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Katkoori, Srinivas, and Ranga Vemuri. "Architectural Power Estimation Based on Behavior Level Profiling." VLSI Design 7, no. 3 (January 1, 1998): 255–70. http://dx.doi.org/10.1155/1998/93106.

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High level synthesis is the process of generating register transfer (RT) level designs from behavioral specifications. High level synthesis systems have traditionally taken into account such constraints as area, clock period and throughput time. Many high level synthesis systems [1] permit generation of many alternative RT level designs meeting these constraints in a relatively short time. If it is possible to accurately estimate the power consumption of RT level designs, then a low power design from among these alternatives can be selected.In this paper, we present an accurate power estimation technique for register transfer level designs generated by high level synthesis systems. The technique has four main aspects: (1) Each RT level component used in high level synthesis is characterized for average switched capacitance per input vector. This data is stored in the RT level component library. (2) Using user-specified stimuli, the given behavioral description is simulated and event activities of various operators and carriers are measured. Then, the behavioral specification is submitted to the synthesis system and a number of alternative RTL designs meeting speed, space and throughput rate constraints are generated. (3) Event activity of each component in an RT level design is estimated using the event activities measured at the time of behavior level profiling and the structure of the RTL design itself. (4) The event activities so obtained are then used to modulate the average switched capacitances of the respective RT level components to obtain an estimate the total switched capacitance of each component.Detailed power estimation procedures for the three different parts of RTL designs, namely, data path, controller and interconnect are presented. Experimental results obtained from a variety of designs show that the power estimates are within 3%–10% of the actual power measured by simulating the transistor level designs extracted from mask layouts.

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MIYAOKA, Yuya, Yuhei NAGAO, Masayuki KUROSAKI, and Hiroshi OCHI. "RTL Design of High-Speed Sorted QR Decomposition for MIMO Decoder." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E95.A, no. 11 (2012): 1991–97. http://dx.doi.org/10.1587/transfun.e95.a.1991.

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Ghosh, I., A. Raghunathan, and N. K. Jha. "Design for hierarchical testability of RTL circuits obtained by behavioral synthesis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, no. 9 (1997): 1001–14. http://dx.doi.org/10.1109/43.658568.

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KumarTiwari, Nitin, Ravi Kumar, R. K. Sarin, and Sarabjeet Singh. "NoC based Efficient RTL Design and Verification of SoCWire BUS Protocol." International Journal of Computer Applications 43, no. 20 (April 30, 2012): 26–30. http://dx.doi.org/10.5120/6221-8786.

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CVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad, and V. Siva Ramakrishna. "Design of High-Speed Multiplier Architecture Based on Vedic Mathematics." International Journal of Engineering & Technology 7, no. 2.4 (March 10, 2018): 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.

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High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyamsutra of Vedic Multiplication has been presented in this paper. The multiplier architecture is implemented using Verilog coding and synthesise during Cadence RTL Compiler. Physical design is implemented using Cadence Encounter RTL-to-GDSII System using standard 180nm technology. The proposed multiplier architecture is compared with the conventional multiplier and the results show significant improvement in speed and power dissipation.

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Zaourar, Lilia, Yann Kieffer, and Chouki Aktouf. "A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions." VLSI Design 2012 (December 20, 2012): 1–11. http://dx.doi.org/10.1155/2012/312808.

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The scan chain insertion problem is one of the mandatory logic insertion design tasks. The scanning of designs is a very efficient way of improving their testability. But it does impact size and performance, depending on the stitching ordering of the scan chain. In this paper, we propose a graph-based approach to a stitching algorithm for automatic and optimal scan chain insertion at the RTL. Our method is divided into two main steps. The first one builds graph models for inferring logical proximity information from the design, and then the second one uses classic approximation algorithms for the traveling salesman problem to determine the best scan-stitching ordering. We show how this algorithm allows the decrease of the cost of both scan analysis and implementation, by measuring total wirelength on placed and routed benchmark designs, both academic and industrial.

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Putukian, Margot, Laura Purcell, Kathryn J. Schneider, Amanda Marie Black, Joel S. Burma, Avinash Chandran, Adrian Boltz, et al. "Clinical recovery from concussion–return to school and sport: a systematic review and meta-analysis." British Journal of Sports Medicine 57, no. 12 (June 2023): 798–809. http://dx.doi.org/10.1136/bjsports-2022-106682.

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ObjectiveTo define the time frames, measures used and modifying factors influencing recovery, return to school/learn (RTL) and return to sport (RTS) after sport-related concussion (SRC).DesignSystematic review and meta-analysis.Data sources8 databases searched through 22 March 2022.Eligibility criteriaStudies with diagnosed/suspected SRC and interventions facilitating RTL/RTS or investigating the time and modifying factors for clinical recovery. Outcomes included days until symptom free, days until RTL and days until RTS. We documented study design, population, methodology and results. Risk of bias was evaluated using a modified Scottish Intercollegiate Guidelines Network tool.Results278 studies were included (80.6% cohort studies and 92.8% from North America). 7.9% were considered high-quality studies, while 23.0% were considered high risk of bias and inadmissible. The mean days until symptom free was 14.0 days (95% CI: 12.7, 15.4; I2=98.0%). The mean days until RTL was 8.3 (95% CI: 5.6, 11.1; I2=99.3%), with 93% of athletes having a full RTL by 10 days without new academic support. The mean days until RTS was 19.8 days (95% CI: 18.8, 20.7; I2=99.3%), with high heterogeneity between studies. Several measures define and track recovery, with initial symptom burden remaining the strongest predictor of longer days until RTS. Continuing to play and delayed access to healthcare providers were associated with longer recovery. Premorbid and postmorbid factors (eg, depression/anxiety, migraine history) may modify recovery time frames. Though point estimates suggest that female sex or younger age cohorts take longer to recover, the heterogeneity of study designs, outcomes and overlap in CIs with male sex or older age cohorts suggests that all have similar recovery patterns.ConclusionMost athletes have full RTL by 10 days but take twice as long for an RTS.PROSPERO registration numberCRD42020159928.

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Moon, Sangook, and Jongsu Park. "System Level Design of Reconfigurable Server Farms Using Elliptic Curve Cryptography Processor Engines." Journal of Applied Mathematics 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/390176.

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As today’s hardware architecture becomes more and more complicated, it is getting harder to modify or improve the microarchitecture of a design in register transfer level (RTL). Consequently, traditional methods we have used to develop a design are not capable of coping with complex designs. In this paper, we suggest a way of designing complex digital logic circuits with a soft and advanced type of SystemVerilog at an electronic system level. We apply the concept of design-and-reuse with a high level of abstraction to implement elliptic curve crypto-processor server farms. With the concept of the superior level of abstraction to the RTL used with the traditional HDL design, we successfully achieved the soft implementation of the crypto-processor server farms as well as robust test bench code with trivial effort in the same simulation environment. Otherwise, it could have required error-prone Verilog simulations for the hardware IPs and other time-consuming jobs such as C/SystemC verification for the software, sacrificing more time and effort. In the design of the elliptic curve cryptography processor engine, we propose a 3X faster GF(2m) serial multiplication architecture.

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Kumar, Kandagatla Ravi, Cheeli Priyadarshini, Kanakam Bhavani, Ankam Varun Sundar Kumar, and Palanki Naga Nanda Sai. "Design of High Speed and Low Area Confined Multiplier on FPGA." Revista Gestão Inovação e Tecnologias 11, no. 4 (July 22, 2021): 2736–46. http://dx.doi.org/10.47059/revistageintec.v11i4.2315.

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In this Advanced world, Technology is playing the major role. Most importantly development in Electronics field has a large impact on the improved life style. Among the advanced applications, DSP ranks first in place. Multipliers are the most basic elements that are widely used in the Digital Signal Processing (DSP) applications. Therefore, the design of the multiplier is the main factor for the performance of the device. Using RTL simulation and a Field Programmable Gate Array (FPGA), we compare the performance of a serial multiplier with an advanced multiplier. Many single bit adders are removed and replaced with multiplexers in this project. So that the less often used FPGAs are fully used by occupying fewer divisions and slices. The use of multiplier architecture results in significant reductions in FPGA resources, latency, area, and power. These multiplication approaches are created utilizing RTL simulation in Xilinx ISE simulator and synthesis in Xilinx ISE 14.7. Finally, the Spartan 3E FPGA is used to implement the design.

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Колбасов, Я. С., and Ф. М. Путря. "МОДЕЛЬ ДЛЯ АВТОМАТИЗАЦИИ АНАЛИЗА СИСТЕМЫ ТАКТИРОВАНИЯ СНК." NANOINDUSTRY Russia 96, no. 3s (June 15, 2020): 262–64. http://dx.doi.org/10.22184/1993-8578.2020.13.3s.262.264.

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В работе представлена модель управления тактированием асинхронных СнК и методика контроля и верификации на уровне описания RTL. На основе модели написан шаблон для автоматизации тестов системы управления тактированием. Проведена оценка результатов. The paper highlights a clock control model for analysis automation. It supports both synchronous and asynchronous approach on RTL level of design. Template for test automation based on a clock control model has been constructed. The results were proven and compared with classical approach.

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Mediavilla, Juan Romero, Cristian Arias Espinoza, Alex Pachacama Espinosa, and Franklin Salazar. "Design of a Passive Radar based on RTL-SDR technology with coherent dual channel." Journal of Physics: Conference Series 2199, no. 1 (February 1, 2022): 012023. http://dx.doi.org/10.1088/1742-6596/2199/1/012023.

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Abstract In this research, a passive radar aimed at the detection of unmanned aerial vehicles was developed. As a UAV navigates at low altitudes and high speeds, RTL-SDR modules are used that with the help of two antennas, one directional and one reference, the position of the object is detected through bounce and signal discrimination, for which several tests were carried out in based on frequencies that are in the FM range. For this, GNU radio is used and data processing with Python in the Anaconda guide that facilitates obtaining data visually through a video of the frequency of the Doppler effect vs the distance in kilometers. Also, mention is made of the synchronization arrangement that is established between the RTL-SDR modules based on their oscillator.

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Joseph, Jan Moritz, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García-Ortiz, and Thilo Pionteck. "Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs." ACM Transactions on Modeling and Computer Simulation 32, no. 1 (January 31, 2022): 1–21. http://dx.doi.org/10.1145/3472754.

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We introduce Ratatoskr , an open-source framework for in-depth power, performance, and area (PPA) analysis in Networks-on-Chips (NoCs) for 3D-integrated and heterogeneous System-on-Chips (SoCs). It covers all layers of abstraction by providing an NoC hardware implementation on Register Transfer Level (RTL), an NoC simulator on cycle-accurate level and an application model on transaction level. By this comprehensive approach, Ratatoskr can provide the following specific PPA analyses: Dynamic power of links can be measured within 2.4% accuracy of bit-level simulations while maintaining cycle-accurate simulation speed. Router power is determined from RTL-to-gate-level synthesis combined with cycle-accurate simulations. The performance of the whole NoC can be measured both via cycle-accurate and RTL simulations. The performance (i.e., timing) of individual routers and the NoC area are obtained from RTL synthesis results. Despite these manifold features, Ratatoskr offers easy two-step user interaction: (1) A single point-of-entry allows setting design parameters. (2) PPA reports are generated automatically. For both the input and the output, different levels of abstraction can be chosen for high-level rapid network analysis or low-level improvement of architectural details. The synthesizable NoC-RTL model shows improved total router power and area in comparison to a conventional standard router. As a forward-thinking and unique feature not found in other NoC PPA-measurement tools, Ratatoskr supports heterogeneous 3D integration that is one of the most promising integration paradigms for upcoming SoCs. Thereby, Ratatoskr lays the groundwork to design their communication architectures. The framework is publicly available at https://github.com/ratatoskr-project .

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Runyon, Lacey M., Cailee E. Welch Bacon, Elizabeth R. Neil, and Lindsey E. Eberman. "Understanding the Athletic Trainer's Role in the Return-to-Learn Process at National Collegiate Athletic Association Division II and III Institutions." Journal of Athletic Training 55, no. 4 (April 1, 2020): 365–75. http://dx.doi.org/10.4085/1062-6050-116-19.

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Context Postconcussion, student-athletes should return to the classroom using a gradual, stepwise process to ensure that symptoms are not exacerbated by cognitive activities. The National Collegiate Athletic Association (NCAA) has mandated that its affiliated institutions develop return-to-learn (RTL) policies to support the return to the classroom. Objective To investigate athletic trainers' (ATs') perceptions of their role in the RTL policy development and implementation at NCAA Division II and III institutions. Design Qualitative study. Setting Individual phone interviews. Patients or Other Participants Fifteen ATs (age = 40 ± 11 years, clinical practice experience = 16 ± 9 years, employment term = 9 ± 9 years) representing NCAA Division II (n = 6) or III (n = 9) institutions. Data Collection and Analysis Interviews were transcribed verbatim and checked for accuracy by the principal investigator. A 2-member data-analysis team independently coded a portion of the transcripts and then met to discuss the codebook. The codebook was applied to the remaining transcripts, confirmed, and externally reviewed. Results Five themes emerged: (1) approach, (2) collaborative practice, (3) patient advocacy, (4) institutional autonomy, and (5) barriers. Policies must allow for an individualized, evidence-based approach through facilitated, active communication among members of the RTL team and the student-athlete. Collaborative practice was described as key to successful policy implementation and should include interprofessional collaboration beyond health care providers (eg, educating academicians about the purpose of RTL). The RTL process was triggered by a specific member of the RTL team, usually a medical doctor or the head AT. Participants noted that the purpose of the RTL policy was to advocate for the student-athlete's successful postconcussion outcomes. Conclusions For the development and implementation of a successful RTL policy, strong communication and interprofessional practice must extend beyond health care professionals. Members of the health care team must establish a network with academic partners to develop a policy that is appropriate for the institution's available resources and the needs of its student-athletes.

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Journal articles on the topic 'RTL Design'

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