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Ling, Malin. "Execution Time Measurements of Processes on the OSE Real-Time Operating System." Thesis, Linköping University, Department of Science and Technology, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-9980.
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<p>Ett ramverk för kontraktbaserad schemaläggning av dynamisk resursfördelning i realtidsoperativsystem ska rapporteras till operativsystemet OSE. Ramverket, som utvecklats i ett EU-forskningsprojekt, kräver uppmätt process exekveringstid för att fatta riktiga schemaläggningsbeslut. Sådana mätningar görs för närvarande inte i ENEAs RTOS OSE och examensarbetets syfte har därför varit att undersöka möjligheterna att implementera en sådan funktion. Alternativ har hittats och utvärderats, slutligen har ett valts för implementation. Funktionalilteten har verifierats och slutlilgen har prestanda utvärderats hos den implementerade mätningsmetoden.</p>
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Borgström, Fredrik. "Acceleration of FreeRTOS withSierra RTOS accelerator : Implementation of a FreeRTOS software layer onSierra RTOS accelerator." Thesis, KTH, Data- och elektroteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-188518.
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Today, the effect of the most common ways to improve the performance of embedded systems and real-time operating systems is stagnating. Therefore it is interesting to examine new ways to push the performance boundaries of embedded systems and real-time operating systems even further. It has previously been demonstrated that the hardware-based real-time operating system, Sierra, has better performance than the software-based real-time operating system, FreeRTOS. These real-time operating systems have also been shown to be similar in many aspects, which mean that it is possible for Sierra to accelerate FreeRTOS. In this thesis an implementation of such acceleration has been carried out. Because existing real-time operating systems are constantly in development combined with that it was several years since an earlier comparison between the two real-time operating systems was per-formed, FreeRTOS and Sierra were compared in terms of functionality and architecture also in this thesis. This comparison showed that FreeRTOS and Sierra share the most fundamental functions of a real-time operating system, and thus can be accelerated by Sierra, but that FreeRTOS also has a number of exclusive functions to facilitate the use of that real-time operating system. The infor-mation obtained by this comparison was the very essence of how the acceleration would be imple-mented. After a number of performance tests it could be concluded that all of the implemented functions, with the exception of a few, had shorter execution time than the corresponding functions in the original version of FreeRTOS.<br>Idag är effekten av de vanligaste åtgärderna för att förbättra prestandan av inbyggda system och realtidsoperativsystem väldigt liten. På grund av detta är det intressant att undersöka nya åtgärder för att tänja prestandagränserna av inbyggda system och realtidsoperativsystem ytterliggare. Det har tidigare påvisats att det hårdvarubaseraderealtidsoperativsystemet, Sierra, har bättre prestanda än det mjukvarubaseraderealtidsoperativsystemet, FreeRTOS. Dessa realtidsoperativsystem har även visats vara lika i flera aspekter, vilket betyder att det är möjligt för Sierra att accelererera FreeRTOS. I detta examensarbete har en implementering av en sådan acceleration genomförts. Eftersom befintliga realtidsoperativsystem ständigtär i utveckling i kombination med att det är flera år sedan som en tidigare jämförelse mellan de båda systemen utfördes, så jämfördes FreeRTOS och Sierra i fråga om funktionalitet och uppbyggnad även i detta examensarbete.Denna jämförelse visade att FreeRTOS och Sierra delar de mest grundläggande funktionerna av ett realtidsoperativsystem, och som därmed kan accelereras av Sierra, men att FreeRTOS även har ett antal exklusiva funktioner för att underlätta användningen av det realtidsoperativsystemet. Informationen som erhölls av denna jämförelse var sedan grunden för hur själva accelerationen skulle implementeras. Efter ett antal prestandatesterkunde det konstateras att alla implementerade funktioner, med undantag för ett fåtal, hade kortare exekveringstid än motsvarande funktioner i ursprungsversionen av FreeRTOS.
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Sjöström, Thames Sixten. "Porting a Real-Time Operating System to a Multicore Platform." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-76933.
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This thesis is part of the European MANY project. The goal of MANY is to provide developers with tools to develop software for multi and many-core hardware platforms. This is the first thesis that is part of MANY at Enea. The thesis aims to provide a knowledge base about software on many-core at the Enea student research group. More than just providing a knowledge base, a part of the thesis is also to port Enea's operating system OSE to Tilera's many-core processor TILEpro64. The thesis shall also investigate the memory hierarchy and interconnection network of the Tilera processor. The knowledge base about software on many-core was constrained to investigating the shared memory model and operating systems for many-core. This was achieved by investigating prominent academic research about operating systems for many-core processors. The conclusion was that a shared memory model does not scale and for the operating system case, operating systems shall be designed with scalability as one of the most important requirements. This thesis has implemented the hardware abstraction layer required to execute a single-core version of OSE on the TILEpro architecture. This was done in three steps. The Tilera hardware and the OSE software platform were investigated. After that, an OSE target port was chosen as reference architecture. Finally, the hardware dependent parts of the reference software were modified. A foundation has been made for future development.
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Yan, Lin Wu. "A Lightweight Framework for Tracing andVisualizing Real-Time Operating Systems." Thesis, Högskolan Väst, Institutionen för ekonomi och it, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:hv:diva-4428.
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System tracing is a helpful method for engineersand users to know exactly what happens in an operating system,especially in real-time operating systems (RTOS), because forreal-time system, it is normally more difficult to know theperformance of hardware and software than for desktopcomputers. Although this kind of tracing tools already exist forsome commercial RTOS, it is fairly hard to see those tools forsmall or open source RTOS. Moreover, because the structure andimplementation of different RTOS varies, it is rare to find aframework that can easily be ported to those platforms. In thisthesis, a solution is presented to this general tracing problem ondifferent platforms. By using the portable framework, it ispossible to implement tracing component into a real timeoperating system by some simple reconfigurations. This platformportability feature is accomplished by separating the specificplatform logic from the logic of the tracing part. Finally, adeployment of this framwork onto a small open source real-timeoperating system—AtomThreads, running on an AVRATmega1650 – is used as a demonstration of this framework.
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Nordström, Susanna. "Configurable Hardware Support for Single Processor Real-Time Systems." Licentiate thesis, Mälardalen University, School of Innovation, Design and Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-528.
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<p>This thesis describes a further development of a building block for programmable devices in embedded systems handling real-time functionality.</p><p>Embedded systems are included in a variety of products within different technical areas such as industrial automation, consumer electronics, automotive industry, and communication-, and multimedia systems. Products ranging from trains and airplanes to microwave ovens and washing machines are controlled by embedded systems.</p><p>Programmable devices constitute a part of these embedded systems. Today, a programmable device can include a complete system containing building blocks connected with each other via programs written using a hardware description language. The programmable devices can be programmed and changed over and over again and this flexibility makes it possible to explore how these building blocks can best be designed in relation to system requirements, before final implementation.</p><p>This thesis describes a further development of a building block for programmable devices implemented in a non-traditional way, i.e., the implementation is written using both hardware description language and traditional software languages. This new building block handles real-time functionality in a non-traditional way that enables certain benefits, such as increased performance, predictability and less memory consumption. Using a non-traditional implementation also has its drawbacks, and e.g., extensions and adjustments can be hard to handle since modifications are required in both hardware and software programming languages.</p><p>The new building block was investigated in order to see how it could be facilitated when used for real-time functionality. The configurability of the block was extended which enables further customization of the building block. This leads to the possibility to use the block within a wider spectrumof applications. It is also possible to reduce the size and cost of the final product since resource usage can be optimized.</p><p>Furthermore, a mathematicalmodel estimating resource usage for real-time functionality has been developed. The model enables distinctive trade-offs comparisons, and guidance for system designers, when considering what type of real-time operating system to use in a certain design.</p>
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Sepulveda, Florez Daniel Mauricio. "Stress Injection Study on Hard Real-Time Operating Systems." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020. http://amslaurea.unibo.it/20261/.
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The automotive software complexity has increased exponentially in the last 30 years. Nowadays, automotive applications are built on top of hard real-time operating system where many tasks are executed. Due to the automotive high integration levels and the time-to-market, software integration and robustness tests should be performed effectively and efficiently. Infineon Technologies for the AURIX 2G microcontroller has integrated a novel hardware architecture to support the Resource Usage Test and the Stress Test. Despite this hardware support, it has never been used before. Then, it is critical to propose a method to efficiently use this structure and to allow the evaluation of the performance and reliability of the chips.
This thesis develops a method and a tool that uses stress injection to analyze the performance, robustness values and boundaries of hard real-time systems under different scenarios. The designer is able: i) to configure the embedded debugging hardware architecture to efficiently explore different stress scenarios; ii) to gather information; and to quantify different types of performance and robustness metrics. The method is automated and fully parameterizable. The developed tool in this thesis is called Galenus, it is integrated into the already existing internal debugging environment of Infineon Technologies for the AURIX microcontroller. The stress injection is based on the reduction of the effective performance of a SoC component (e.g., TriCore within AURIX). The stress injection allows to assess the sensitivity of the SoC under different stress scenarios. These scenarios are defined on the offline initial state using formal methods of scheduling theory. Using the stress injection method, the SoC designer can identify possible risk scenarios testing the performance and robustness of the system at runtime. This thesis is based on the stress injection by CPU suspension within two types of software application, RTOS and Bare-metal.
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Lee, Young Joon. "The real-time implementation of hardware-in-the-loop systems on different RTOS platforms." Thesis, Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15942.
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Borges, Rodrigo Weissmann. "Aplicabilidade de sistemas operacionais de tempo real (RTOS) para sistemas embarcados de baixo custo e pequeno porte." Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/18/18152/tde-09082011-081631/.
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Sistemas embarcados ganham cada vez mais espaço devido ao aumento da demanda por novas funções em equipamentos, às normas regulatórias e às novas necessidades dos consumidores e do mercado. Esse aumento nos requisitos aumenta o tamanho e a complexidade dos softwares embarcados cuja importância cresce significativamente. Sistemas operacionais de tempo real constituem uma ferramenta poderosa para gerenciar a complexidade, facilitar o reuso e aumentar a portabilidade do software e também reduzir o time-to-market. Este trabalho visa avaliar a aplicabilidade de sistemas operacionais de tempo real em sistemas embarcados de baixo custo que utilizam microprocessadores pequenos (8 e 16 bits), avaliando suas características e propondo as melhores alternativas para desenvolvimento de software embarcado. Para o atendimento desta proposta, foi realizado o levantamento de características sobre o desenvolvimento brasileiro de sistemas embarcados, uma análise das características de sistemas de pequeno porte, uma discussão da viabilidade do uso de RTOS e um estudo de caso comparando arquiteturas de software embarcado. Os resultados principais mostram que arquiteturas simplificadas como a Superloop apresentam vantagem sobre os sistemas operacionais devido ao baixo consumo de memória e processamento. Os sistemas operacionais, apesar de propiciarem desenvolvimentos de códigos modulares bem como facilitar o gerenciamento de tempo, são de difícil implementação em microcontroladores pequenos, devido ao seu elevado consumo de memória e processamento. O uso de sistemas operacionais é viável para sistemas de pequeno porte com no mínimo 4 Kbytes de memória RAM e processos com limite de tempo máximo para execução (deadlines) superiores a 1 ms, condições essas que evitam a sobrecarga do microcontrolador. Neste trabalho também é mostrado um retrato do desenvolvimento de embarcados no Brasil.<br>Embedded systems, more and more are gaining importance, due to the increase of features requested on equipments, the regulatory standards and the costumers and market requirements. This increment on requirements increases the software size and complexity, which importance significantly grows. Real-time operating systems represents a powerful tool to manage the complexity, help the software reuse and improve portability of the software and also reduce the time-to-market. This work aims to analyze the real-time operating systems, verifying their application on low cost embedded systems using small microcontrollers (8 and 16-bit), evaluating their characteristics and propose the best architectures for software development. To attend this proposal, it was performed a survey of Brazilian embedded system development, evaluates the low cost embedded system characteristics, discusses the viability of RTOS usage and performs a comparative study of embedded software architectures. Results show that simplified architectures like the Superloop presents vantages over the operating systems due to their low memory and processing consumption. The operating system, besides helping on time management and code modularity, is difficult to implement in small microcontrollers, due to the high memory and processing consumption. The operating systems are more applicable to small embedded systems with at minimum 4 Kbytes of RAM memory and process with maximum execution time (deadlines) over 1 ms, conditions that do not causes microcontroller overload. In this work is also presented an overview of Brazilian embedded system development.
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Midéus, Gustav, and Chavez Antonio Morales. "RISC-V Thread Isolation : Using Zephyr RTOS." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-279100.
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Many embedded systems lack a memory management unit (MMU) and thus often also lack protection of memory. This causes these systems to be less robust since the operating system (OS), processes, and threads are no longer isolated from each other. This is also a potential security issue and with the number of embedded systems rapidly increasing as a result of the rise of Internet of things (IoT), vulnerabilities like this could become a major problem. However, with a recent update to the RISC-V processor architecture, a possibility to isolate regions of memory without an MMU was introduced. This study aims to identify problems and possibilities of implementing such memory protection with RISC-V. Based on a study of literature and documentation on memory protection and the RISC-V architecture, a prototype was designed and implemented to determine potential problems and evaluate performance in terms of execution time and memory cost. The developed prototype showed aworking implementation of memory protection for the memory regions with RISC-V. The evaluation of the prototype demonstrated an increase in context switch execution time and memory usage. The results indicate that the implemented memory protection comes with an increased cost in performance with a constant factor and a small memory overhead. Therefore, it is recommended that implementations that wish to implement memory protection with RISC-V on smaller embedded systems where time and memory may be crucial takes the overhead in consideration. Further research and testing is needed to identify optimizations that could improve the performance as well as discover security flaws.<br>Många inbyggda system saknar en enhet för minneshantering (s.k. MMU) och saknar därför oftast minnesskydd. Detta leder till att dessa system blir mindre robusta eftersom operativsystemet, processer och trådar inte längre är isolerade från varandra. Detta är också en säkerhetsbrist och med antalet inbyggda system som snabbt ökar på grund av tillväxten av Internet of things (IoT), så kan sårbarheter som denna bli ett stort problem. Med en nyligen introducerad uppdatering av RISC-Vprocessor arkitekturen, så introducerades en möjlighet till att isolera minne utan hjälp av en MMU. Denna studie syftar till att identifiera problem och möjligheter av att implementera sådant minneskydd med RISC-V. Baserat på en studie av litteratur och dokumentation om minnesskydd och RISC-V arkitekturen designades och implementerades en prototyp för att hjälpa till att fastställa problem och möjligheter samt göra en utvärdering med avseende på prestanda- och minneskostnader. Den utvecklade prototypen visade en fungerande implementering av minneskydd för minnesregioner med RISC-V. Utvärderingen av prototypen visade en ökad exekveringstid för kontextbyten och ökad minnesanvändning. Resultaten indikerar att det implementerade minneskyddet kommer med en ökad kostnad i prestanda med en konstant faktor och en liten omkostnad i minne. Därför rekommenderas att implementeringar som vill implementera minneskydd med RISC-V på mindre inbyggda system där tid och minne kan vara avgörande tar hänsyn till omkostnaderna. Ytterligare studier och tester behövs för att identifiera optimeringar som kan förbättra prestandan och upptäcka säkerhetsbrister.
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Wassi-Leupi, Guy. "Online scheduling for real-time multitasking on reconfigurable hardware devices." Thesis, Bucks New University, 2011. http://bucks.collections.crest.ac.uk/9992/.
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Nowadays the ever increasing algorithmic complexity of embedded applications requires the designers to turn towards heterogeneous and highly integrated systems denoted as SoC (System-on-a-Chip). These architectures may embed CPU-based processors, dedicated datapaths as well as recon gurable units. However, embedded SoCs are submitted to stringent requirements in terms of speed, size, cost, power consumption, throughput, etc. Therefore, new computing paradigms are required to ful l the constraints of the applications and the requirements of the architecture. Recon gurable Computing is a promising paradigm that provides probably the best trade-o between these requirements and constraints. Dynamically recon gurable architectures are their key enabling technology. They enable the hardware to adapt to the application at runtime. However, these architectures raise new challenges in SoC design. For example, on one hand, designing a system that takes advantage of dynamic recon guration is still very time consuming because of the lack of design methodologies and tools. On the other hand, scheduling hardware tasks di ers from classical software tasks scheduling on microprocessor or multiprocessors systems, as it bears a further complicated placement problem. This thesis deals with the problem of scheduling online real-time hardware tasks on Dynamically Recon gurable Hardware Devices (DRHWs). The problem is addressed from two angles : (i) Investigating novel algorithms for online real-time scheduling/placement on DRHWs. (ii) Scheduling/Placement algorithms library for RTOS-driven Design Space Exploration (DSE). Regarding the first point, the thesis proposes two main runtime-aware scheduling and placement techniques and assesses their suitability for online real-time scenarios. The first technique discusses the impact of synthesizing, at design time, several shapes and/or sizes per hardware task (denoted as multi-shape task), in order to ease the online scheduling process. The second technique combines a looking-ahead scheduling approach with a slots-based recon gurable areas management that relies on a 1D placement. The results show that in both techniques, the scheduling and placement quality is improved without signi cantly increasing the algorithm time complexity. Regarding the second point, in the process of designing SoCs embedding recon gurable parts, new design paradigms tend to explore and validate as early as possible, at system level, the architectural design space. Therefore, the RTOS (Real-Time Operating System) services that manage the recon gurable parts of the SoC can be re fined. In such a context, gathering numerous hardware tasks scheduling and placement algorithms of various complexity vs performance trade-o s in a kind of library is required. In this thesis, proposed algorithms in addition to some existing ones are purposely implemented in C++ language, in order to insure the compatibility with any C++/SystemC based SoC design methodology.
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Lorenc, Ján. "Porovnání vlastností a výkonnosti jader uC/OS-II a uC/OS-III." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255364.
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This master's thesis is focused on benchmarking of Real-Time Operating Systems uC/OS-II and uC/OS-III . It describes the basic features of these systems and metrics used for benchmarking of Real-Time Operating Systems. Selected test methods are implemented and based on them are then compared the performance of Real-Time Operating Systems uC/OS-II and uC/OS-III .
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Paolillo, Antonio. "Optimisation of Performance Metrics of Embedded Hard Real-Time Systems using Software/Hardware Parallelism." Doctoral thesis, Universite Libre de Bruxelles, 2018. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/277427.
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Optimisation of Performance Metrics of Embedded Hard Real-Time Systems using Software/Hardware Parallelism. Nowadays, embedded systems are part of our daily lives.Some of these systems are called safetycritical and have strong requirements in terms of safety and reliability.Additionally, these systems must have a long autonomy, good performance and minimal costs.Finally, these systems must exhibit predictable behaviour and provide their results within firm deadlines.When these different constraints are combined in the requirement specifications of a modern product, classic design techniques making use of single core platforms are not sufficient.Academic research in the field of real-time embedded systems has produced numerous techniques to exploit the capabilities of modern hardware platforms.These techniques are often based on using parallelism inherently present in modern hardware to improve the system performance while reducing the platform power dissipation.However, very few systems existing on the market are using these state-of-the-art techniques.Moreover, few of these techniques have been validated in the context of practical experiments.In this thesis, we realise the study of operating system level techniques allowing to exploit hardware parallelism through the implementation of parallel software in order to boost the performance of target applications and to reduce the overall system energy consumption while satisfying strict application timing requirements.We detail the theoretical foundations of the ideas applied in the dissertation and validate these ideas through experimental work.To this aim, we use a new Real-Time Operating System kernel written in the context of the creation of a spin-off of the Université libre de Bruxelles.Our experiments are based on the execution of applications on the operating system which run on a real-world platform for embedded systems.Our results show that, compared to traditional design techniques, using parallel and power-aware scheduling techniques in order to exploit hardware and software parallelism allows to execute embedded applications with substantial savings in terms of energy consumption.We present future and ongoing research work that exploit the capabilities of recent embedded platforms.These platforms combine multi-core processors and reconfigurable hardware logic, allowing further improvements in performance and energy consumption.<br>Optimisation de Métriques de Performances de Systèmes Embarqués Temps Réel Durs par utilisation du Parallélisme Logiciel et Matériel. De nos jours, les systèmes embarqués font partie intégrante de notre quotidien.Certains de ces systèmes, appelés systèmes critiques, sont soumis à de fortes contraintes de fiabilité et de robustesse.De plus, des contraintes de coûts, d’autonomie et de performances s’additionnent à la fiabilité.Enfin, ces systèmes doivent très souvent respecter des délais très stricts de façon prédictible.Lorsque ces différentes contraintes sont combinées dans le cahier de charge d’un produit, les techniques classiques de conception consistant à utiliser un seul cœur d’un processeur ne suffisent plus.La recherche académique dans le domaine des systèmes embarqués temps réel a produit de nombreuses techniques pour exploiter les plate-formes modernes.Ces techniques sont souvent basées sur l’exploitation du parallélisme inhérent au matériel pour améliorer les performances du système et la puissance dissipée par la plate-forme.Cependant, peu de systèmes existant sur le marché exploitent ces techniques de la littérature et peu de ces techniques ont été validées dans le cadre d’expériences pratiques.Dans cette thèse, nous réalisons l’étude des techniques, au niveau du système d’exploitation, permettant l’exploitation du parallélisme matériel par l’implémentation de logiciels parallèles afin de maximiser les performances et réduire l’impact sur l’énergie consommée tout en satisfaisant les contraintes temporelles strictes du cahier de charge applicatif. Nous détaillons les fondements théoriques des idées qui sont appliquées dans la dissertation et nous les validons par des travaux expérimentaux.A ces fins, nous utilisons le nouveau noyau d’un système d’exploitation écrit dans le cadre de la création d’une spin-off de l’Université libre de Bruxelles.Nos expériences, basées sur l’exécution d’applications sur le système d’exploitation qui s’exécute lui-même sur une plate-forme embarquée réelle, montre que l’utilisation de techniques d’ordonnancement exploitant le parallélisme matériel et logiciel permet de larges économies d’énergie consommée lors de l’exécution d’applications embarquées.De futurs travaux en cours de réalisation sont présentés.Ceux-ci exploitent des plate-formes innovantes qui combinent processeurs multi-cœurs et matériel reconfigurable, permettant d’aller encore plus loin dans l’amélioration des performances et les gains énergétiques.<br>Doctorat en Sciences<br>info:eu-repo/semantics/nonPublished
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Haur, Imane. "AUTOSAR compliant multi-core RTOS formal modeling and verification." Electronic Thesis or Diss., Ecole centrale de Nantes, 2022. http://www.theses.fr/2022ECDN0057.
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La vérification formelle est une solution pour augmenter la fiabilité de l’implémentation du système. Dans notre travail de thèse, nous nous intéressons à l’utilisation de ces méthodes pour la vérification des systèmes d’exploitation multi-coeurs temps réel. Nous proposons une approche de model-checking utilisant les réseaux de Petri temporels, étendus avec des transitions colorées et des fonctionnalités de haut niveau. Nous utilisons ce formalisme pour modéliser le système d’exploitation multi-coeur Trampoline, conforme aux standards OSEK/VDX etAUTOSAR. Nous définissons dans un premier temps ce formalisme et montrons son adéquation avec la modélisation de systèmes concurrents temps reel. Nous utilisons ensuite ce formalisme pour modéliser le système d’exploitation multi-coeur Trampoline et vérifions par model-checking sa conformité avec le standard AUTOSAR. À partir de ce modèle, nous pouvons vérifier des propriétés aussi bien sur l’OS que sur l’application telles que l’ordonnançabilité d’un système tempsréel ainsi que les mécanismes de synchronisation : accès concurrents aux structures de données du système d’exploitation, ordonnancement multi-coeur et traitement des interruptions inter-coeur. À titre d’illustration, cette méthode a permis l’identification automatique de deux erreurs possibles de l’OS Trampoline dans l’exécution concurrente, montrant une protection insuffisante des données et une synchronisation défectueuse<br>Formal verification is a solution to increase the system’s implementation reliability. In our thesis work, we are interestedin using these methods to verify multi-core RTOS. We propose a model-checking approach using time Petri nets extended with colored transitions and high-level features. We use this formalism to model the Trampoline multi-core OS, compliant with the OSEK/VDX and AUTOSAR standards. We first define this formalism and show its suitability for modeling real-time concurrent systems. We then use this formalism to model the Trampoline multi-core RTOS and verify by model-checkingits conformity with the AUTOSAR standard. From this model, we can verify properties of both the OS and the application, such as the schedulability of a real-time system and the synchronization mechanisms: concurrent access to the data structures of the OS, multicore scheduling, and inter-core interrupt handling. As an illustration, this method allowed the automatic identification of two possible errors of the Trampoline OS in concurrent execution, showing insufficient data protection andfaulty synchronization
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Mzid, Rania. "Rétro-ingénierie des plateformes pour le déploiement des applications temps-réel." Thesis, Brest, 2014. http://www.theses.fr/2014BRES0065/document.
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Les travaux présentés dans cette thèse s’inscrivent dans le cadre du développement logiciel des systèmes temps réel embarqués. Nous définissons dans ce travail une méthodologie nommée DRIM. Cette méthodologie permet de guider le déploiement des applications temps réel sur différents RTOS en suivant la ligne de l’IDM et en assurant le respect des contraintes de temps après le déploiement. L’automatisation de la méthodologie DRIM montre sa capacité à détecter les descriptions non-implémentables de l’application, réalisées au niveau conception, pour un RTOS donné, ce qui présente l’avantage de réduire le temps de mise sur le marché d’une part et de guider l’utilisateur pour un choix approprié de l’RTOS cible d’autre part<br>The main purpose of this Phd is to contribute to the software development of real-time embedded systems. We define in this work a methodology named DRIM: Design Refinement toward Implementation Methodology. This methodology aims to guide the deployment of a real-time application on to different RTOS while respecting MDE principals and ensuing that the timing properties are still met after deployment. The automation of DRIM shows its ability to detect non-implementable design models describing the real-time application, on aparticular RTOS, which permits to reduce the time-to-market on the one hand and guide the user to the selection of the appropriate RTOS from the other hand
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Šubr, Jiří. "Porovnání RT vlastností 8-bitových a 32-bitových implementací jádra uC/OS-II." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2013. http://www.nusl.cz/ntk/nusl-236389.
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This thesis concerns of benchmarking $\mu$C/OS-II systems on different microcontroller architectures. The thesis describes COS-II microcontroller core and possible series of benchmark tests which can be used. Selected tests are implemented and measured properties of microcontrollers with different architecture are compared.
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Čižinský, Vojtěch. "Implementace pokročilých mechanismů plánování množin RT úloh běžících pod uC/OS-II." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2010. http://www.nusl.cz/ntk/nusl-237270.
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This thesis deals with extensions of uC/OS-II kernel services. These extensions are about advanced task scheduling mechanisms. Source code of this operating system is wide open and can be, in accordance with licence agreement, modified and extended with additional capabilities. Functionality of implemented scheduling algorithms is at the end verified using tools Cheddar and TimesTool.
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Krejčí, Roman. "Řízení modelu v reálném čase." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221296.
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This diploma thesis deals with control the Ball on the wheel system in real time. In the first part there is made mathematical model of system, which is described by state equations. Then the laboratory model of Ball on the wheel system and its parts are described. The laboratory model consists servo drive, servo amplifier, microcontroller with real-time operating system and distance sensors. In the practical part of the thesis there is designed control of system by linear quadratic regulator and its implementation with control peripherals into microcontroller with real-time operating system. Ball on the wheel system is controlled by microcontroller, which sends a commands to servo amplifier by CAN bus.
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Poczekajlo, Xavier. "Ordonnancement efficace de systèmes embarqués temps réel strict sur plates-formes hétérogènes." Doctoral thesis, Universite Libre de Bruxelles, 2020. https://dipot.ulb.ac.be/dspace/bitstream/2013/313478/3/TOC.pdf.
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Les systèmes embarqués sont de plus en plus présents dans notre quotidien, à l’instar des téléphones ou des équipements des voitures modernes. Les systèmes embarqués modernes utilisent des plates-formes de plus en plus complexes. Après avoir longtemps utilisé un seul processeur, les plates-formes modernes peuvent désormais contenir plusieurs processeurs. Depuis quelques années, afin de continuer à améliorer la performance de ces systèmes à moindre coût, certaines de ces plates-formes embarquent désormais plusieurs processeurs différents, parfois même capables de modifier rapidement leurs caractéristiques pendant l’exécution du système. C’est ce qu’on appelle des plates-formes hétérogènes.Cette thèse traite de l’ordonnancement d’applications temps réel strict pour des plates-formes hétérogènes reconfigurables. Établir une polituqe d’ordonnancement consiste à garantir l’exécution d’ensembles de tâches récurrentes, avec le respect des contraintes temporelles de chaque tâche. Dans un contexte de temps réel strict, une tâche doit nécessairement être pleinement exécutée avant son échéance. Tout retard pourrait compromettre la sécurité du système ou des utilisateurs.Produire un ordonnancement temps réel strict efficace pour de telles plates-formes hétérogènes est particulièrement difficile. En effet, la vitesse d’exécution d’un processeur d’une telle plates-forme dépend à la fois du type du processeur et de la tâche exécutée. Cela rend les tâches difficilement interchangeables et augmente ainsi considérablement la complexité des polituqes d’ordonnancement. De plus, le coût d’une migration – le déplacement d’une tâche en cours d’exécution – d’un processeur à un autre est élevé, ce qui peut rendre les polituqes d’ordonnancement peu efficaces en pratique.Dans cette thèse, deux voies sont explorées pour tirer parti des possibilités offertes par ces plates-formes hétérogènes. Tout d’abord, en proposant un ordonnanceur dit global, qui permet une utilisation théorique de l’entièreté de la plates-forme. Pour atteindre cet objectif, nous isolons différents sous-problèmes, en suivant un schéma établi par la littérature existante. Pour chaque sous-problème, nous proposons une amélioration significative par rapport à l’état de l’art. L’ensemble constitue un nouvel ordonnanceur. Une évaluation empirique montre que ses performances sont bien supérieures à celles des ordonnanceurs existants. De plus, la polituqe d’ordonnancement proposée a une meilleure applicabilité, car elle réduit le nombre de migrations d’un processeur à un autre.Une deuxième voie explorée est le paradigme d’application dite multimode. Nous proposons ici le premier modèle où le matériel comme le logiciel peuvent être modifiés pendant l’exécution de l’application, afin de s’adapter au contexte dans lequel elle se trouve. Enfin, deux nouveaux protocoles utilisant ce modèle sont proposés et évalués. Il est montré théoriquement et empiriquement que ces protocoles présentent une faible complexité et de bonnes performances, et correspondent donc au besoin d’applications réelles.<br>Doctorat en Sciences<br>info:eu-repo/semantics/nonPublished
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Roker, I. G. R. J. "A real-time operating system." Thesis, University of Bath, 1986. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.375638.
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Pinnix, Justin Everett. "Operating System Kernel for All Real Time Systems." NCSU, 2001. http://www.lib.ncsu.edu/theses/available/etd-20010310-181302.
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<p><P>PINNIX, JUSTIN EVERETT. Operating System Kernel for All Real Time Systems.(Under the direction of Robert J. Fornaro and Vicki E. Jones.)</P><P>This document describes the requirements, design, and implementation of OSKAR, ahard real time operating system for Intel Pentium compatible personal computers.OSKAR provides rate monotonic scheduling, fixed and dynamic priority scheduling,semaphores, message passing, priority ceiling protocols, TCP/IP networking, and globaltime synchronization using the Global Positioning System (GPS). It is intended toprovide researchers a test bed for real time projects that is inexpensive, simple tounderstand, and easy to extend.</P><P>The design of the system is described with special emphasis on design tradeoffs made toimprove real time requirements compliance. The implementation is covered in detail atthe source code level. Experiments to qualify functionality and obtain performanceprofiles are included and the results explained.</P><P>
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Lee, Rusty (Rusty Shawn) 1978. "VORTOS : Versatile Object-oriented Real-Time Operating System." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/16770.
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Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.<br>Includes bibliographical references (p. 79-80).<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>As computer software has become more complex in response to increasing demands and greater levels of abstraction, so have computer operating systems. In order to achieve the desired level of functionality, operating systems have become less flexible and overly complex. The additional complexity and abstraction introduced often leads to less efficient use of hardware and increased hardware requirements. In embedded systems with limited hardware resources, efficient resource use is extremely important to the functionality of the resources. Therefore, operating system functionality not useful for the embedded system's applications is detrimental to the system. Component-based software provides a way to achieve both the efficient application-specific functionality required in embedded systems and the ability to extend this functionality to other applications. This thesis presents a component-based operating system, VORTOS, the Versatile Object-oriented Real-Time Operating System. VORTOS uses a virtual machine to abstract the hardware, eliminating the need for further portability abstractions within the operating system and application level components. The simple modular component architecture allows both the operating system and user applications to be extremely flexible by allowing them to utilize the particular components required, without sacrificing performance.<br>by Rusty Lee.<br>M.Eng.and S.B.
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Gracioli, Giovani. "Real-time operating system support for multicore applications." reponame:Repositório Institucional da UFSC, 2014. https://repositorio.ufsc.br/xmlui/handle/123456789/129575.
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Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia de Automação e Sistemas, Florianópolis, 2014<br>Made available in DSpace on 2015-02-05T21:15:28Z (GMT). No. of bitstreams: 1
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Previous issue date: 2014<br>Plataformas multiprocessadas atuais possuem diversos níveis da memória cache entre o processador e a memória principal para esconder a latência da hierarquia de memória. O principal objetivo da hierarquia de memória é melhorar o tempo médio de execução, ao custo da previsibilidade. O uso não controlado da hierarquia da cache pelas tarefas de tempo real impacta a estimativa dos seus piores tempos de execução, especialmente quando as tarefas de tempo real acessam os níveis da cache compartilhados. Tal acesso causa uma disputa pelas linhas da cache compartilhadas e aumenta o tempo de execução das aplicações. Além disso, essa disputa na cache compartilhada pode causar a perda de prazos, o que é intolerável em sistemas de tempo real críticos. O particionamento da memória cache compartilhada é uma técnica bastante utilizada em sistemas de tempo real multiprocessados para isolar as tarefas e melhorar a previsibilidade do sistema. Atualmente, os estudos que avaliam o particionamento da memória cache em multiprocessadores carecem de dois pontos fundamentais. Primeiro, o mecanismo de particionamento da cache é tipicamente implementado em um ambiente simulado ou em um sistema operacional de propósito geral. Consequentemente, o impacto das atividades realizados pelo núcleo do sistema operacional, tais como o tratamento de interrupções e troca de contexto, no particionamento das tarefas tende a ser negligenciado. Segundo, a avaliação é restrita a um escalonador global ou particionado, e assim não comparando o desempenho do particionamento da cache em diferentes estratégias de escalonamento. Ademais, trabalhos recentes confirmaram que aspectos da implementação do SO, tal como a estrutura de dados usada no escalonamento e os mecanismos de tratamento de interrupções, impactam a escalonabilidade das tarefas de tempo real tanto quanto os aspectos teóricos. Entretanto, tais estudos também usaram sistemas operacionais de propósito geral com extensões de tempo real, que afetamos sobre custos de tempo de execução observados e a escalonabilidade das tarefas de tempo real. Adicionalmente, os algoritmos de escalonamento tempo real para multiprocessadores atuais não consideram cenários onde tarefas de tempo real acessam as mesmas linhas da cache, o que dificulta a estimativa do pior tempo de execução. Esta pesquisa aborda os problemas supracitados com as estratégias de particionamento da cache e com os algoritmos de escalonamento tempo real multiprocessados da seguinte forma. Primeiro, uma infraestrutura de tempo real para multiprocessadores é projetada e implementada em um sistema operacional embarcado. A infraestrutura consiste em diversos algoritmos de escalonamento tempo real, tais como o EDF global e particionado, e um mecanismo de particionamento da cache usando a técnica de coloração de páginas. Segundo, é apresentada uma comparação em termos da taxa de escalonabilidade considerando o sobre custo de tempo de execução da infraestrutura criada e de um sistema operacional de propósito geral com extensões de tempo real. Em alguns casos, o EDF global considerando o sobre custo do sistema operacional embarcado possui uma melhor taxa de escalonabilidade do que o EDF particionado com o sobre custo do sistema operacional de propósito geral, mostrando claramente como diferentes sistemas operacionais influenciam os escalonadores de tempo real críticos em multiprocessadores. Terceiro, é realizada uma avaliação do impacto do particionamento da memória cache em diversos escalonadores de tempo real multiprocessados. Os resultados desta avaliação indicam que um sistema operacional "leve" não compromete as garantias de tempo real e que o particionamento da cache tem diferentes comportamentos dependendo do escalonador e do tamanho do conjunto de trabalho das tarefas. Quarto, é proposto um algoritmo de particionamento de tarefas que atribui as tarefas que compartilham partições ao mesmo processador. Os resultados mostram que essa técnica de particionamento de tarefas reduz a disputa pelas linhas da cache compartilhadas e provê garantias de tempo real para sistemas críticos. Finalmente, é proposto um escalonador de tempo real de duas fases para multiprocessadores. O escalonador usa informações coletadas durante o tempo de execução das tarefas através dos contadores de desempenho em hardware. Com base nos valores dos contadores, o escalonador detecta quando tarefas de melhor esforço o interferem com tarefas de tempo real na cache. Assim é possível impedir que tarefas de melhor esforço acessem as mesmas linhas da cache que tarefas de tempo real. O resultado desta estratégia de escalonamento é o atendimento dos prazos críticos e não críticos das tarefas de tempo real.<br><br>Abstracts: Modern multicore platforms feature multiple levels of cache memory placed between the processor and main memory to hide the latency of ordinary memory systems. The primary goal of this cache hierarchy is to improve average execution time (at the cost of predictability). The uncontrolled use of the cache hierarchy by realtime tasks may impact the estimation of their worst-case execution times (WCET), specially when real-time tasks access a shared cache level, causing a contention for shared cache lines and increasing the application execution time. This contention in the shared cache may leadto deadline losses, which is intolerable particularly for hard real-time (HRT) systems. Shared cache partitioning is a well-known technique used in multicore real-time systems to isolate task workloads and to improve system predictability. Presently, the state-of-the-art studies that evaluate shared cache partitioning on multicore processors lack two key issues. First, the cache partitioning mechanism is typically implemented either in a simulated environment or in a general-purpose OS (GPOS), and so the impact of kernel activities, such as interrupt handlers and context switching, on the task partitions tend to be overlooked. Second, the evaluation is typically restricted to either a global or partitioned scheduler, thereby by falling to compare the performance of cache partitioning when tasks are scheduled by different schedulers. Furthermore, recent works have confirmed that OS implementation aspects, such as the choice of scheduling data structures and interrupt handling mechanisms, impact real-time schedulability as much as scheduling theoretic aspects. However, these studies also used real-time patches applied into GPOSes, which affects the run-time overhead observed in these works and consequently the schedulability of real-time tasks. Additionally, current multicore scheduling algorithms do not consider scenarios where real-time tasks access the same cache lines due to true or false sharing, which also impacts the WCET. This thesis addresses these aforementioned problems with cache partitioning techniques and multicore real-time scheduling algorithms as following. First, a real-time multicore support is designed and implemented on top of an embedded operating system designed from scratch. This support consists of several multicore real-time scheduling algorithms, such as global and partitioned EDF, and a cache partitioning mechanism based on page coloring. Second, it is presented a comparison in terms of schedulability ratio considering the run-time overhead of the implemented RTOS and a GPOS patched with real-time extensions. In some cases, Global-EDF considering the overhead of the RTOS is superior to Partitioned-EDF considering the overhead of the patched GPOS, which clearly shows how different OSs impact hard realtime schedulers. Third, an evaluation of the cache partitioning impacton partitioned, clustered, and global real-time schedulers is performed.The results indicate that a lightweight RTOS does not impact real-time tasks, and shared cache partitioning has different behavior depending on the scheduler and the task's working set size. Fourth, a task partitioning algorithm that assigns tasks to cores respecting their usage of cache partitions is proposed. The results show that by simply assigning tasks that shared cache partitions to the same processor, it is possible to reduce the contention for shared cache lines and to provideHRT guarantees. Finally, a two-phase multicore scheduler that provides HRT and soft real-time (SRT) guarantees is proposed. It is shown that by using information from hardware performance counters at run-time, the RTOS can detect when best-effort tasks interfere with real-time tasks in the shared cache. Then, the RTOS can prevent best effort tasks from interfering with real-time tasks. The results also show that the assignment of exclusive partitions to HRT tasks together with the two-phase multicore scheduler provides HRT and SRT guarantees, even when best-effort tasks share partitions with real-time tasks.
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BOTTO, GIANLUCA. "FPGA Operating System for Hard Real Time Applications." Doctoral thesis, Politecnico di Torino, 2008. http://hdl.handle.net/11583/2501613.
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In mechatronics, as in many others fields, one of the main aspect is the prototyping.
Since the mechatronics covers a lot of complex applications, the availability of a common digital platform to use in all of them is a valid help in the prototyping phase of the project.
FPGAs are often used as software acceleration in reconfigurable computers (RC), in which the operating system is a standard off-the-shelf real time operating system such as Linux and VxWorks.
The object of the first part of the work is to develop a hardware operating system for mechatronic applications, which means that the FPGA device does not host a soft core processor, able to execute one only operation at a time, but it executes many concurrent hard real time functions allowing the user to develop his own application code taking advantage of the main features of the device: concurrency, flexibility and determinism.
The second part of the thesis is related to the project of an electronic module that integrates logic and power devices to drive piezoelectric stack actuators and demonstrate experimentally the results in terms of control of piezoelectric stack tip displacement on atest bench.
The electronic module controls up to four piezoelectric stack actuators and guarantees that the correct tip displacement is reached starting from a desired profile.
The various opening/closing phases of the actuators are tuned in terms of slew rate, timings and values to reach during all the controlled phase.
The control parameters are passed to the control unit by means of a host human machine interface or by an external electronic control unit that acts as a supervisor.
This part will illustrate all the passages of the design starting from the constitutive equations of the piezoelectric material up to the final architecture of the control law and implementation passing through:
• creation of a FEM model of the piezoelectric stack;
• construction of the modal residues model;
• FEM model validation;
• identification of the electrical equivalent circuit of the piezoelectric stack;
• design of the power driver circuit;
• design of the control loops;
A complete model validation is then performed and experimental results are presented.
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Zhang, Ziyu. "Distributed real-time operating system (DRTOS) modeling in SpecC." [Ames, Iowa : Iowa State University], 2006.
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Okyay, Mehmet Onur Aytaç Sıtkı. "A portable real-time operating system for embedded platforms/." [s.l.]: [s.n.], 2004. http://library.iyte.edu.tr/tezler/master/bilgisayaryazilimi/T000477.doc.
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Yu, Ke. "Real-time operating system modelling and simulation using systemC." Thesis, University of York, 2010. http://etheses.whiterose.ac.uk/1088/.
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Increasing system complexity and stringent time-to-market pressure bring challenges to the design productivity of real-time embedded systems. Various System-Level Design (SLD), System-Level Design Languages (SLDL) and Transaction-Level Modelling (TLM) approaches have been proposed as enabling tools for real-time embedded system specification, simulation, implementation and verification. SLDL-based Real-Time Operating System (RTOS) modelling and simulation are key methods to understand dynamic scheduling and timing issues in real-time software behavioural simulation during SLD. However, current SLDL-based RTOS simulation approaches do not support real-time software simulation adequately in terms of both functionality and accuracy, e.g., simplistic RTOS functionality or annotation-dependent software time advance. This thesis is concerned with SystemC-based behavioural modelling and simulation of real-time embedded software, focusing upon RTOSs. The RTOS-centric simulation approach can support flexible, fast and accurate real-time software timing and functional simulation. They can help software designers to undertake real-time software prototyping at early design phases. The contributions in this thesis are fourfold. Firstly, we propose a mixed timing real-time software modelling and simulation approach with various timing related techniques, which are suitable for early software modelling and simulation. We show that this approach not only avoids the accuracy drawback in some existing methods but also maintains a high simulation performance. Secondly, we propose a Live CPU Model to assist software behavioural timing modelling and simulation. It supports interruptible and accurate software timing simulation in SystemC and extends modelling capability of the mixed timing approach for HW/SW interactions. Thirdly, we propose a RTOS-centric real-time embedded software simulation model. It provides a systematic approach for building modular software (including both application tasks and RTOS) simulation models in SystemC. It flexibly supports mixed timing application task models. The functions and timing overheads of the RTOS model are carefully designed and considered. We show that the RTOS-centric model is both convenient and accurate for real-time software simulation. Fourthly, we integrate TLM communication interfaces in the software models, which extend the proposed RTOS-centric software simulation model for SW/HW inter-module TLM communication modelling. As a whole, this thesis focuses on RTOS and real-time software modelling and simulation in the context of SystemC-based SLD and provides guidance to software developers about how to utilise this approach in their real-time software development. The various aspects of research work in this thesis constitute an integrated software Processing Element (PE) model, interoperable with existing TLM hardware and communication modelling.
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Brinkmeyer, Jay Charles 1960. "A multi-tasking operating system for real-time applications." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276589.
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Presented in this thesis is the design and implementation of a fast, compact, and flexible multi-tasking operating system. This system is designed for use in small computers which must deliver real-time performance in extremely constrained environments. The operating system is implemented in the "C" language to allow portability between different computers systems. A number of useful features are provided which support dynamic task management, message passing, a hierarchial file system, device drivers, and a command line interpreter. Modularized construction enables the user to prune unnecessary system features for specific applications. Presently, the system is operational on a personal computer which is also used for system development. This serves as a realistic environment for testing system response to real-time events.
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Smith, Dan, and Doug Steele. "REAL-TIME TELEMETRY ON A PC." International Foundation for Telemetering, 2005. http://hdl.handle.net/10150/604908.
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ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada<br>Near real-time telemetry acquisition, processing and analysis on a desktop PC have always been difficult. Many factors complicate working with real-time data, including operating system latencies, design inefficiencies and hardware limitations. These problems are further compounded when data from multiple sources had to be integrated, increasing design complexity. Current design solutions for analyzing data in near real-time now utilize the latest hardware implementations and software designs, taking advantage of new hardware and language features. This paper will discuss several issues found with PC-based telemetry systems and how new designs are addressing these issues.
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Chen, Bojie. "HUMIDITY SENSOR CIRCUIT USING REAL TIME OPERATING SYSTEM (FREERTOS) KERNEL." UKnowledge, 2014. http://uknowledge.uky.edu/ece_etds/61.
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A humidity sensor can be used to measure the moisture content of the environment. The physical change of the sensor expresses as the change of electrical property like capacitance, resistance, voltage, current, frequency, etc. In order to process these analog signals digitally, microprocessor is involved in the measurement. This thesis presents design of a circuit to measure low moisture levels. The 16-bit RISC mixed signal microcontroller MSP430F249 from Texas Instruments will be used. The circuit has good performance at extremely low humidity levels.
Meanwhile, a small real time operating system kernel FreeRTOS, a market leading RTOS from Real Time Engineer Ltd is ported to the microcontroller. The basic concept about FreeRTOS and how to port this RTOS to MSP430F249 microcontrollers will be the topics of this thesis as well.
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Cheng, Shu. "Formally modelling and verifying the FreeRTOS real-time operating system." Thesis, University of York, 2014. http://etheses.whiterose.ac.uk/12671/.
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Formal methods is an alternative way to develop software, which applies math- ematical techniques to software design and verification. It ensures logical consistency between the requirements and the behaviour of the software, because each step in the development process, i.e., abstracting the requirements, design, refinement and implementation, is verified by mathematical techniques. However, in ordinary software development, the correctness of the software is tested at the end of the development process, which means it is limited and incomplete. Thus formal methods provides higher quality software than ordinary software devel- opment. At the same time, real-time operating systems are playing increasingly more important roles in embedded applications. Formal verification of this kind of software is therefore of strong interest. FreeRTOS has a wide community of users: it is regarded by many as the de facto standard for micro-controllers in embedded applications. This project formally specifies the behaviour of FreeRTOS in Z, and its consistency is ver- ified using the Z/Eves theorem prover. This includes a precise statement of the preconditions for all API commands. Based on this model, (a) code-level annotations for verifying task related API are produced with Microsoft’s Verifying C Complier (VCC); and (b) an abstract model for extension of FreeRTOS to multi-core architectures is specified with the Z notation. This work forms the basis of future work that is refinement of the models to code to produce a verified implementation for both single and multi-core platforms.
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Hyden, Eoin Andrew. "Operating system support for quality of service." Thesis, University of Cambridge, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.319971.
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Sword, Cameron, and Edine Bakker. "¡VAMOS! Viable Alternative Mine Operating System: A Novel Underwater Mining System." Technische Universitaet Bergakademie Freiberg Universitaetsbibliothek "Georgius Agricola", 2018. http://nbn-resolving.de/urn:nbn:de:bsz:105-qucosa-231090.
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The 42-month ¡VAMOS! project (Viable Alternative Mine Operating System, Grant Agreement 642477, vamos-project.eu), co-funded by the European Commission’s Horizon2020 programme, will enable access to reserves of mineral deposits by developing an innovative, safe, clean, and low-visibility underwater inland mining technique.
Through field-testing, ¡VAMOS! hopes to encourage investment in abandoned and prospective EU open-pit mines by providing a viable novel excavation process, ultimately aiming to reduce the EU’s reliance on imports of strategically important raw materials.
The project will test the technological and economic viability of the underwater mining of inland mineral deposits which are currently economically, technologically, and environmentally unobtainable. If proven viable, ¡VAMOS! will enable access to deposits whose excavation has been historically limited by stripping ratio and hydrological and geotechnical considerations. Also, due to low noise and dust levels, and its road-transportable electric-powered system, ¡VAMOS! will be able to be applied safely in both urban-proximal and hard-to-access rural locations.
¡VAMOS! is defined by a remotely-operated underwater mining vehicle, adapted and improved from existing subsea mining technology. Operating in tandem with a remote-controlled sensory assistance-vehicle, the underwater miner will connect to a flexible riser through which mined material will be pumped from the mudline to a land-based dewatering pit via a floating mobile deployment-platform. On the deployment platform, a bypass system will be linked to production measuring equipment and a laser-induced breakdown spectroscopy system, enabling throughput monitoring and real-time grade-control.
Preparatory work has been carried out to assess the regulatory compliance of the project, its likely social and environmental impact, and the steps which need to be taken to reduce and quantify these during testing. Two community stakeholder workshops held in both England and Portugal have indicated that the public is receptive to the concept.
Following an official project design-freeze in October 2016, construction and integration of all components will conclude in June 2017. This will be followed by field-testing at a flooded kaolin-granite quarry in Devon, England in October 2017, with further testing planned at a flooded iron mine in Vareš, Bosnia in June 2018.
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Boman, Simon, and Olof Rutgersson. "Replacing OSE with Real Time capable Linux." Thesis, Department of Computer and Information Science, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18128.
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<p>For many years OSE has been a common used operating system, with real time extensions enhancements, in embed-ded systems. But in the last decades, Linux has grown and became a competitor to common operating systems and, in recent years, even as an operating system with real time extensions. With this in mind, ÅF was interested in replacing the quite expensive OSE with some distribution of the open source based Linux on a PowerPC MPC8360. Therefore, our purpose with thesis is to implement Linux on the named platform and make some tests to see if it is possible to replace OSE with Linux. Using Linux has several advantages, for example it is free of charge to use and over the years the popularity of Linux within the developer community has resulted in numerous tools and utilities available for free.</p><p>As a result, this study shows that Linux with real time extensions on the MPC8360 PowerPC platform is a viable alternative to OSE regarding cost efficiency, flexibility, adaptability and competence available on the market.</p><p>Further studies can be done towards benchmarking for I/O systems and implementing support for more hardware on the MPC8360 AF platform.</p>
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Blake, Carl David. "A REAL-TIME MULTI-TASKING OPERATING SYSTEM FOR GENERAL PURPOSE APPLICATIONS." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275400.
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Roscoe, Timothy. "The structure of a multi-service operating system." Thesis, University of Cambridge, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.363305.
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Sword, Cameron, and Edine Bakker. "¡VAMOS! Viable Alternative Mine Operating System: A Novel Underwater Mining System." TU Bergakademie Freiberg, 2017. https://tubaf.qucosa.de/id/qucosa%3A23174.
Full textAbstract:
The 42-month ¡VAMOS! project (Viable Alternative Mine Operating System, Grant Agreement 642477, vamos-project.eu), co-funded by the European Commission’s Horizon2020 programme, will enable access to reserves of mineral deposits by developing an innovative, safe, clean, and low-visibility underwater inland mining technique.
Through field-testing, ¡VAMOS! hopes to encourage investment in abandoned and prospective EU open-pit mines by providing a viable novel excavation process, ultimately aiming to reduce the EU’s reliance on imports of strategically important raw materials.
The project will test the technological and economic viability of the underwater mining of inland mineral deposits which are currently economically, technologically, and environmentally unobtainable. If proven viable, ¡VAMOS! will enable access to deposits whose excavation has been historically limited by stripping ratio and hydrological and geotechnical considerations. Also, due to low noise and dust levels, and its road-transportable electric-powered system, ¡VAMOS! will be able to be applied safely in both urban-proximal and hard-to-access rural locations.
¡VAMOS! is defined by a remotely-operated underwater mining vehicle, adapted and improved from existing subsea mining technology. Operating in tandem with a remote-controlled sensory assistance-vehicle, the underwater miner will connect to a flexible riser through which mined material will be pumped from the mudline to a land-based dewatering pit via a floating mobile deployment-platform. On the deployment platform, a bypass system will be linked to production measuring equipment and a laser-induced breakdown spectroscopy system, enabling throughput monitoring and real-time grade-control.
Preparatory work has been carried out to assess the regulatory compliance of the project, its likely social and environmental impact, and the steps which need to be taken to reduce and quantify these during testing. Two community stakeholder workshops held in both England and Portugal have indicated that the public is receptive to the concept.
Following an official project design-freeze in October 2016, construction and integration of all components will conclude in June 2017. This will be followed by field-testing at a flooded kaolin-granite quarry in Devon, England in October 2017, with further testing planned at a flooded iron mine in Vareš, Bosnia in June 2018.
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Backeman, Peter, and Erik Gustafsson. "Demonstrating the Effects of Power Management on a Real-time Operating System." Thesis, Uppsala University, Department of Information Technology, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-129477.
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<p>This thesis is part of the GEODES project, dealing with the issues of power optimization, e.g. how to make a systems lifetime longer, at the cost of the quality of the performance, this is called system degradation.</p><p>The objective for this project was develop an application to monitor and visualize the effects of power management (controlled system degradation to minimize power consumption). With such software it is possible to demonstrate the possibilities of so called energy aware systems.</p><p>During the project two scenarios were investigated and implemented, one is a simple state-based monitor. This monitor application can observe and visualize the effects of power management on a computer system. It shows that by utilizing system degradation, the lifetime of a system can be prolonged.</p><p>The other scenario consists of a prototype for a firefighter coordinator application. It allows a rescue leader to observe firefighters at an emergency scene. This application can interact with the power management, by requesting a desired life time of a hand-held device carried by the firefighter. This shows that these techniques can be utilized without knowledge of the underlying power management software.</p>
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Nilsson, Lenny. "Delivering Interactive Real-Time Multi-Media Content with a Secure Operating System." Thesis, Umeå universitet, Institutionen för datavetenskap, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-44359.
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The company Dohi Sweden is developing a user interface product. This interface will deliver interactive content on a multi-touch screen surface. The system will provide a user-friendly way to populate touch-screen surfaces with interactive real-time multi-media contents. The interactive surface is populated by a client computer, connected to the internet. Third party applications will render interactive multi-media content on the touch-screen.This thesis report will provide an operating system (OS), for the client computer, that display interactive multi-media content. Known technologies are presented in the report. These technologies are considered as components for the construction of the OS. The client computer can be a target for different malicious software and penetration attempts. I will address the security risks and different aspects of modern computer security. A proof-of-concept OS will be a subject for security evaluation.
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Dhake, Pravin. "A real time operating system based test-bed for autonomous vehicle navigation." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Dhake_09007dcc803c20b4.pdf.
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Thesis (M.S.)--University of Missouri--Rolla, 2007.<br>Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 28, 2007) Includes bibliographical references (p. 86-87).
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Swim, Bradley Roy. "Predictable dynamic task scheduling in a hard real-time distributed operating system." Thesis, Staffordshire University, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.337215.
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Schäfer, Pierre-Alain. "Dynamic loading and linking native code on a real-time operating system." Instituto Tecnológico de Aeronáutica, 2007. http://www.bd.bibl.ita.br/tde_busca/arquivo.php?codArquivo=473.
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This thesis presents a very efficient and simple approach to native code generation and dynamic code loading for the RTOS RTEMS on the Blackfin architecture. The whole solution is intended for PLCs implementing the IEC 61131-3 standard. The second part of the solution, native code loading on RTEMS, is also usable for code updates in satellite applications. For the code generation modern parser generator tools have been used to implement a language translator from Instruction List to C language. The generated C language is then feed to the freely distributable GCC compiler which generates efficient native code. This native code is later on loaded and executed on a Blackfin CPU. The execution environment RTEMS has been ported to the Blackfin architecture. RTEMS is a hard real-time operating system which has been widely used in space applications. For the dynamic loading and linking of the native code 2 different loaders have been evaluated and compared. Those loaders are of special interest for satellite applications because they allow for much faster software update over slow communication links. The final systems achieves a speedup of approximately 4 compared to a traditional interpreted IEC 61131-3 system.
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Iturbe, Xabier. "Design and implementation of a reliable reconfigurable real-time operating system (R3TOS)." Thesis, University of Edinburgh, 2013. http://hdl.handle.net/1842/9413.
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Twenty-first century Field-Programmable Gate Arrays (FPGAs) are no longer used for implementing simple “glue logic” functions. They have become complex arrays of reconfigurable logic resources and memories as well as highly optimised functional blocks, capable of implementing large systems on a single chip. Moreover, Dynamic Partial Reconfiguration (DPR) capability permits to adjust some logic resources on the chip at runtime, whilst the rest are still performing active computations. During the last few years, DPR has become a hot research topic with the objective of building more reliable, efficient and powerful electronic systems. For instance, DPR can be used to mitigate spontaneously occurring bit upsets provoked by radiation, or to jiggle around the FPGA resources which progressively get damaged as the silicon ages. Moreover, DPR is the enabling technology for a new computing paradigm which combines computation in time and space. In Reconfigurable Computing (RC), a battery of computation-specific circuits (“hardware tasks”) are swapped in and out of the FPGA on demand to hold a continuous stream of input operands, computation and output results. Multitasking, adaptation and specialisation are key properties in RC, as multiple swappable tasks can run concurrently at different positions on chip, each with custom data-paths for efficient execution of specific computations. As a result, considerable computational throughput can be achieved even at low clock frequencies. However, DPR penetration in the commercial market is still testimonial, mainly due to the lack of suitable high-level design tools to exploit this technology. Indeed, currently, special skills are required to successfully develop a dynamically reconfigurable application. In light of the above, this thesis aims at bridging the gap between high-level application and low-level DPR technology. Its main objective is to develop Operating System (OS)-like support for high-level software-centric application developers in order to exploit the benefits brought about by DPR technology, without having to deal with the complex low-level hardware details. The developed solution in this thesis is named as R3TOS, which stands for Reliable Reconfigurable Real-Time Operating System. R3TOS defines a flexible infrastructure for reliably executing reconfigurable hardware-based applications under real-time constraints. In R3TOS, the hardware tasks are scheduled in order to meet their computation deadlines and allocated to non-damaged resources, keeping the system fault-free at all times. In addition, R3TOS envisages a computing framework whereby both hardware and software tasks coexist in a seamless manner, allowing the user to access the advanced computation capabilities of modern reconfigurable hardware from a software “look and feel” environment. This thesis covers all of the design and implementation aspects of R3TOS. The thesis proposes a novel EDF-based scheduling algorithm, two novel task allocation heuristics (EAC and EVC) and a novel task allocation strategy (called Snake), addressing many RC-related particularities as well as technological constraints imposed by current FPGA technology. Empirical results show that these approaches improve on the state of the art. Besides, the thesis describes a novel way to harness the internal reconfiguration mechanism of modern FPGAs to performinter-task communications and synchronisation regardless of the physical location of tasks on-chip. This paves the way for implementing more sophisticated RC solutions which were only possible in theory in the past. The thesis illustrates R3TOS through a proof-of-concept prototype with two demonstrator applications: (1) dependability oriented control of the power chain of a railway traction vehicle, and (2) datastreaming oriented Software Defined Radio (SDR).
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Liew, Kenny Eng Wee. "A distributed real-time operating system for a multi-processor StrongARM network." Thesis, Nottingham Trent University, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.393509.
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Forbes, Harold C. "Operating system principles and constructs for dynamic multi-processor real-time control systems." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/8165.
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Rhee, Sokwoo. "Development of a Windows NT real-time operating system for NC machine control." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/45474.
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Hong, Chuan. "Towards the development of a reliable reconfigurable real-time operating system on FPGAs." Thesis, University of Edinburgh, 2013. http://hdl.handle.net/1842/8948.
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In the last two decades, Field Programmable Gate Arrays (FPGAs) have been rapidly developed from simple “glue-logic” to a powerful platform capable of implementing a System on Chip (SoC). Modern FPGAs achieve not only the high performance compared with General Purpose Processors (GPPs), thanks to hardware parallelism and dedication, but also better programming flexibility, in comparison to Application Specific Integrated Circuits (ASICs). Moreover, the hardware programming flexibility of FPGAs is further harnessed for both performance and manipulability, which makes Dynamic Partial Reconfiguration (DPR) possible. DPR allows a part or parts of a circuit to be reconfigured at run-time, without interrupting the rest of the chip’s operation. As a result, hardware resources can be more efficiently exploited since the chip resources can be reused by swapping in or out hardware tasks to or from the chip in a time-multiplexed fashion. In addition, DPR improves fault tolerance against transient errors and permanent damage, such as Single Event Upsets (SEUs) can be mitigated by reconfiguring the FPGA to avoid error accumulation. Furthermore, power and heat can be reduced by removing finished or idle tasks from the chip. For all these reasons above, DPR has significantly promoted Reconfigurable Computing (RC) and has become a very hot topic. However, since hardware integration is increasing at an exponential rate, and applications are becoming more complex with the growth of user demands, highlevel application design and low-level hardware implementation are increasingly separated and layered. As a consequence, users can obtain little advantage from DPR without the support of system-level middleware. To bridge the gap between the high-level application and the low-level hardware implementation, this thesis presents the important contributions towards a Reliable, Reconfigurable and Real-Time Operating System (R3TOS), which facilitates the user exploitation of DPR from the application level, by managing the complex hardware in the background. In R3TOS, hardware tasks behave just like software tasks, which can be created, scheduled, and mapped to different computing resources on the fly. The novel contributions of this work are: 1) a novel implementation of an efficient task scheduler and allocator; 2) implementation of a novel real-time scheduling algorithm (FAEDF) and two efficacious allocating algorithms (EAC and EVC), which schedule tasks in real-time and circumvent emerging faults while maintaining more compact empty areas. 3) Design and implementation of a faulttolerant microprocessor by harnessing the existing FPGA resources, such as Error Correction Code (ECC) and configuration primitives. 4) A novel symmetric multiprocessing (SMP)-based architectures that supports shared memory programing interface. 5) Two demonstrations of the integrated system, including a) the K-Nearest Neighbour classifier, which is a non-parametric classification algorithm widely used in various fields of data mining; and b) pairwise sequence alignment, namely the Smith Waterman algorithm, used for identifying similarities between two biological sequences. R3TOS gives considerably higher flexibility to support scalable multi-user, multitasking applications, whereby resources can be dynamically managed in respect of user requirements and hardware availability. Benefiting from this, not only the hardware resources can be more efficiently used, but also the system performance can be significantly increased. Results show that the scheduling and allocating efficiencies have been improved up to 2x, and the overall system performance is further improved by ~2.5x. Future work includes the development of Network on Chip (NoC), which is expected to further increase the communication throughput; as well as the standardization and automation of our system design, which will be carried out in line with the enablement of other high-level synthesis tools, to allow application developers to benefit from the system in a more efficient manner.
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Yankov, Y. Daniel. "Discrete event system modeling of demand responsive transportation systems operating in real time." [Tampa, Fla] : University of South Florida, 2008. http://purl.fcla.edu/usf/dc/et/SFE0002466.
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Yankov, Daniel Y. "Discrete Event System Modeling Of Demand Responsive Transportation Systems Operating In Real Time." Scholar Commons, 2008. https://scholarcommons.usf.edu/etd/575.
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Demand responsive transportation is a variable route service of passengers or freight from specific origin(s) to destination(s) in response to the request of users. Operational planning of DRT system encompasses the methods to provide efficient service to the passengers and to the system operators. These methods cover the assignments of vehicles to transportation requests and vehicle routings under various constraints such as environmental conditions, traffic and service limitations. Advances in the information and communication technologies, such as the Internet, mobile communication devices, GIS, GPS, Intelligent Transportation Systems have led to a significantly complex and highly dynamical decision making environment. Recent approaches to DRT operational planning are based on "closed information loop" to achieve a higher level of automation, increased flexibility and efficiency.
Intelligent and effective use of the available information in such a complex decision making environment requires the application of formal modeling and control approaches, which are robust, modular and computationally efficient. In this study, DRT systems are modeled as Discrete Event Systems using Finite Automata formalism and DRT real time control is addressed using Supervisory Control Theory. Two application scenarios are considered; the first is based on air-charter service and illustrates uncontrolled system model and operational specification synthesis. The automatic synthesis of centralized and modular supervisors is demonstrated. The second scenario is a mission critical application based on emergency evacuation problem. Decentralized supervisory control architecture suitable for accommodating the real-time contingencies is presented.
Conditions for parallel computation of local supervisors are specified and the computational advantages of alternative supervisory control architectures are discussed. Discrete event system modeling and supervisory control theory are well established and powerful mathematical tools. In this dissertation, they are shown to be suitable for expressing the modeling and control requirements of complex and dynamic applications in DRT. The modeling and control approaches described herein, coupled with the mature body of research literature in Discrete Event Systems and Supervisory Control Theory, facilitate logical analysis of these complex systems and provide the necessary framework for development of intelligent decision making tools for real time operational planning and control in a broad range of DRT applications.
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Baldovin, Andrea <1983>. "Operating System Contribution to Composable Timing Behaviour in High-Integrity Real-Time Systems." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2014. http://amsdottorato.unibo.it/6597/1/Baldovin_Andrea_tesi.pdf.
Full textAbstract:
The development of High-Integrity Real-Time Systems has a high footprint in terms of human, material and schedule costs. Factoring functional, reusable logic in the application favors incremental development and contains costs. Yet, achieving incrementality in the timing behavior is a much harder problem. Complex features at all levels of the execution stack, aimed to boost average-case performance, exhibit timing behavior highly dependent on execution history, which wrecks time composability and incrementaility with it.
Our goal here is to restitute time composability to the execution stack, working bottom up across it. We first characterize time composability without making assumptions on the system architecture or the software deployment to it. Later, we focus on the role played by the real-time operating system in our pursuit. Initially we consider single-core processors and, becoming less permissive on the admissible hardware features, we devise solutions that restore a convincing degree of time composability.
To show what can be done for real, we developed TiCOS, an ARINC-compliant kernel, and re-designed ORK+, a kernel for Ada Ravenscar runtimes. In that work, we added support for limited-preemption to ORK+, an absolute premiere in the landscape of real-word kernels. Our implementation allows resource sharing to co-exist with limited-preemptive scheduling, which extends state of the art.
We then turn our attention to multicore architectures, first considering partitioned systems, for which we achieve results close to those obtained for single-core processors. Subsequently, we shy away from the over-provision of those systems and consider less restrictive uses of homogeneous multiprocessors, where the scheduling algorithm is key to high schedulable utilization. To that end we single out RUN, a promising baseline, and extend it to SPRINT, which supports sporadic task sets, hence matches real-world industrial needs better.
To corroborate our results we present findings from real-world case studies from avionic industry.
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Baldovin, Andrea <1983>. "Operating System Contribution to Composable Timing Behaviour in High-Integrity Real-Time Systems." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2014. http://amsdottorato.unibo.it/6597/.
Full textAbstract:
The development of High-Integrity Real-Time Systems has a high footprint in terms of human, material and schedule costs. Factoring functional, reusable logic in the application favors incremental development and contains costs. Yet, achieving incrementality in the timing behavior is a much harder problem. Complex features at all levels of the execution stack, aimed to boost average-case performance, exhibit timing behavior highly dependent on execution history, which wrecks time composability and incrementaility with it.
Our goal here is to restitute time composability to the execution stack, working bottom up across it. We first characterize time composability without making assumptions on the system architecture or the software deployment to it. Later, we focus on the role played by the real-time operating system in our pursuit. Initially we consider single-core processors and, becoming less permissive on the admissible hardware features, we devise solutions that restore a convincing degree of time composability.
To show what can be done for real, we developed TiCOS, an ARINC-compliant kernel, and re-designed ORK+, a kernel for Ada Ravenscar runtimes. In that work, we added support for limited-preemption to ORK+, an absolute premiere in the landscape of real-word kernels. Our implementation allows resource sharing to co-exist with limited-preemptive scheduling, which extends state of the art.
We then turn our attention to multicore architectures, first considering partitioned systems, for which we achieve results close to those obtained for single-core processors. Subsequently, we shy away from the over-provision of those systems and consider less restrictive uses of homogeneous multiprocessors, where the scheduling algorithm is key to high schedulable utilization. To that end we single out RUN, a promising baseline, and extend it to SPRINT, which supports sporadic task sets, hence matches real-world industrial needs better.
To corroborate our results we present findings from real-world case studies from avionic industry.