Relevant bibliographies by topics / Run-time reconfigurable hardware

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Run-time reconfigurable hardware'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Run-time reconfigurable hardware"

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Fons, M., F. Fons, and E. Canto. "Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware." IEEE Transactions on Circuits and Systems II: Express Briefs 57, no. 12 (December 2010): 991–95. http://dx.doi.org/10.1109/tcsii.2010.2087970.

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Uchevler, Bahram N., and Kjetil Svarstad. "Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions." International Journal of Reconfigurable Computing 2018 (July 10, 2018): 1–25. http://dx.doi.org/10.1155/2018/3276159.

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With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform.
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Edwards, Martyn, and Peter Green. "Run-time support for dynamically reconfigurable computing systems." Journal of Systems Architecture 49, no. 4-6 (September 2003): 267–81. http://dx.doi.org/10.1016/s1383-7621(03)00068-7.

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Clemente, Juan Antonio, Javier Resano, Carlos Gonzalez, and Daniel Mozos. "A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 7 (July 2011): 1263–76. http://dx.doi.org/10.1109/tvlsi.2010.2050158.

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Al-Wattar, A., S. Areibi, and G. Grewal. "An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems." International Journal of Reconfigurable Computing 2016 (2016): 1–24. http://dx.doi.org/10.1155/2016/9012909.

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Several embedded application domains for reconfigurable systems tend to combine frequent changes with high performance demands of their workloads such as image processing, wearable computing, and network processors. Time multiplexing of reconfigurable hardware resources raises a number of new issues, ranging from run-time systems to complex programming models that usually form a reconfigurable operating system (ROS). In this paper, an efficient ROS framework that aids the designer from the early design stages all the way to the actual hardware implementation is proposed and implemented. An efficient reconfigurable platform is implemented along with novel placement/scheduling algorithms. The proposed algorithms tend to reuse hardware tasks to reduce reconfiguration overhead, migrate tasks between software and hardware to efficiently utilize resources, and reduce computation time. A supporting framework for efficient mapping of execution units to task graphs in a run-time reconfigurable system is also designed. The framework utilizes an Island Based Genetic Algorithm flow that optimizes several objectives including performance, area, and power consumption. The proposed Island Based GA framework achieves on average 55.2% improvement over a single-GA implementation and an 80.7% improvement over a baseline random allocation and binding approach.
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Silva, M. L., and J. C. Ferreira. "Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems." IET Computers & Digital Techniques 1, no. 5 (2007): 461. http://dx.doi.org/10.1049/iet-cdt:20060056.

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Fons, Francisco, Mariano Fons, Enrique Cantó, and Mariano López. "Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications." Journal of Signal Processing Systems 66, no. 2 (August 10, 2011): 191–221. http://dx.doi.org/10.1007/s11265-011-0607-9.

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NAYLOR, MATTHEW, and COLIN RUNCIMAN. "The Reduceron reconfigured and re-evaluated." Journal of Functional Programming 22, no. 4-5 (July 10, 2012): 574–613. http://dx.doi.org/10.1017/s0956796812000214.

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AbstractA new version of a special-purpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.
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Shirazi, N., W. Luk, and P. Y. K. Cheung. "Framework and tools for run-time reconfigurable designs." IEE Proceedings - Computers and Digital Techniques 147, no. 3 (2000): 147. http://dx.doi.org/10.1049/ip-cdt:20000486.

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Chun, Pil Woo, and Lev Kirischian. "Architecture synthesis methodology for cost-effective run-time reconfigurable systems." International Journal of Embedded Systems 4, no. 3/4 (2010): 225. http://dx.doi.org/10.1504/ijes.2010.039026.

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Dissertations / Theses on the topic "Run-time reconfigurable hardware"

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Fons, Lluís Francisco. "Embedded electronic systems driven by run-time reconfigurable hardware." Doctoral thesis, Universitat Rovira i Virgili, 2012. http://hdl.handle.net/10803/83494.

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Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.
Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.
Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria.
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Carline, Dylan Thomas Frederick. "The control of hardware for run-time reconfigurable computing environments." Thesis, Lancaster University, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.422969.

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Puttegowda, Kiran. "Context Switching Strategies in a Run-Time Reconfigurable system." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/32043.

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A distinctive feature of run-time reconfigurable systems is the ability to change the configuration of programmable resources during execution. This opens a number of possibilities such as virtualisation of computational resources, simplified routing and in certain applications lower power. Seamless run-time reconfiguration requires rapid configuration. Commodity programmable devices have relatively long configuration time, which makes them poor candidates for run-time reconfigurable systems. Reducing this reconfiguration time to the order of nano seconds will enable rapid run-time reconfiguration. Having multiple configuration planes and switching between them while processing data is one approach towards achieving rapid reconfiguration. An experimental context switching programmable device, called the Context Switching Reconfigurable Computer (CSRC), has been created by BAE Systems, which provided opportunities to explore context-switching strategies for run-time reconfigurable systems. The work presented here studies this approach for run-time reconfiguration, by applying the concepts to develop applications on a context switching reconfigurable system. The work also discusses the advantages and disadvantages of such an approach and ways of leveraging the concept for efficient computing.
Master of Science
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Fazzoletto, Emilio. "Characterization of Partial and Run-Time Reconfigurable FPGAs." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-202724.

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FPGA based systems have been heavily used to prototype and test Application Specic Integrated Circuit (ASIC) designs with much lower costs and development time compared to hardwired prototypes. In recentyears, thanks to both the latest technology nodes and a change in the architecture of reconfigurable integrated circuits (from traditional Complex Programmable Logic Device (CPLD) to full-CMOS FPGA), FPGAs have become more popular in embedded systems, both as main computation resources and as hardware accelerators. A new era is beginning for FPGA based systems: the partial run-time reconguration of a FPGA is a feature now available in products already on the market and hardware designers and software developers have to exploit this capability. Previous works show that, when designed properly, a system can improve both its power efficiency and its performance taking advantage of a partial run-time reconfigurable architecture. Unfortunately, taking advantage of run-time reconfigurable hardware is very challenging and there are several problems to face: the reconfiguration overhead is not negligible compared to nowadays CPUs performance,the reconfiguration time is not easily predictable, and the software has to be re-though to work with a time-evolving platform. This thesis project aims to investigate the performance of a modern run-time reconfigurable SoC (a Xilinx Zynq 7020), focusing on the reconfiguration overhead and its predictability, on the achievable speedup, and the trade-off and limits of this kind of platform. Since it is not always obvious when an application (especially a real-time one) is really able to use at its own advantage a partial run-time reconfigurable platform, the data collected during this project could be a valid help for hardware designers that use reconfigurable computing.
FPGA-baserade system har tidigare främst använts för snabb och kostnadseffektiv konstruktion av prototyper vid framtagandet av applikationsspecika integrerade kretsar (ASIC). På senare år har användandet av FPGA:er i inbyggda system för implementation av hårdvaruacceleratorers såväl som huvudsaklig beräkningsenhet ökat. Denna ökning har möjliggjorts mycket tack vare den utveckling som har skett av rekonfigurerbara integrerade kretsar: från de mer traditionella Complex Programmable Logic Devices (CPLD) till helt CMOS-baserade FPGA:er. Nu inleds en ny era för FPGA-baserade system tack vare möjligheten att under körning rekonfigurera delar av FPGA:n genom så kallad partial run-time reconguration(RTR) - en teknik som redan idag finns tillgänglig i produkter på marknaden. Tidigare forskning visar att användandet av en RTR-baserad hårdvaruarkitektur kan ha en positiv effekt med avseende på prestanda såväl som strömförbrukning. Att använda RTR-baserad hårdvara innebär dock flera utmaningar: En ej försumbar rekonfigurationstid måste tas i beaktning, så även den icke-deterministiska exekveringstiden som en rekonfiguration kan innebära. Vidare måste anpassningar av mjukvaran göras för att fungera med en hårdvaruplattform som förändras över tid. Denna uppsats syftar till att undersöka prestandan hos ett modernt RTRbaserat SoC (Xilinx Zynq 7020) med fokus på rekonfigurationstider och dess förutsägbarhet, prestanda ökning, begränsningar samt nödvändiga kompromisser som denna arkitektur innebär. Huruvida en applikation kan dra nytta av en RTR-baserad arkitektur eller inte kan vara svårt att avgöra. Den insamlade datan som presenteras i denna rapport kan dock fungera som stöd för hårdvarukonstruktörer som önskar använda en RTR-baserad plattform.
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Blumer, Aric David. "Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration." Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/29380.

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The run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new avenues to hardware reuse. Through the use of process migration between hardware and software, an FPGA provides a parallel execution cache. Busy processes can be migrated into hardware-based, parallel processors, and idle processes can be migrated out increasing the utilization of the hardware. The application of hardware/software process migration to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that executing processes tend to be executed again. This property is termed executive temporal locality, and it can be exploited by migration systems to accelerate RTL simulation. In this dissertation, process migration is first formally modeled using Finite State Machines (FSMs). Upon FSMs are built programs, processes, migration realms, and the migration of process state within a realm. From this model, a taxonomy of migration realms is developed. Second, process migration is applied to the RTL simulation of digital circuits. The canonical form of an RTL process is defined, and transformations of HDL code are justified and demonstrated. These transformations allow a simulator to identify basic active units within the simulation and combine them to balance the load across a set of processors. Through the use of input monitors, executive locality of reference is identified and demonstrated on a set of six RTL designs. Finally, the implementation of a migration system is described which utilizes Virtual Machines (VMs) and Real Machines (RMs) in existing FPGAs. Empirical and algorithmic models are developed from the data collected from the implementation to evaluate the effect of optimizations and migration algorithms.
Ph. D.
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Su, Hong-Yi, and 蘇弘毅. "Run-Time Reconfigurable Hardware Platform Design for Multimedia Applications." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/51805335613040622909.

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碩士
國立成功大學
電機工程學系碩博士班
93
Due to the pressure of TTM and expensive mask cost, IC designers are forced to shorten design process time and try their best to increase the reusability of IPs. The reconfigurable architecture provides extremely advantages such as reducing the cost, time and complexity of design, and diminishing the difficulties for the integration on IP components. Here, for fast multimedia processing we presented a high performance on-line reconfigurable hardware platform. With it, the hardware designers can easily and efficiently design different multimedia applications into hardware, and then, easy reusing and modifications. We have verified the platform by mapping many multimedia applications into the platform, and experimental results show that the average speed up ratio is 8.29 compared with the software-only design approach.
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Paulino, Nuno Miguel Cardanha. "Generation of Custom Run-Time Reconfigurable Hardware for Transparent Binary Acceleration." Tese, 2016. https://repositorio-aberto.up.pt/handle/10216/83952.

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Paulino, Nuno Miguel Cardanha. "Generation of Custom Run-Time Reconfigurable Hardware for Transparent Binary Acceleration." Doctoral thesis, 2016. https://repositorio-aberto.up.pt/handle/10216/83952.

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Alle, Mythri. "Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm." Thesis, 2012. http://etd.iisc.ernet.in/handle/2005/2453.

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Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using a network and this interconnection of computation elements is referred to as a reconfigurable fabric. The size of application that can be accommodated on the reconfigurable fabric is limited by the size of instruction buffers associated with each Compute element. When an application cannot be accommodated entirely, application is partitioned such that each of these partitions can be executed on the reconfigurable fabric. These partitions are scheduled by an orchestrator. The orchestrator employs dynamic dataflow execution paradigm. Dynamic dataflow execution paradigm has inherent support for synchronization and helps in exploitation of parallelism that exists across application partitions. In this thesis, we present a compiler that targets such CGRAs. The compiler presented in this thesis is capable of accepting applications specified in C89 standard. To enable architectural design space exploration, the compiler is designed such that it can be customized for several instances of CGRAs employing dataflow execution paradigm at the orchestrator. This can be achieved by specifying the appropriate configuration parameters to the compiler. The focus of this thesis is to provide efficient support for various kinds of parallelism while ensuring correctness. The compiler is designed to support fine-grained task level parallelism that exists across iterations of loops and function calls. Additionally, compiler can also support pipeline parallelism, where a loop is split into multiple stages that execute in a pipelined manner. The prototype compiler, which targets multiple instances of a CGRA, is demonstrated in this thesis. We used this compiler to target multiple variants of CGRAs employing dataflow execution paradigm. We varied the reconfigur-able fabric, orchestration mechanism employed, size of instruction buffers. We also choose applications from two different domains viz. cryptography and linear algebra. The execution time of the CGRA (the best among all instances) is compared against an Intel Quad core processor. Cryptography applications show a performance improvement ranging from more than one order of magnitude to close to two orders of magnitude. These applications have large amounts of ILP and our compiler could successfully expose the ILP available in these applications. Further, the domain customization also played an important role in achieving good performance. We employed two custom functional units for accelerating Cryptography applications and compiler could efficiently use them. In linear algebra kernels we observe multiple iterations of the loop executing in parallel, effectively exploiting loop-level parallelism at runtime. Inspite of this we notice close to an order of magnitude performance degradation. The reason for this degradation can be attributed to the use of non-pipelined floating point units, and the delays involved in accessing memory. Pipeline parallelism was demonstrated using this compiler for FFT and QR factorization. Thus, the compiler is capable of efficiently supporting different kinds of parallelism and can support complete C89 standard. Further, the compiler can also support different instances of CGRAs employing dataflow execution paradigm.
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Book chapters on the topic "Run-time reconfigurable hardware"

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Wold, Alexander, Andreas Agne, and Jim Torresen. "Relocatable Hardware Threads in Run-Time Reconfigurable Systems." In Lecture Notes in Computer Science, 61–72. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-05960-0_6.

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Wang, Gang, Du Chen, Jian Chen, Jianliang Ma, and Tianzhou Chen. "A Performance Model for Run-Time Reconfigurable Hardware Accelerator." In Lecture Notes in Computer Science, 54–66. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03644-6_5.

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Osborne, W. G., W. Luk, J. G. F. Coutinho, and O. Mencer. "Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation." In Lecture Notes in Computer Science, 354–69. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24568-8_18.

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Götz, Marcelo, Achim Rettberg, and Carlos Eduardo Pereira. "A Run-Time Partitioning Algorithm for RTOS on Reconfigurable Hardware." In Embedded and Ubiquitous Computing – EUC 2005, 469–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11596356_48.

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Knieper, Tobias, Paul Kaufmann, Kyrre Glette, Marco Platzner, and Jim Torresen. "Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture." In Evolvable Systems: From Biology to Hardware, 250–61. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-15323-5_22.

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Islam, Mahfuzul, and Hidetoshi Onodera. "Monitor Circuits for Cross-Layer Resiliency." In Dependable Embedded Systems, 385–407. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_16.

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AbstractCross-layer resiliency has become a critical deciding factor for any successful product. This chapter focuses on monitor circuits that are essential in realizing the cross-layer resiliency. The role of monitor circuits is to establish a bridge between the hardware and other layers by providing information about the devices and the operating environment in run-time. This chapter explores delay-based monitor circuits for design automation with the existing cell-based design methodology. The chapter discusses several design techniques to monitor parameters of threshold voltage, temperature, leakage current, critical delay, and aging. The chapter then demonstrates a reconfigurable architecture to monitor multiple parameters with small area footprint. Finally, an extraction methodology of physical parameters is discussed for model-hardware correlation. Utilizing the cell-based design flow, delay-based monitors can be placed inside the target digital circuit and thus a better correlation between monitor and target circuit behavior can be realized.
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George, Laurent, and Pierre Courbin. "Reconfiguration of Uniprocessor Sporadic Real-Time Systems." In Reconfigurable Embedded Control Systems, 167–89. IGI Global, 2011. http://dx.doi.org/10.4018/978-1-60960-086-0.ch007.

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In this chapter the authors focus on the problem of reconfiguring embedded real-time systems. Such reconfiguration can be decided either off-line to determine if a given application can be run on a different platform, while preserving the timeliness constraints imposed by the application, or on-line, where a reconfiguration should be done to adapt the system to the context of execution or to handle hardware or software faults. The task model considered in this chapter is the classical sporadic task model defined by a Worst Case Execution Time (WCET), a minimum inter-arrival time (also denoted the minimum Period) and a late termination deadline. The authors consider two preemptive scheduling strategies: Fixed Priority highest priority first (FP) and Earliest Deadline First (EDF). They propose a sensitivity analysis to handle reconfiguration issues. Sensitivity analysis aims at determining acceptable deviations from the specifications of a problem due to evolutions in system characteristics (reconfiguration or performance tuning). They present a state of the art for sensitivity analysis in the case of WCETs, Periods and Deadlines reconfigurations and study to what extent sensitivity analysis can be used to decide on the possibility of reconfiguring a system.
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Gazzano, Julio Daniel Dondo, Fernando Rincon Calle, Julian Caba, David de la Fuente, and Jesus Barba Romero. "Dynamic Reconfiguration for Internal Monitoring Services." In Field-Programmable Gate Array (FPGA) Technologies for High Performance Instrumentation, 124–36. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-5225-0299-9.ch006.

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In hardware design flow, testing is the most important step to hardware quality assurance before a hardware component is released. However simulation and verification during design steps are not enough to guarantee a system without failures. In many cases the system fails after have been deployed. Dynamically reconfigurable FPGAs have the ability to reconfigure part of its architecture during run time without stopping the whole system. This feature is an added value that can be exploited for internal system monitoring and verification. Using partial reconfiguration, an Internal Monitoring System can be implemented in reconfigurable areas for monitoring different conditions and signals in the circuit, after implementation. This allows detecting and identifying those failures that were not possible to detect during simulation process.
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Ahmad, Balal, Ali Ahmadinia, and Tughrul Arslan. "Dynamically Reconfigurable NoC for Future Heterogeneous Multi-core Architectures." In Dynamic Reconfigurable Network-on-Chip Design, 256–76. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-61520-807-4.ch010.

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To increase the efficiency of NoCs and to efficiently utilize the available hardware resources, a novel dynamically reconfigurable NoC (drNoC) is proposed in this chapter. Exploiting the notion of hardware reconfigurability, the proposed drNoC reconfigures itself in terms of switching, routing and packet size with the changing communication requirements of the system at run time, thus utilizing the maximum available channel bandwidth. In order to increase the applicability of drNoC, the network interface is designed to support OCP socket standard. This makes drNoC a highly re-useable communication framework, qualifying it as a communication centric platform for high data intensive SoC architectures. Simulation results show a 32% increase in data throughput and 22-35% decrease in network delay when compared with a traditional NoC with fixed parameters.
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Lin, Wei-Wen, Jih-Sheng Shen, and Pao-Ann Hsiung. "An Efficient Hardware/Software Communication Mechanism for Reconfigurable NoC." In Dynamic Reconfigurable Network-on-Chip Design, 84–109. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-61520-807-4.ch004.

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With the progress of technology, more and more intellectual properties (IPs) can be integrated into one single chip. The performance bottleneck has shifted from the computation in individual IPs to the communication among IPs. A Network-on-Chip (NoC) was proposed to provide high scalability and parallel communication. An ASIC-implemented NoC lacks flexibility and has a high non-recurring engineering (NRE) cost. As an alternative, we can implement an NoC in a Field Programmable Gate Arrays (FPGA). In addition, FPGA devices can support dynamic partial reconfiguration such that the hardware circuits can be configured into an FPGA at run time when necessary, without interfering hardware circuits that are already running. Such an FPGA-based NoC, namely reconfigurable NoC (RNoC), is more flexible and the NRE cost of FPGA-based NoC is also much lower than that of an ASIC-based NoC. Because of dynamic partial reconfiguration, there are several issues in the RNoC design. We focus on how communication between hardware and software can be made efficient for RNoC. We implement three communication architectures for RNoC namely single output FIFO-based architecture, multiple output FIFO-based architecture, and shared memory-based architecture. The average communication memory overhead is less on the single output FIFO-based architecture and the shared memory-based architecture than on the multiple output FIFO-based architecture when the lifetime interval is smaller than 0.5. In the performance analysis, some real applications are applied. Real application examples show that performance of the multiple output FIFO-based architecture is more efficient by as much as 1.789 times than the performance of the single output FIFO-based architecture. The performance of the shared memory-based architecture is more efficient by as much as 1.748 times than the performance of the single output FIFO-based architecture.
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Conference papers on the topic "Run-time reconfigurable hardware"

1

Turner, R. "A virtual hardware handler for run-time reconfiguration systems." In IEE Colloquium Reconfigurable Systems. IEE, 1999. http://dx.doi.org/10.1049/ic:19990352.

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Derbyshire, Arran, Tobias Becker, and Wayne Luk. "Incremental elaboration for run-time reconfigurable hardware designs." In the 2006 international conference. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1176760.1176773.

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Davidson, Tom, Karel Bruneel, and Dirk Stroobandt. "Run-Time Reconfiguration for Automatic Hardware/Software Partitioning." In 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010). IEEE, 2010. http://dx.doi.org/10.1109/reconfig.2010.57.

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Khuat, Quang-Hai, Daniel Chillet, and Michael Hubner. "Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC." In 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2014. http://dx.doi.org/10.1109/reconfig.2014.7032512.

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Jeong, Byungil, Sungjoo Yoo, Sunghyun Lee, and Kiyoung Choi. "Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs." In the 2000 conference. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/368434.368598.

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Hagemeyer, Jens, Arne Hilgenstein, Dirk Jungewelter, Dario Cozzi, Carmelo Felicetti, Ulrich Rueckert, Sebastian Korf, et al. "A scalable platform for run-time reconfigurable satellite payload processing." In 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE, 2012. http://dx.doi.org/10.1109/ahs.2012.6268642.

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Villalobos, Ricardo, Rami Abielmona, and Voicu Groza. "A Bridging Layer for Run-Time Reconfigurable Hardware Operating Systems." In 2008 IEEE Instrumentation and Measurement Technology Conference - I2MTC 2008. IEEE, 2008. http://dx.doi.org/10.1109/imtc.2008.4547112.

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Beckert, R., T. Fuchs, St Ruelke, and W. Hardt. "A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator." In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). IEEE, 2007. http://dx.doi.org/10.1109/dsd.2007.4341462.

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Kosciuszkiewicz, Krzysztof, Fearghal Morgan, and Krzysztof Kepa. "Run-Time Management of Reconfigurable Hardware Tasks Using Embedded Linux." In 2007 International Conference on Field-Programmable Technology. IEEE, 2007. http://dx.doi.org/10.1109/fpt.2007.4439251.

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Agwa, Shady O., Hany H. Ahmad, and Awad I. Saleh. "Hardware Pessimistic Run-Time Profiling for a Self-Reconfigurable Embedded Processor Architecture." In 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010). IEEE, 2010. http://dx.doi.org/10.1109/reconfig.2010.12.

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