Journal articles: 'Run-time reconfigurable hardware'

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Fons, M., F. Fons, and E. Canto. "Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware." IEEE Transactions on Circuits and Systems II: Express Briefs 57, no. 12 (December 2010): 991–95. http://dx.doi.org/10.1109/tcsii.2010.2087970.

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Uchevler, Bahram N., and Kjetil Svarstad. "Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions." International Journal of Reconfigurable Computing 2018 (July 10, 2018): 1–25. http://dx.doi.org/10.1155/2018/3276159.

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With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform.

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Edwards, Martyn, and Peter Green. "Run-time support for dynamically reconfigurable computing systems." Journal of Systems Architecture 49, no. 4-6 (September 2003): 267–81. http://dx.doi.org/10.1016/s1383-7621(03)00068-7.

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Clemente, Juan Antonio, Javier Resano, Carlos Gonzalez, and Daniel Mozos. "A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 7 (July 2011): 1263–76. http://dx.doi.org/10.1109/tvlsi.2010.2050158.

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Al-Wattar, A., S. Areibi, and G. Grewal. "An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems." International Journal of Reconfigurable Computing 2016 (2016): 1–24. http://dx.doi.org/10.1155/2016/9012909.

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Several embedded application domains for reconfigurable systems tend to combine frequent changes with high performance demands of their workloads such as image processing, wearable computing, and network processors. Time multiplexing of reconfigurable hardware resources raises a number of new issues, ranging from run-time systems to complex programming models that usually form a reconfigurable operating system (ROS). In this paper, an efficient ROS framework that aids the designer from the early design stages all the way to the actual hardware implementation is proposed and implemented. An efficient reconfigurable platform is implemented along with novel placement/scheduling algorithms. The proposed algorithms tend to reuse hardware tasks to reduce reconfiguration overhead, migrate tasks between software and hardware to efficiently utilize resources, and reduce computation time. A supporting framework for efficient mapping of execution units to task graphs in a run-time reconfigurable system is also designed. The framework utilizes an Island Based Genetic Algorithm flow that optimizes several objectives including performance, area, and power consumption. The proposed Island Based GA framework achieves on average 55.2% improvement over a single-GA implementation and an 80.7% improvement over a baseline random allocation and binding approach.

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Silva, M. L., and J. C. Ferreira. "Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems." IET Computers & Digital Techniques 1, no. 5 (2007): 461. http://dx.doi.org/10.1049/iet-cdt:20060056.

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Fons, Francisco, Mariano Fons, Enrique Cantó, and Mariano López. "Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications." Journal of Signal Processing Systems 66, no. 2 (August 10, 2011): 191–221. http://dx.doi.org/10.1007/s11265-011-0607-9.

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NAYLOR, MATTHEW, and COLIN RUNCIMAN. "The Reduceron reconfigured and re-evaluated." Journal of Functional Programming 22, no. 4-5 (July 10, 2012): 574–613. http://dx.doi.org/10.1017/s0956796812000214.

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AbstractA new version of a special-purpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.

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Shirazi, N., W. Luk, and P. Y. K. Cheung. "Framework and tools for run-time reconfigurable designs." IEE Proceedings - Computers and Digital Techniques 147, no. 3 (2000): 147. http://dx.doi.org/10.1049/ip-cdt:20000486.

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Chun, Pil Woo, and Lev Kirischian. "Architecture synthesis methodology for cost-effective run-time reconfigurable systems." International Journal of Embedded Systems 4, no. 3/4 (2010): 225. http://dx.doi.org/10.1504/ijes.2010.039026.

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Yoon, Iljung, Heewon Joung, and Jooheung Lee. "Zynq-Based Reconfigurable System for Real-Time Edge Detection of Noisy Video Sequences." Journal of Sensors 2016 (2016): 1–9. http://dx.doi.org/10.1155/2016/2654059.

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We implement Zynq-based self-reconfigurable system to perform real-time edge detection of 1080p video sequences. While object edge detection is a fundamental tool in computer vision, noises in the video frames negatively affect edge detection results significantly. Moreover, due to the high computational complexity of 1080p video filtering operations, hardware implementation on reconfigurable hardware fabric is necessary. Here, the proposed embedded system utilizes dynamic reconfiguration capability of Zynq SoC so that partial reconfiguration of different filter bitstreams is performed during run-time according to the detected noise density level in the incoming video frames. Pratt’s Figure of Merit (PFOM) to evaluate the accuracy of edge detection is analyzed for various noise density levels, and we demonstrate that adaptive run-time reconfiguration of the proposed filter bitstreams significantly increases the accuracy of edge detection results while efficiently providing computing power to support real-time processing of 1080p video frames. Performance results on configuration time, CPU usage, and hardware resource utilization are also compared.

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BELAID, IKBEL, BASSEM OUNI, FABRICE MULLER, and MAHER BENJEMAA. "COMPLETE AND APPROXIMATE METHODS FOR OFF-LINE PLACEMENT OF HARDWARE TASKS ON RECONFIGURABLE DEVICES." Journal of Circuits, Systems and Computers 22, no. 02 (February 2013): 1250080. http://dx.doi.org/10.1142/s0218126612500806.

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With the advent of run-time partial reconfiguration, the most recent reconfigurable devices support reconfiguring hardware tasks individually, without interrupting the remaining tasks running on the same device. While the concept of run-time partial reconfiguration increases performance and resource utilization, it also leads to resource wastage, high configuration overhead and complex allocation situations of hardware tasks on reconfigurable devices. Many on-line and off-line methods for hardware task placement have been proposed for such reconfigurable devices to enhance placement quality expressed by fragmentation rate, the amount of task rejection and a few of them also estimate configuration overhead. However, these works treat each criterion individually and therefore do not reflect the overall metrics of placement quality. Hardware task placement is a multi-objective combinatory optimization problem. In this paper, we investigate the problem of off-line placement of hardware tasks in partially reconfigurable devices and we present a new three-level resource management that is based on two methods, i.e., a complete analytic method: the formulation into mixed integer programming, and an approximate iterative method: the Bees algorithm. For both methods, the placement quality is measured by the rate of resource efficiency and by the amount of configuration overhead. Experiments demonstrate that the analytic method provides better resource efficiency than the Bees Algorithm by 33% and attains 15% of gain in configuration overhead.

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Marescaux, T., V. Nollet, J. Y. Mignolet, A. Bartic, W. Moffat, P. Avasare, P. Coene, D. Verkest, S. Vernalde, and R. Lauwereins. "Run-time support for heterogeneous multitasking on reconfigurable SoCs." Integration 38, no. 1 (October 2004): 107–30. http://dx.doi.org/10.1016/j.vlsi.2004.03.002.

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Al-Wattar, Ahmed, Shawki Areibi, and Gary Grewal. "An Efficient Framework for Floor-plan Prediction of Dynamic Runtime Reconfigurable Systems." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 2 (July 1, 2015): 99. http://dx.doi.org/10.11591/ijres.v4.i2.pp99-121.

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Several embedded application domains for reconfigurable systems tend to combine frequent changes with high performance demands of their workloads such as image processing, wearable computing and network processors. Time multiplexing of reconfigurable hardware resources raises a number of new issues, ranging from run-time systems to complex programming models that usually form a Reconfigurable hardware Operating System (ROS). The Operating System performs online task scheduling and handles resource management. There are many challenges in adaptive computing and dynamic reconfigurable systems. One of the major understudied challenges is estimating the required resources in terms of soft cores, Programmable Reconfigurable Regions (PRRs), the appropriate communication infrastructure, and to predict a near optimal layout and floor-plan of the reconfigurable logic fabric. Some of these issues are specific to the application being designed, while others are more general and relate to the underlying run-time environment. Static resource allocation for Run-Time Reconfiguration (RTR) often leads to inferior and unacceptable results. In this paper, we present a novel adaptive and dynamic methodology, based on a Machine Learning approach, for predicting and estimating the necessary resources for an application based on past historical information. An important feature of the proposed methodology is that the system is able to learn and generalize and, therefore, is expected to improve its accuracy over time. The goal of the entire process is to extract useful hidden knowledge from the data. This knowledge is the prediction and estimation of the necessary resources for an unknown or not previously seen application.

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Le, Shu Ping, Zhi Wen Xiong, and Hong Zeng. "Design and Implement of the Reconfigurable Algorithm Based on uC/OS-II." Applied Mechanics and Materials 198-199 (September 2012): 1372–77. http://dx.doi.org/10.4028/www.scientific.net/amm.198-199.1372.

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More and more applications need The ability to customize the architecture to match the computation and the data flow of the application, so increasingly new system implementations based on reconfigurable computing are being considered. Reconfigurable computing has potential to accelerate a wide variety of applications; its main feature is the ability to perform computations in hardware to improve performance, while retaining the flexibility of software solutions. An operating system (OS) for reconfigurable computing uses new versions of algorithms for the scheduling, the operating system must decide how to allocate the hardware at run-time based on the status of the system. This paper discusses the scheduling algorithm for reconfigurable computing platform, covers two aspects of reconfigurable computing: architectures and design methods. The tasks are divided into two categories in this survey, consider the issues involved in reusing the configurable hardware during program execution. And improve μC/OS-II to manage the use of reconfigurable resources, responsible for task scheduling, helping the programmer to concentrate more on application development.

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Dorta, Taho, Jaime Jiménez, José Luis Martín, Unai Bidarte, and Armando Astarloa. "Reconfigurable Multiprocessor Systems: A Review." International Journal of Reconfigurable Computing 2010 (2010): 1–10. http://dx.doi.org/10.1155/2010/570279.

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Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them. This approach provides better results in terms of area, speed, and power consumption compared to traditional uniprocessor digital systems. Reconfigurable multiprocessor systems are a particular type of embedded system, implemented using reconfigurable hardware. This paper presents a review of this emerging research area. A number of state-of-the-art systems published in this field are presented and classified. Design methods and challenges are also discussed. Advances in FPGA technology are leading to more powerful systems in terms of processing and flexibility. Flexibility is one of the strong points of this kind of system, and multiprocessor systems can even be reconfigured at run time, allowing hardware to be adjusted to the demands of the application.

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Dandekar, Omkar, William Plishker, Shuvra S. Bhattacharyya, and Raj Shekhar. "Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration." International Journal of Reconfigurable Computing 2008 (2008): 1–17. http://dx.doi.org/10.1155/2008/738174.

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In real-time signal processing, a single application often has multiple computationally intensive kernels that can benefit from acceleration using custom or reconfigurable hardware platforms, such as field-programmable gate arrays (FPGAs). For adaptive utilization of resources at run time, FPGAs with capabilities for dynamic reconfiguration are emerging. In this context, it is useful for designers to derive sets of efficient configurations that trade off application performance with fabric resources. Such sets can be maintained at run time so that the best available design tradeoff is used. Finding a single, optimized configuration is difficult, and generating a family of optimized configurations suitable for different run-time scenarios is even more challenging. We present a novel multiobjective wordlength optimization strategy developed through FPGA-based implementation of a representative computationally intensive image processing application: medical image registration. Tradeoffs between FPGA resources and implementation accuracy are explored, and Pareto-optimized wordlength configurations are systematically identified. We also compare search methods for finding Pareto-optimized design configurations and demonstrate the applicability of search based on evolutionary techniques for identifying superior multiobjective tradeoff curves. We demonstrate feasibility of this approach in the context of FPGA-based medical image registration; however, it may be adapted to a wide range of signal processing applications.

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Wang, Jian, and Ying Li. "RDAMS: An Efficient Run-Time Approach for Memory Fault and Hardware Trojans Detection." Information 12, no. 4 (April 14, 2021): 169. http://dx.doi.org/10.3390/info12040169.

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Ensuring the security of IoT devices and chips at runtime has become an urgent task as they have been widely used in human life. Embedded memories are vital components of SoC (System on Chip) in these devices. If they are attacked or incur faults at runtime, it will bring huge losses. In this paper, we propose a run-time detection architecture for memory security (RDAMS) to detect memory threats (fault and Hardware Trojans attack). The architecture consists of a Security Detection Core (SDC) that controls and enforces the detection procedure as a “security brain”, and a memory wrapper (MEM_wrapper) which interacts with memory to assist the detection. We also design a low latency response mechanism to solve the SoC performance degradation caused by run-time detection. A block-based multi-granularity detection approach is proposed to render the design flexible and reduce the cost in implementation using the FPGA’s dynamic partial reconfigurable (DPR) technology, which enables online detection mode reconfiguration according to the requirements. Experimental results show that RDAMS can correctly detect and identify 10 modeled memory faults and two types of Hardware Trojans (HTs) attacks without leading a great performance degradation to the system.

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Davidson, Tom, Fatma Abouelella, Karel Bruneel, and Dirk Stroobandt. "Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment." International Journal of Reconfigurable Computing 2012 (2012): 1–13. http://dx.doi.org/10.1155/2012/716984.

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Parameterised reconfiguration is a method for dynamic circuit specialization on FPGAs. The main advantage of this new concept is the high resource efficiency. Additionally, there is an automated tool flow,TMAP, that converts a hardware design into a more resource-efficient run-time reconfigurable design without a large design effort. We will start by explaining the core principles behind the dynamic circuit specialization technique. Next, we show the possible gains in encryption applications using an AES encoder. Our AES design shows a 20.6% area gain compared to an unoptimized hardware implementation and a 5.3% gain compared to a manually optimized third-party hardware implementation. We also usedTMAPon a Triple-DES and an RC6 implementation, where we achieve a 27.8% and a 72.7% LUT-area gain. In addition, we discuss a run-time reconfigurable DNA aligner. We focus on the optimizations to the dynamic specialization overhead. Our final design is up to 2.80-times more efficient on cheaper FPGAs than the original DNA aligner when at least one DNA sequence is longer than 758 characters. Most sequences in DNA alignment are of the order 213.

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Sharma, Dimple, and Lev Kirischian. "A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs." International Journal of Reconfigurable Computing 2021 (January 7, 2021): 1–20. http://dx.doi.org/10.1155/2021/8818788.

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Autonomous mobile systems nowadays deploy FPGA-based System on Programmable Chips (SoPCs) for supporting their dynamic multitask multimodal workloads. For such field-deployed systems, activation times, execution periods of tasks, and variations in environmental conditions are usually difficult to predict. These dynamic variations result in a new challenge of dynamic thermal cycling stress on the SoPC die, which can result in transient and even permanent hardware faults in the computing system. This paper proposes the approach of run-time structural adaptation (RTSA) to mitigate dynamic thermal cycling stress on the SoPC dies. RTSA assumes the tasks to have multiple implementation variants, called Application Specific Processing (ASP) circuit variants, which vary in hardware resources, operating frequency, and power consumption. Dynamically reconfiguring appropriate ASP circuit variants of tasks allow systems to maintain their die temperature in the desired range while taking into account variations in power budget and modes of operation. This means the essence of RTSA is a decision-making mechanism which can select at run-time, a suitable system configuration (set of ASP circuit variants of active tasks), whenever needed, to meet the die temperature constraints. To do so, run-time die temperature prediction for potential system configurations using an estimation model is required. This paper presents a generic method to derive an analytical model for any SoPC that can estimate the die temperature in real time and thus support the decision-making mechanism. To develop this method, the thermal behavior of SoPC die under different task scenarios is studied and relation of die temperature to frequency, resource utilization, and power consumption is analyzed. An RTSA-enabled experimental platform is set up on Xilinx Zynq XC7Z020 SoPC for this purpose. Experimental results also demonstrate that the proposed method can be used to derive a model in run-time, thus enabling systems to self-derive and dynamically update the model in run-time.

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Sharma, Dimple, and Lev Kirischian. "A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs." International Journal of Reconfigurable Computing 2021 (January 7, 2021): 1–20. http://dx.doi.org/10.1155/2021/8818788.

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Autonomous mobile systems nowadays deploy FPGA-based System on Programmable Chips (SoPCs) for supporting their dynamic multitask multimodal workloads. For such field-deployed systems, activation times, execution periods of tasks, and variations in environmental conditions are usually difficult to predict. These dynamic variations result in a new challenge of dynamic thermal cycling stress on the SoPC die, which can result in transient and even permanent hardware faults in the computing system. This paper proposes the approach of run-time structural adaptation (RTSA) to mitigate dynamic thermal cycling stress on the SoPC dies. RTSA assumes the tasks to have multiple implementation variants, called Application Specific Processing (ASP) circuit variants, which vary in hardware resources, operating frequency, and power consumption. Dynamically reconfiguring appropriate ASP circuit variants of tasks allow systems to maintain their die temperature in the desired range while taking into account variations in power budget and modes of operation. This means the essence of RTSA is a decision-making mechanism which can select at run-time, a suitable system configuration (set of ASP circuit variants of active tasks), whenever needed, to meet the die temperature constraints. To do so, run-time die temperature prediction for potential system configurations using an estimation model is required. This paper presents a generic method to derive an analytical model for any SoPC that can estimate the die temperature in real time and thus support the decision-making mechanism. To develop this method, the thermal behavior of SoPC die under different task scenarios is studied and relation of die temperature to frequency, resource utilization, and power consumption is analyzed. An RTSA-enabled experimental platform is set up on Xilinx Zynq XC7Z020 SoPC for this purpose. Experimental results also demonstrate that the proposed method can be used to derive a model in run-time, thus enabling systems to self-derive and dynamically update the model in run-time.

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Kirischian, L., V. Dumitriu, P. W. Chun, and G. Okouneva. "Mechanism of Resource Virtualization in RCS for Multitask Stream Applications." International Journal of Reconfigurable Computing 2010 (2010): 1–13. http://dx.doi.org/10.1155/2010/159367.

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Virtualization of logic, routing, and communication resources in recent FPGA devices can provide a dramatic improvement in cost-efficiency for reconfigurable computing systems (RCSs). The presented work is “proof-of-concept” research for the virtualization of the above resources in partially reconfigurable FPGA devices with a tile-based architecture. The following aspects have been investigated, prototyped, tested, and analyzed: (i) platform architecture for hardware support of the dynamic allocation of Application Specific Virtual Processors (ASVPs), (ii) mechanisms for run-time on-chip ASVP assembling using virtual hardware Components (VHCs) as building blocks, and (iii) mechanisms for dynamic on-chip relocation of VHCs to predetermined slots in the target FPGA. All the above mechanisms and procedures have been implemented and tested on a prototype platform—MARS (multitask adaptive reconfigurable system) using a Xilinx Virtex-4 FPGA. The on-chip communication infrastructure has been developed and investigated in detail, and its timing and hardware overhead were analyzed. It was determined that component relocation can be done without affecting the ASVP pipeline cycle time and throughput. The hardware overhead was estimated as relatively small compared to the gain of other performance parameters. Finally, industrial applications associated with next generation space-borne platforms are discussed, where the proposed approach can be beneficial.

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Ortiz, Alberto, Alfonso Rodríguez, Raúl Guerra, Sebastián López, Andrés Otero, Roberto Sarmiento, and Eduardo de la Torre. "A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images." Remote Sensing 10, no. 11 (November 12, 2018): 1790. http://dx.doi.org/10.3390/rs10111790.

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Space missions are facing disruptive innovation since the appearance of small, lightweight, and low-cost satellites (e.g., CubeSats). The use of commercial devices and their limitations in cost usually entail a decrease in available on-board computing power. To face this change, the on-board processing paradigm is advancing towards the clustering of satellites, and moving to distributed and collaborative schemes in order to maintain acceptable performance levels in complex applications such as hyperspectral image processing. In this scenario, hybrid hardware/software and reconfigurable computing have appeared as key enabling technologies, even though they increase complexity in both design and run time. In this paper, the ARTICo3 framework, which abstracts and eases the design and run-time management of hardware-accelerated systems, has been used to deploy a networked implementation of the Fast UNmixing (FUN) algorithm, which performs linear unmixing of hyperspectral images in a small cluster of reconfigurable computing devices that emulates a distributed on-board processing scenario. Algorithmic modifications have been proposed to enable data-level parallelism and foster scalability in two ways: on the one hand, in the number of accelerators per reconfigurable device; on the other hand, in the number of network nodes. Experimental results motivate the use of ARTICo3-enabled systems for on-board processing in applications traditionally addressed by high-performance on-Earth computation. Results also show that the proposed implementation may be better, for certain configurations, than an equivalent software-based solution in both performance and energy efficiency, achieving great scalability that is only limited by communication bandwidth.

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Fazlali, Mahmood, Ali Zakerolhosseini, and Georgi Gaydadjiev. "Efficient datapath merging for the overhead reduction of run-time reconfigurable systems." Journal of Supercomputing 59, no. 2 (June 17, 2010): 636–57. http://dx.doi.org/10.1007/s11227-010-0458-3.

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Pan, J. Z., and R. V. Patel. "Reconfigurable distributed real-time processing for multi-robot control: Design, implementation and experimentation." Robotica 22, no. 6 (November 2004): 661–79. http://dx.doi.org/10.1017/s0263574704000360.

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Sophisticated robotic applications require systems to be reconfigurable at the system level. Aiming at this requirement, this paper presents the design and implementation of a software architecture for a reconfigurable real-time multi-processing system for multi-robot control. The system is partitioned into loosely coupled function units and the data modules manipulated by the function units. Modularized and unified structures of the sub-controllers and controller processes are designed and constructed. All the controller processes run autonomously and intra-sub-controller information exchange is realized by shared data modules that serve as a data repository in the sub-controller. The dynamic data-management processes are responsible for data exchange among sub-controllers and across the computer network. Among sub-controllers there is no explicit temporal synchronization and the data dependencies are maintained by using datum-based synchronization. The hardware driver is constructed as a two-layered system to facilitate adaptation to various robotic hardware systems. A series of effective schemes for software fault detection, fault anticipation and fault termination are accomplished to improve run-time safety. The system is implemented cost-effectively on a QNX real-time operating system (RTOS) based system with a complete PC architecture, and experimentally validated successfully on an experimental dual-arm test-bed. The results indicate that the architectural design and implementation are well suited for advanced application tasks.

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Sharma, Dimple, Lev Kirischian, and Valeri Kirischian. "Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC." Computers 7, no. 4 (October 11, 2018): 52. http://dx.doi.org/10.3390/computers7040052.

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Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.

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GERMAIN, CECILE, and FRANCK CAPPELLO. "THE STATIC NETWORK: A HIGH PERFORMANCE RECONFIGURABLE COMMUNICATION NETWORK." Parallel Processing Letters 05, no. 01 (March 1995): 97–109. http://dx.doi.org/10.1142/s0129626495000096.

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This paper presents a new interconnection network for a massively parallel architecture based on the static model of communication. The principle of the model is to schedule at run time, on a circuit switching hardware, the off-line routed circuits computed at compile time. Designing a network especially for the compiled model can take full benefit of the current interconnection technology. The static network is intended to a synchronised MIMD distributed memory machine, based on high performance processing nodes including microprocessors. The application scope is numerical computation, where all communication patterns may occur. The hardware issues are the various synchronisations inside the network, which need a sophisticated switch design to keep pace with 1.33 Gbit/s links. The network is designed to reach a sustained aggregate bandwidth of more than 500GBytes/s, and provide an overall latency less than 270ns, up to 4K inputs. The network is fully pipelined and can be reconfigured each 60ns.

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Kaufmann, Paul, Kyrre Glette, Marco Platzner, and Jim Torresen. "Compensating Resource Fluctuations by Means of Evolvable Hardware." International Journal of Adaptive, Resilient and Autonomic Systems 3, no. 4 (October 2012): 17–31. http://dx.doi.org/10.4018/jaras.2012100102.

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The evolvable hardware (EHW) paradigm facilitates the construction of autonomous systems that can adapt to environmental changes and degradation of the computational resources. Extending the EHW principle to architectural adaptation, the authors study the capability of evolvable hardware classifiers to adapt to intentional run-time fluctuations in the available resources, i.e., chip area, in this work. To that end, the authors leverage the Functional Unit Row (FUR) architecture, a coarse-grained reconfigurable classifier, and apply it to two medical benchmarks, the Pima and Thyroid data sets from the UCI Machine Learning Repository. While quick recovery from architectural changes was already demonstrated for the FUR architecture, the authors also introduce two reconfiguration schemes helping to reduce the magnitude of degradation after architectural reconfiguration.

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Funie, Andreea-Ingrid, Paul Grigoras, Pavel Burovskiy, Wayne Luk, and Mark Salmon. "Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies." Journal of Signal Processing Systems 90, no. 1 (May 8, 2017): 39–52. http://dx.doi.org/10.1007/s11265-017-1244-8.

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Cardona, Luis Andres, and Carles Ferrer. "AC_ICAP: A Flexible High Speed ICAP Controller." International Journal of Reconfigurable Computing 2015 (2015): 1–15. http://dx.doi.org/10.1155/2015/314358.

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The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.

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Dumitriu, Victor, Lev Kirischian, and Valeri Kirischian. "Run-Time Recovery Mechanism for Transient and Permanent Hardware Faults Based on Distributed, Self-Organized Dynamic Partially Reconfigurable Systems." IEEE Transactions on Computers 65, no. 9 (September 1, 2016): 2835–47. http://dx.doi.org/10.1109/tc.2015.2506558.

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Hosseinabady, M., and J. L. Nunez-Yanez. "Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles." IET Computers & Digital Techniques 6, no. 1 (2012): 1. http://dx.doi.org/10.1049/iet-cdt.2010.0097.

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Chen, Hsiu-Niang, and Kuo-Liang Chung. "Partitionable Bus-based String-matching Algorithm for Run-length Coded Strings With VLDCs." VLSI Design 9, no. 1 (January 1, 1999): 55–67. http://dx.doi.org/10.1155/1999/75313.

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String matching (SM) problem is to find the occurrences of a pattern within a text. A vanable length don't care (VLDC) is a special symbol, not belonging to a finite alphabet ∑ but in ∑*. Each VLDC in the pattern can match any substring in the text. Given a run-length coded text of length 2n over ∑ and a run-length coded pattern of length 2m over ∑*, this paper first presents an O(1) time parallel SM algorithm for run-length coded strings with VLDCs on a reconfigurable mesh (RM) using O(nm) processors. Consider the hardware limitation in VLSI implementation. In order to be suitable for VLSI modular implementation, a partitionable parallel algorithm on the RM with limited processors is further presented. For N < n and M < m, the SM for run-length coded strings with VLDCs can be solved in O(X^Y^) time on the RM using O(NM)(= O((nm)/((X^Y^))) processors, where X^ = [(n – 1)/(N – 1)] and Y^ = [(m – 1)/(M – 1)].

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Gharbi, Ibrahim, Hamza Gharsellaoui, and Sadok Bouamama. "New Hybrid Genetic Based Approach for Real-Time Scheduling of Reconfigurable Embedded Systems." International Journal of Advanced Pervasive and Ubiquitous Computing 10, no. 1 (January 2018): 23–36. http://dx.doi.org/10.4018/ijapuc.2018010102.

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This journal article deals with the problem of real-time scheduling of operating systems (OS) tasks by a hybrid genetic-based scheduling algorithm. Indeed, most of real-time systems are framed with aid of priority-based scheduling algorithms. Nevertheless, when such a scenario is applied to save the system at the occurrence of hardware-software faults, or to improve its performance, some real-time properties can be violated at run-time. In contrast, most of the applications of real-time systems are based on timing constraints, i.e. OS tasks should be scheduled properly to finish their execution within the time specified by the real-time systems. For this reason, the authors propose in their article, a hybrid genetic-based scheduling approach that automatically checks the systems feasibility after any reconfiguration scenario was applied to an embedded system. A benchmark example is given, and the experimental results demonstrate the effectiveness of the originally proposed genetic-based scheduling approach over other such classical genetic algorithmic approaches.

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CORSONELLO, PASQUALE, and STEFANIA PERRI. "EFFICIENT RECONFIGURABLE MANCHESTER ADDERS FOR LOW-POWER MEDIA PROCESSING." Journal of Circuits, Systems and Computers 14, no. 01 (February 2005): 57–63. http://dx.doi.org/10.1142/s0218126605002222.

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A new highly reconfigurable Manchester adder for low-power media signal processing is presented. The proposed circuit can be run-time partitioned. Its 64-bit version performs one 64-, two 32-, four 16-, or eight 8-bit additions. When the AMS 0.35 mm 2-poly 3-metal 3.3 V CMOS (CSD) process is used to produce a layout, an energy dissipation of only 78 pJ and a worst propagation delay of about 10.2 ns are obtained. The novelty demonstrated in this letter is that the introduction of dummy bit positions along the carry-path can be avoided using on-purpose dynamic logic stages.

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Weigong, Zhang, Li Chao, Qiu Keni, Zhang Shaonan, and Chen Xianglong. "A Novel Time Synchronization Method for Dynamic Reconfigurable Bus." VLSI Design 2016 (April 3, 2016): 1–10. http://dx.doi.org/10.1155/2016/5752080.

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UM-BUS is a novel dynamically reconfigurable high-speed serial bus for embedded systems. It can achieve fault tolerance by detecting the channel status in real time and reconfigure dynamically at run-time. The bus supports direct interconnections between up to eight master nodes and multiple slave nodes. In order to solve the time synchronization problem among master nodes, this paper proposes a novel time synchronization method, which can meet the requirement of time precision in UM-BUS. In this proposed method, time is firstly broadcasted through time broadcast packets. Then, the transmission delay and time deviations via three handshakes during link self-checking and channel detection can be worked out referring to the IEEE 1588 protocol. Thereby, each node calibrates its own time according to the broadcasted time. The proposed method has been proved to meet the requirement of real-time time synchronization. The experimental results show that the synchronous precision can achieve a bias less than 20 ns.

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Liu, Xing, Haiying Zhou, Jianwen Xiang, Shengwu Xiong, Kun Mean Hou, Christophe de Vaulx, Huan Wang, Tianhui Shen, and Qing Wang. "Energy and Delay Optimization of Heterogeneous Multicore Wireless Multimedia Sensor Nodes by Adaptive Genetic-Simulated Annealing Algorithm." Wireless Communications and Mobile Computing 2018 (2018): 1–13. http://dx.doi.org/10.1155/2018/7494829.

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Energy efficiency and delay optimization are significant for the proliferation of wireless multimedia sensor network (WMSN). In this article, an energy-efficient, delay-efficient, hardware and software cooptimization platform is researched to minimize the energy cost while guaranteeing the deadline of the real-time WMSN tasks. First, a multicore reconfigurable WMSN hardware platform is designed and implemented. This platform uses both the heterogeneous multicore architecture and the dynamic voltage and frequency scaling (DVFS) technique. By this means, the nodes can adjust the hardware characteristics dynamically in terms of the software run-time contexts. Consequently, the software can be executed more efficiently with less energy cost and shorter execution time. Then, based on this hardware platform, an energy and delay multiobjective optimization algorithm and a DVFS adaption algorithm are investigated. These algorithms aim to search out the global energy optimization solution within the acceptable calculation time and strip the time redundancy in the task executing process. Thus, the energy efficiency of the WMSN node can be improved significantly even under strict constraint of the execution time. Simulation and real-world experiments proved that the proposed approaches can decrease the energy cost by more than 29% compared to the traditional single-core WMSN node. Moreover, the node can react quickly to the time-sensitive events.

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Barrios, Yubal, Alfonso Rodríguez, Antonio Sánchez, Arturo Pérez, Sebastián López, Andrés Otero, Eduardo de la Torre, and Roberto Sarmiento. "Lossy Hyperspectral Image Compression on a Reconfigurable and Fault-Tolerant FPGA-Based Adaptive Computing Platform." Electronics 9, no. 10 (September 26, 2020): 1576. http://dx.doi.org/10.3390/electronics9101576.

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This paper describes a novel hardware implementation of a lossy multispectral and hyperspectral image compressor for on-board operation in space missions. The compression algorithm is a lossy extension of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 lossless standard that includes a bit-rate control stage, which in turn manages the losses the compressor may introduce to achieve higher compression ratios without compromising the recovered image quality. The algorithm has been implemented using High-Level Synthesis (HLS) techniques to increase design productivity by raising the abstraction level. The proposed lossy compression solution is deployed onto ARTICo3, a dynamically reconfigurable multi-accelerator architecture, obtaining a run-time adaptive solution that enables user-selectable performance (i.e., load more hardware accelerators to transparently increase throughput), power consumption, and fault tolerance (i.e., group hardware accelerators to transparently enable hardware redundancy). The whole compression solution is tested on a Xilinx Zynq UltraScale+ Field-Programmable Gate Array (FPGA)-based MPSoC using different input images, from multispectral to ultraspectral. For images acquired by the Airborne Visible/Infrared Imaging Spectrometer (AVIRIS), the proposed implementation renders an execution time of approximately 36 s when 8 accelerators are compressing concurrently at 100 MHz, which in turn uses around 20% of the LUTs and 17% of the dedicated memory blocks available in the target device. In this scenario, a speedup of 15.6× is obtained in comparison with a pure software version of the algorithm running in an ARM Cortex-A53 processor.

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Farhadi Beldachi, Arash, Mohammad Hosseinabady, and Jose Luis Nunez-Yanez. "Configurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC." International Journal of Reconfigurable and Embedded Systems (IJRES) 2, no. 1 (March 1, 2013): 27. http://dx.doi.org/10.11591/ijres.v2.i1.pp27-48.

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New Field Programmable Gate Arrays (FPGAs) are capable of implementing complete multi-core System-on-Chip (SoC) with the possibility of modifying the hardware configuration at run-time with partial dynamic reconfiguration. The usage of a soft reconfigurable Network-on-Chip (NoC) to connect these cores is investigated in this paper. We have used a standard switch developed with the objective of supporting dynamically reconfigurable FPGAs as the starting point to create a novel configurable router. The configurable router uses distributed routing suitable for regular topologies and can vary the number of local ports and communication ports to build multi dimensional networks (i.e., 2D and 3D) with different topologies. The evaluation results show that the selection of the ideal router is different depending on traffic patterns and design objectives. Overall, the mesh network with a four local ports router offers a higher level of performance with lower complexity compared to the traditional mesh with one local port router.

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Asghar, Rizwan, and Dake Liu. "Multimode Flex-Interleaver Core for Baseband Processor Platform." Journal of Computer Systems, Networks, and Communications 2010 (2010): 1–16. http://dx.doi.org/10.1155/2010/793807.

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This paper presents a flexible interleaver architecture supporting multiple standards like WLAN, WiMAX, HSPA+, 3GPP-LTE, and DVB. Algorithmic level optimizations like 2D transformation and realization of recursive computation are applied, which appear to be the key to reach to an efficient hardware multiplexing among different interleaver implementations. The presented hardware enables the mapping of vital types of interleavers including multiple block interleavers and convolutional interleaver onto a single architecture. By exploiting the hardware reuse methodology the silicon cost is reduced, and it consumes 0.126 mm2area in total in 65 nm CMOS process for a fully reconfigurable architecture. It can operate at a frequency of 166 MHz, providing a maximum throughput up to 664 Mbps for a multistream system and 166 Mbps for single stream communication systems, respectively. One of the vital requirements for multimode operation is the fast switching between different standards, which is supported by this hardware with minimal cycle cost overheads. Maximum flexibility and fast switchability among multiple standards during run time makes the proposed architecture a right choice for the radio baseband processing platform.

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Magalhães Pereira, Monica, and Luigi Carro. "Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates." International Journal of Reconfigurable Computing 2011 (2011): 1–17. http://dx.doi.org/10.1155/2011/452589.

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The aggressive scaling of CMOS technology has increased the density and allowed the integration of multiple processors into a single chip. Although solutions based on MPSoC architectures can increase application's speed through TLP exploitation, this speedup is still limited to the amount of parallelism available in the application, as demonstrated by Amdahl's Law. Moreover, with the continuous shrinking of device features, very aggressive defect rates are expected for new technologies. Under high defect rates a large amount of processors of the MPSoC will be susceptible to defects and consequently will fail, not only reducing yield but also severely affecting the expected performance. This paper presents a run-time adaptive architecture that allows software execution even under aggressive defect rates. The proposed architecture can accelerate not only highly parallel applications but also sequential ones, and it is a heterogeneous solution to overcome the performance penalty that is imposed to homogeneous MPSoCs under massive defect rates.

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Amar, Hebibi, Arres Bartil, and Lahcene Ziet. "Comparison of two new methods for implementa BPSK modulator using FPGA." Indonesian Journal of Electrical Engineering and Computer Science 19, no. 2 (August 1, 2020): 819. http://dx.doi.org/10.11591/ijeecs.v19.i2.pp819-827.

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The design of electronic systems has become mainly dependent on FPGAs applications. This is due to the softness effectiveness progress by reconfigurable computing and reduced time to develop solutions for digital signal processing. In this article, we present the theoretical backgrounds of a BPSK modulation and hardware designs of the BPSK system, a firstly with the help of Matlab/Simulink reliant on the System Generator and a second with Xilinx ISE VERILOG Hardware Description Language. In order to show the differences between them, in terms of efficiency, duration of development and how many resources are used in FPGA. For the projected system, we have a tendency to aimed toward employing a moderately sized, low-value FPGA to implement the system. The Atlys development board by Digilent to configure develops, and run the system, based on a Xilinx Spartan-6 LX45 FPGA.

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Pfänder, O. A., H. J. Pfleiderer, and S. W. Lachowicz. "Configurable multiplier modules for an adaptive computing system." Advances in Radio Science 4 (September 6, 2006): 231–36. http://dx.doi.org/10.5194/ars-4-231-2006.

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Abstract. The importance of reconfigurable hardware is increasing steadily. For example, the primary approach of using adaptive systems based on programmable gate arrays and configurable routing resources has gone mainstream and high-performance programmable logic devices are rivaling traditional application-specific hardwired integrated circuits. Also, the idea of moving from the 2-D domain into a 3-D design which stacks several active layers above each other is gaining momentum in research and industry, to cope with the demand for smaller devices with a higher scale of integration. However, optimized arithmetic blocks in course-grain reconfigurable arrays as well as field-programmable architectures still play an important role. In countless digital systems and signal processing applications, the multiplication is one of the critical challenges, where in many cases a trade-off between area usage and data throughput has to be made. But the a priori choice of word-length and number representation can also be replaced by a dynamic choice at run-time, in order to improve flexibility, area efficiency and the level of parallelism in computation. In this contribution, we look at an adaptive computing system called 3-D-SoftChip to point out what parameters are crucial to implement flexible multiplier blocks into optimized elements for accelerated processing. The 3-D-SoftChip architecture uses a novel approach to 3-dimensional integration based on flip-chip bonding with indium bumps. The modular construction, the introduction of interfaces to realize the exchange of intermediate data, and the reconfigurable sign handling approach will be explained, as well as a beneficial way to handle and distribute the numerous required control signals.

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Ramalingam, Balakrishnan, Rajesh Elara Mohan, Selvasundari Balakrishnan, Karthikeyan Elangovan, Braulio Félix Gómez, Thejus Pathmakumar, Manojkumar Devarassu, Madan Mohan Rayaguru, and Chanthini Baskar. "sTetro-Deep Learning Powered Staircase Cleaning and Maintenance Reconfigurable Robot." Sensors 21, no. 18 (September 18, 2021): 6279. http://dx.doi.org/10.3390/s21186279.

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Staircase cleaning is a crucial and time-consuming task for maintenance of multistory apartments and commercial buildings. There are many commercially available autonomous cleaning robots in the market for building maintenance, but few of them are designed for staircase cleaning. A key challenge for automating staircase cleaning robots involves the design of Environmental Perception Systems (EPS), which assist the robot in determining and navigating staircases. This system also recognizes obstacles and debris for safe navigation and efficient cleaning while climbing the staircase. This work proposes an operational framework leveraging the vision based EPS for the modular re-configurable maintenance robot, called sTetro. The proposed system uses an SSD MobileNet real-time object detection model to recognize staircases, obstacles and debris. Furthermore, the model filters out false detection of staircases by fusion of depth information through the use of a MobileNet and SVM. The system uses a contour detection algorithm to localize the first step of the staircase and depth clustering scheme for obstacle and debris localization. The framework has been deployed on the sTetro robot using the Jetson Nano hardware from NVIDIA and tested with multistory staircases. The experimental results show that the entire framework takes an average of 310 ms to run and achieves an accuracy of 94.32% for staircase recognition tasks and 93.81% accuracy for obstacle and debris detection tasks during real operation of the robot.

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Nishikant Sadafale, Minal Deshmukh, Prasad Khandekar,. "AN EFFICIENT FPGA OVERLAY FOR COLOR TRANSFORMATION FUNCTION USING HIGH LEVEL SYNTHESIS." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 1 (March 1, 2021): 280–87. http://dx.doi.org/10.17762/itii.v9i1.130.

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Image Processing is a significantly desirable in commercial, industrial, and medical applications. Processor based architectures are inappropriate for real time applications as Image processing algorithms are quite intensive in terms of computations. To reduce latency and limitation in performance due to limited amount of memory and fixed clock frequency for synthesis in processor-based architecture, FPGA can be used in smart devices for implementing real time image processing applications. To increase speed of real time image processing custom overlays (Hardware Library of programmable logic circuit) can be designed to run on FPGA fabric. The IP core generated by the HLS (High Level Synthesis) can be implemented on a reconfigurable platform which allows effective utilization of channel bandwidth and storage. In this paper we have presented FPGA overlay design for color transformation function using Xilinx’s python productivity board PYNQ-Z2 to get benefit in performance over a traditional processor. Performance comparison of custom overlay on FPGA and Processor based platform shows FPGA execution yields minimum computation time.

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N, Geethanjali, and Dr Rekha K. R. "Design and Implementation of a Efficient Router using X Y Algorithm." Indian Journal of Data Communication and Networking 1, no. 3 (June 10, 2021): 5–9. http://dx.doi.org/10.35940/ijdcn.b5009.061321.

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The engineering for on chip network configuration utilizing dynamic reconfiguration is an answer for Communication Interfaces, Chip cost, Quality of Service, ensure adaptability of the organization. The proposed engineering powerfully arrange itself concerning Hardware Modules like switches, Switch based packet , information to a packet size with changing the correspondence situation and its prerequisites on run time. The NOC Architecture assumes urgent part while planning correspondence frameworks intended for SOC. The NOC engineering be better over traditional transport, mutual transport plan , cross bar interconnection design intended for on chip organizations. In a greater part of the NO C engineering contains lattice, torus or different geographies to plan solid switch. In any case, the greater part of the plans are neglects to advance a Quality of Service, blocking issues, cost, Chip as well as mostly plan throughput, region transparency with inactivity. Proposed plan we are planning a reconfigurable switch for network on chip plan that improve the correspondence performance. The proposed configuration dodges the restrictions of transport based interconnection plans which are frequently applied in part progressively reconfigurable FPGA plans. . With the assistance of this switch plan we can accomplish low inactivity and high information throughput.

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Hariharan, I., and M. Kannan. "Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate the Reconfiguration Overheads in Reconfigurable Systems." Journal of Circuits, Systems and Computers 28, no. 14 (March 15, 2019): 1950246. http://dx.doi.org/10.1142/s0218126619502463.

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Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology.

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Meloni, Paolo, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, and Menno Lindwer. "Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper." VLSI Design 2012 (March 29, 2012): 1–16. http://dx.doi.org/10.1155/2012/580584.

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Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

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Canesche, Michael, Westerley Carvalho, Lucas Reis, Matheus Oliveira, Salles Magalhães, Peter Jamieson, Jaugusto M. Nacif, and Ricardo Ferreira. "You Only Traverse Twice: A YOTT Placement, Routing, and Timing Approach for CGRAs." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–25. http://dx.doi.org/10.1145/3477038.

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Coarse-grained reconfigurable architecture (CGRA) mapping involves three main steps: placement, routing, and timing. The mapping is an NP-complete problem, and a common strategy is to decouple this process into its independent steps. This work focuses on the placement step, and its aim is to propose a technique that is both reasonably fast and leads to high-performance solutions. Furthermore, a near-optimal placement simplifies the following routing and timing steps. Exact solutions cannot find placements in a reasonable execution time as input designs increase in size. Heuristic solutions include meta-heuristics, such as Simulated Annealing (SA) and fast and straightforward greedy heuristics based on graph traversal. However, as these approaches are probabilistic and have a large design space, it is not easy to provide both run-time efficiency and good solution quality. We propose a graph traversal heuristic that provides the best of both: high-quality placements similar to SA and the execution time of graph traversal approaches. Our placement introduces novel ideas based on “you only traverse twice” (YOTT) approach that performs a two-step graph traversal. The first traversal generates annotated data to guide the second step, which greedily performs the placement, node per node, aided by the annotated data and target architecture constraints. We introduce three new concepts to implement this technique: I/O and reconvergence annotation, degree matching, and look-ahead placement. Our analysis of this approach explores the placement execution time/quality trade-offs. We point out insights on how to analyze graph properties during dataflow mapping. Our results show that YOTT is 60.6 , 9.7 , and 2.3 faster than a high-quality SA, bounding box SA VPR, and multi-single traversal placements, respectively. Furthermore, YOTT reduces the average wire length and the maximal FIFO size (additional timing requirement on CGRAs) to avoid delay mismatches in fully pipelined architectures.

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Claus, Christopher, Walter Stechele, and Andreas Herkersdorf. "Autovision – A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision – Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme)." it - Information Technology 49, no. 3 (January 1, 2007). http://dx.doi.org/10.1524/itit.2007.49.3.181.

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In this article the Autovision architecture is presented, a new Multi Processor System-on-Chip (MPSoC) architecture for future video-based driver assistance systems, using run-time reconfigurable hardware accelerator engines for video processing. According to various driving conditions (highway, city, sunlight, rain, tunnel entrance) different algorithms have to be used for video processing. These different algorithms require different hardware accelerator engines, which are loaded into the Autovision chip at run-time of the system, triggered by changing driving conditions. It was investigated how to use dynamic partial reconfiguration to load and operate the correct hardware accelerator engines in time, while removing unused engines in order to save precious chip area.

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Journal articles on the topic 'Run-time reconfigurable hardware'

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