Relevant bibliographies by topics / Runtime Reconfiguration

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Runtime Reconfiguration'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Runtime Reconfiguration"

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Loukil, Sihem, Slim Kallel, and Mohamed Jmaiel. "Managing Architectural Reconfiguration at Runtime." International Journal of Web Portals 5, no. 1 (January 2013): 55–72. http://dx.doi.org/10.4018/jwp.2013010105.

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Managing dynamic reconfiguration of software systems is a tedious task in the software development because of the substantially increasing need for continuously available systems even at runtime. In particular, the software architecture of dynamically adaptive systems must continuously adapt to varying environmental conditions and user requirements. Therefore, they propose a wide range of possible configurations. The static enumeration of all the possible configurations is a difficult task. Moreover, not all dynamic reconfiguration operations can be foreseen at design time. Some reconfigurations may appear when the system is already deployed. In this context, we propose to combine the Architecture Description Languages and the Aspect-Oriented Software Development paradigm in order to make the dynamic reconfiguration process easier to design, understand and possible to validate. Also, this combination allows to easily evolving the reconfiguration policies even at runtime.
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McDonald, Eric. "Runtime FPGA partial reconfiguration." IEEE Aerospace and Electronic Systems Magazine 23, no. 7 (July 2008): 10–15. http://dx.doi.org/10.1109/maes.2008.4579286.

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Chen, Wei, Xiaoqiang Qiao, Jun Wei, Hua Zhong, and Tao Huang. "A Virtual Machine Placement and Reconfiguration Framework for Cloud Computing Platforms." International Journal of Adaptive, Resilient and Autonomic Systems 5, no. 2 (April 2014): 1–22. http://dx.doi.org/10.4018/ijaras.2014040101.

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As a rising application paradigm and technology, cloud computing can leverage the efficient pooling of on-demand, self-managed virtual infrastructure. How to maximize the resource utilization and how to reduce the cost of configuration are essential issues in cloud computing. In this paper, the authors propose a framework to achieve these objectives by optimizing VM placement and deciding when and how to perform the VM reconfigurations. The authors leverage the vector arithmetic to model the objective of balancing the multiple resource utilization and propose an optimization method for the static VM placement. Then the authors propose a two-level runtime reconfiguration policy, including the local adjustment and the parallel migration, to minimize the reconfiguration cost. Finally, the authors implement a prototype to validate and evaluate the proposed mechanism with a set of preliminary experiments, which shows that our work can maximize the resource utilization while effectively reducing the cost of the runtime reconfiguration.
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LEE, KEVIN, and GEOFFREY COULSON. "SUPPORTING RUNTIME RECONFIGURATION ON NETWORK PROCESSORS." Journal of Interconnection Networks 07, no. 04 (December 2006): 475–92. http://dx.doi.org/10.1142/s0219265906001818.

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Network Processors (NPs) are set to play a key role in the next generation of networking technology. They have the performance of ASIC-based routers whilst offering a high degree of programmability. However, the programmability potential of NPs can only be realised with appropriate software. In this paper we argue that specialised software to support runtime reconfiguration is needed to fully exploit the potential of NPs. We first justify supporting runtime reconfiguration on NPs by offering real-world scenarios and discussing the issues associated with these. We then demonstrate how runtime reconfiguration can be achieved in practice through a case study of our component-based programming approach on the Intel IXP2400 NP.
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Wildermann, S., J. Angermeier, E. Sibirko, and J. Teich. "Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures." International Journal of Reconfigurable Computing 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/608312.

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By means of partial reconfiguration, parts of the hardware can be dynamically exchanged at runtime. This allows that streaming application running in different modes of the systems can share resources. In this paper, we discuss the architectural issues to design such reconfigurable systems. For being able to reduce reconfiguration time, this paper furthermore proposes a novel algorithm to aggregate several streaming applications into a single representation, called merge graph. The paper also proposes an algorithm to place streaming application at runtime which not only considers the placement and communication constraints, but also allows to place merge tasks. In a case study, we implement the proposed algorithm as runtime support on an FPGA-based system on chip. Furthermore, experiments show that reconfiguration time can be considerably reduced by applying our approach.
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Puranik, Dipti Anil. "Runtime Reconfiguration of FPGA for Biomedical Applications." Indian Journal of Science and Technology 9, no. 1 (January 20, 2016): 1–15. http://dx.doi.org/10.17485/ijst/2016/v9i47/106429.

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Ali, M. Mubarak, R. Arun, and S. Saravanan. "Runtime Partial Reconfiguration of FPGAs for DSP Applications." Procedia Engineering 30 (2012): 514–18. http://dx.doi.org/10.1016/j.proeng.2012.01.892.

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Niu, Xinyu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu, and Oliver Pell. "Automating Elimination of Idle Functions by Runtime Reconfiguration." ACM Transactions on Reconfigurable Technology and Systems 8, no. 3 (May 19, 2015): 1–28. http://dx.doi.org/10.1145/2700415.

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Bingxiong Xu and D. H. Albonesi. "Runtime reconfiguration techniques for efficient general-purpose computation." IEEE Design & Test of Computers 17, no. 1 (2000): 42–52. http://dx.doi.org/10.1109/54.825676.

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Purnaprajna, Madhura, Mario Porrmann, Ulrich Rueckert, Michael Hussmann, Michael Thies, and Uwe Kastens. "Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis." ACM Transactions on Reconfigurable Technology and Systems 3, no. 3 (September 2010): 1–25. http://dx.doi.org/10.1145/1839480.1839487.

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Dissertations / Theses on the topic "Runtime Reconfiguration"

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Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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Tan, Heng. "A MULTI-LAYER FPGA FRAMEWORK SUPPORTING AUTONOMOUS RUNTIME PARTIAL RECONFIGURATION." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2375.

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Partial reconfiguration is a unique capability provided by several Field Programmable Gate Array (FPGA) vendors recently, which involves altering part of the programmed design within an SRAM-based FPGA at run-time. In this dissertation, a Multilayer Runtime Reconfiguration Architecture (MRRA) is developed, evaluated, and refined for Autonomous Runtime Partial Reconfiguration of FPGA devices. Under the proposed MRRA paradigm, FPGA configurations can be manipulated at runtime using on-chip resources. Operations are partitioned into Logic, Translation, and Reconfiguration layers along with a standardized set of Application Programming Interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. An MRRA mapping theory is developed to link the general logic function and area allocation information to the device related physical configuration level data by using mathematical data structure and physical constraints. In certain scenarios, configuration bit stream data can be read and modified directly for fast operations, relying on the use of similar logic functions and common interconnection resources for communication. A corresponding logic control flow is also developed to make the entire process autonomous. Several prototype MRRA systems are developed on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Area, speed and power optimization techniques are developed based on the developed Xilinx prototype. Evaluations and analysis of these prototype and techniques are performed on a number of benchmark and hashing algorithm case studies. The results indicate that based on a variety of test benches, up to 70% reduction in the resource utilization, up to 50% improvement in power consumption, and up to 10 times increase in run-time performance are achieved using the developed architecture and approaches compared with Xilinx baseline reconfiguration flow. Finally, a Genetic Algorithm (GA) for a FPGA fault tolerance case study is evaluated as a ultimate high-level application running on this architecture. It demonstrated that this is a hardware and software infrastructure that enables an FPGA to dynamically reconfigure itself efficiently under the control of a soft microprocessor core that is instantiated within the FPGA fabric. Such a system contributes to the observed benefits of intelligent control, fast reconfiguration, and low overhead.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Engineering PhD
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Philipp, François. "Runtime Hardware Reconfiguration in Wireless Sensor Networks for Condition Monitoring." Phd thesis, Universitäts- und Landesbibliothek Darmstadt, 2014. https://tuprints.ulb.tu-darmstadt.de/4159/7/diss.pdf.

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The integration of miniaturized heterogeneous electronic components has enabled the deployment of tiny sensing platforms empowered by wireless connectivity known as wireless sensor networks. Thanks to an optimized duty-cycled activity, the energy consumption of these battery-powered devices can be reduced to a level where several years of operation is possible. However, the processing capability of currently available wireless sensor nodes does not scale well with the observation of phenomena requiring a high sampling resolution. The large amount of data generated by the sensors cannot be handled efficiently by low-power wireless communication protocols without a preliminary filtering of the information relevant for the application. For this purpose, energy-efficient, flexible, fast and accurate processing units are required to extract important features from the sensor data and relieve the operating system from computationally demanding tasks. Reconfigurable hardware is identified as a suitable technology to fulfill these requirements, balancing implementation flexibility with performance and energy-efficiency. While both static and dynamic power consumption of field programmable gate arrays has often been pointed out as prohibitive for very-low-power applications, recent programmable logic chips based on non-volatile memory appear as a potential solution overcoming this constraint. This thesis first verifies this assumption with the help of a modular sensor node built around a field programmable gate array based on Flash technology. Short and autonomous duty-cycled operation combined with hardware acceleration efficiently drop the energy consumption of the device in the considered context. However, Flash-based devices suffer from restrictions such as long configuration times and limited resources, which reduce their suitability for complex processing tasks. A template of a dynamically reconfigurable architecture built around coarse-grained reconfigurable function units is proposed in a second part of this work to overcome these issues. The module is conceived as an overlay of the sensor node FPGA increasing the implementation flexibility and introducing a standardized programming model. Mechanisms for virtual reconfiguration tailored for resource-constrained systems are introduced to minimize the overhead induced by this genericity. The definition of this template architecture leaves room for design space exploration and application- specific customization. Nevertheless, this aspect must be supported by appropriate design tools which facilitate and automate the generation of low-level design files. For this purpose, a software tool is introduced to graphically configure the architecture and operation of the hardware accelerator. A middleware service is further integrated into the wireless sensor network operating system to bridge the gap between the hardware and the design tools, enabling remote reprogramming and scheduling of the hardware functionality at runtime. At last, this hardware and software toolchain is applied to real-world wireless sensor network deployments in the domain of condition monitoring. This category of applications often require the complex analysis of signals in the considered range of sampling frequencies such as vibrations or electrical currents, making the proposed system ideally suited for the implementation. The flexibility of the approach is demonstrated by taking examples with heterogeneous algorithmic specifications. Different data processing tasks executed by the sensor node hardware accelerator are modified at runtime according to application requests.
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Coskuner, Aydin Ibrahim. "A Novel Fault Tolerant Architecture On A Runtime Reconfigurable Fpga." Master's thesis, METU, 2006. http://etd.lib.metu.edu.tr/upload/12607849/index.pdf.

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Due to their programmable nature, Field Programmable Gate Arrays (FPGAs) offer a good test environment for reconfigurable systems. FPGAs can be reconfigured during the operation with changing demands. This feature, known as Runtime Reconfiguration (RTR), can be used to speed-up computations and reduce system cost. Moreover, it can be used in a wide range of applications such as adaptable hardware, fault tolerant architectures. This thesis is mostly concentrated on the runtime reconfigurable architectures. Critical properties of runtime reconfigurable architectures are examined. As a case study, a Triple Modular Redundant (TMR) system has been implemented on a runtime reconfigurable FPGA. The runtime reconfigurable structure increases the system reliability against faults. Especially, the weakness of SRAM based FPGAs against Single Event Upsets (SEUs) is eliminated by the designed system. Besides, the system can replace faulty elements with non-faulty elements during the operation. These features of the developed architecture provide extra safety to the system also prolong the life of the FPGA device without interrupting the whole system.
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PANDEY, ANKUR. "A MULTITHREADED RUNTIME SUPPORT ENVIRONMENT FOR DYNAMIC RECONFIGURABLE COMPUTING." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1026133065.

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Naber, Jens [Verfasser], and Christian [Akademischer Betreuer] Becker. "Runtime reconfiguration of physical and virtual pervasive systems / Jens Naber ; Betreuer: Christian Becker." Mannheim : Universitätsbibliothek Mannheim, 2020. http://d-nb.info/120436527X/34.

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Meyer, Dominik [Verfasser]. "Multicore reconfiguration platform - a research and evaluation FPGA framework for runtime reconfigurable systems / Dominik Meyer." Hamburg : Helmut-Schmidt-Universität, Bibliothek, 2015. http://d-nb.info/1068917326/34.

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Belaggoun, Amel. "Adaptability and reconfiguration of automotive embedded systems." Thesis, Paris 6, 2017. http://www.theses.fr/2017PA066252/document.

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Les véhicules modernes sont de plus en plus informatisés pour satisfaire les exigences de sureté les plus strictes et pour fournir de meilleures expériences de conduite. Par conséquent, le nombre d'unités de contrôle électronique (ECU) dans les véhicules modernes a augmenté de façon continue au cours des dernières années. En outre, les applications à calcul complexe offrent une demande de calcul plus élevée sur les ECU et ont des contraintes de temps-réel dures et souples, d'où le besoin d’une approche unifiée traitant les deux types de contraintes. Les architectures multi-cœur permettent d'intégrer plusieurs niveaux de criticité de sureté sur la même plate-forme. De telles applications ont été conçues à l'aide d'approches statiques; cependant, les approches dites statiques ne sont plus réalisables dans des environnements très dynamiques en raison de la complexité croissante et les contraintes de coûts strictes, d’où la nécessite des solutions plus souples. Cela signifie que, pour faire face aux environnements dynamiques, un système automobile doit être adaptatif; c'est-à-dire qu'il doit pouvoir adapter sa structure et / ou son comportement à l'exécution en réponse à des changements fréquents dans son environnement. Ces nouvelles exigences ne peuvent être confrontées aux approches actuelles des systèmes et logiciels automobiles. Ainsi, une nouvelle conception de l'architecture électrique / électronique (E / E) d'un véhicule doit être développé. Récemment, l'industrie automobile a convenu de changer la plate-forme AUTOSAR actuelle en "AUTOSAR Adaptive Platform". Cette plate-forme est développée par le consortium AUTOSAR en tant que couche supplémentaire de la plate-forme classique. Il s'agit d'une étude de faisabilité continue basée sur le système d'exploitation POSIX qui utilise une communication orientée service pour intégrer les applications dans le système à tout moment. L'idée principale de cette thèse est de développer de nouveaux concepts d'architecture basés sur l'adaptation pour répondre aux besoins d'une nouvelle architecture E / E pour les véhicules entièrement électriques (VEF) concernant la sureté, la fiabilité et la rentabilité, et les intégrer à AUTOSAR. Nous définissons l'architecture ASLA (Adaptive System Level in AUTOSAR), qui est un cadre qui fournit une solution adaptative pour AUTOSAR. ASLA intègre des fonctions de reconfiguration au niveau des tâches telles que l'addition, la suppression et la migration des tâches dans AUTOSAR. La principale différence entre ASLA et la plate-forme Adaptive AUTOSAR est que ASLA permet d'attribuer des fonctions à criticité mixtes sur le même ECU ainsi que des adaptations bornées temps-réel, tant dis que Adaptive AUTOSAR sépare les fonctions temps réel critiques (fonctionnant sur la plate-forme classique) des fonctions temps réel non critiques (fonctionnant sur la plate-forme adaptative). Pour évaluer la validité de notre architecture proposée, nous fournissons une implémentation prototype de notre architecture ASLA et nous évaluons sa performance à travers des expériences
Modern vehicles have become increasingly computerized to satisfy the more strict safety requirements and to provide better driving experiences. Therefore, the number of electronic control units (ECUs) in modern vehicles has continuously increased in the last few decades. In addition, advanced applications put higher computational demand on ECUs and have both hard and soft timing constraints, hence a unified approach handling both constraints is required. Moreover, economic pressures and multi-core architectures are driving the integration of several levels of safety-criticality onto the same platform. Such applications have been traditionally designed using static approaches; however, static approaches are no longer feasible in highly dynamic environments due to increasing complexity and tight cost constraints, and more flexible solutions are required. This means that, to cope with dynamic environments, an automotive system must be adaptive; that is, it must be able to adapt its structure and/or behaviour at runtime in response to frequent changes in its environment. These new requirements cannot be faced by the current state-of-the-art approaches of automotive software systems. Instead, a new design of the overall Electric/Electronic (E/E) architecture of a vehicle needs to be developed. Recently, the automotive industry agreed upon changing the current AUTOSAR platform to the “AUTOSAR Adaptive Platform”. This platform is being developed by the AUTOSAR consortium as an additional product to the current AUTOSAR classic platform. This is an ongoing feasibility study based on the POSIX operating system and uses service-oriented communication to integrate applications into the system at any desired time. The main idea of this thesis is to develop novel architecture concepts based on adaptation to address the needs of a new E/E architecture for Fully Electric Vehicles (FEVs) regarding safety, reliability and cost-efficiency, and integrate these in AUTOSAR. We define the ASLA (Adaptive System Level in AUTOSAR) architecture, which is a framework that provides an adaptive solution for AUTOSAR. ASLA incorporates tasks-level reconfiguration features such as addition, deletion and migration of tasks in AUTOSAR. The main difference between ASLA and the Adaptive AUTOSAR platform is that ASLA enables the allocation of mixed critical functions on the same ECU as well as time-bound adaptations while adaptive AUTOSAR separates critical, hard real-time functions (running on the classic platform) from non-critical/soft-real-time functions (running on the adaptive platform). To assess the validity of our proposed architecture, we provide an early prototype implementation of ASLA and evaluate its performance through experiments
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Philipp, François [Verfasser], Manfred [Akademischer Betreuer] Glesner, Christian [Akademischer Betreuer] Hochberger, and Eduardo de la [Akademischer Betreuer] Torre. "Runtime Hardware Reconfiguration in Wireless Sensor Networks for Condition Monitoring / François Philipp. Betreuer: Manfred Glesner ; Christian Hochberger ; Eduardo de la Torre." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2014. http://d-nb.info/1110902972/34.

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Oliveira, Neto Inael Rodrigues de. "Síntese de requisitos de segurança para internet das coisas baseada em modelos em tempo de execução." Universidade Federal de Goiás, 2015. http://repositorio.bc.ufg.br/tede/handle/tede/5185.

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Submitted by Cláudia Bueno (claudiamoura18@gmail.com) on 2016-01-29T14:17:13Z No. of bitstreams: 2 Dissertação - Inael Rodrigues de Oliveira Neto - 2015.pdf: 3158226 bytes, checksum: 9d8ebb3f5b3305532b92d7e59da8184e (MD5) license_rdf: 23148 bytes, checksum: 9da0b6dfac957114c6a7714714b86306 (MD5)
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The Internet of Things (IoT) connects the Internet all kinds of “things” or “smart objects” such as devices, sensors, actuators, mobile phones, home appliances, cars and even furniture. IIoT is characterized by the ubiquity and dynamism of its environment and connected objects. Thus, the environment of the IoT is highly volatile and heterogeneous as it counts with the presence of different objects able to interact and to cooperate with each other over the Internet. While Smart Objects become more ubiquitous, there is growing uncertainty about the environment, which contributes to a greater appearance of security threats not foreseen in the design phase. This thesis presents a solution that aims to ensure flexibility by allowing the safety requirements to be changed at runtime by the user, systematically reflecting these changes to the security settings for objects connected to the IoT. Therefore, this work presents an architecture of middleware and implementation of an algorithm for assessment requirements and security reconfiguration as well as its evaluation. In addition, this work presents a domain-specific modeling language using models@runtime for specifying the user’s security requirements. About the contributions of this work, we can mention the proposed architecture of middleware, a requirements synthesis algorithm for reconfiguration of security at runtime, a security requirement modeling language, the application of models@runtime approach for reconfiguration of security and the construction of a metamodel for capturing application security aspects running on devices in the IoT.
A Internet das Coisas (IoT) conecta na Internet todo tipo de coisas ou objetos inteligentes, tais como dispositivos, sensores, atuadores, telefones celulares, eletrodomésticos, carros e até mesmo móveis. Ela caracteriza-se pela ubiquidade e dinamismo do seu ambiente e objetos conectados. Com isso, o ambiente da IoT é altamente volátil e heterogêneo, pois ele conta com a presença de diferentes objetos capazes de interagir e cooperar uns com os outros através da Internet. Ao passo que objetos inteligentes se tornam mais ubíquos, há uma crescente incerteza sobre o ambiente, o que contribui com um maior surgimento de ameaças de segurança não previstas na fase de projeto. Esta dissertação apresenta uma solução que objetiva garantir flexibilidade nos requisitos de segurança para serem alterados pelo usuário em tempo de execução e refletir sistematicamente sobre essas mudanças nas configurações de segurança em objetos conectados na IoT. Para isso, este trabalho apresenta uma arquitetura de middleware e a implementação de um algoritmo para avaliação de requisitos e reconfiguração da segurança. Além disso, este trabalho apresenta uma linguagem de modelagem de domínio específico usando models@ runtime para especificação dos requisitos de segurança do usuário. Entre as contribuições deste trabalho, podemos citar a proposta de arquitetura de middleware, um algoritmo de síntese de requisitos para reconfiguração da segurança em tempo de execução, a linguagem de modelagem de requisitos de segurança, a aplicação da abordagem de modelos em tempo de execução para reconfiguração da segurança e a construção de um metamodelo que captura de aspectos de segurança de aplicações executando em dispositivos na IoT.
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Books on the topic "Runtime Reconfiguration"

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Papp, Zoltan, and George Exarchakos, eds. Runtime Reconfiguration in Networked Embedded Systems. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-0715-6.

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Papp, Zoltan, and George Exarchakos. Runtime Reconfiguration in Networked Embedded Systems: Design and Testing Practices. Springer, 2016.

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Papp, Zoltan, and George Exarchakos. Runtime Reconfiguration in Networked Embedded Systems: Design and Testing Practices. Springer, 2018.

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Papp, Zoltan, and George Exarchakos. Runtime Reconfiguration in Networked Embedded Systems: Design and Testing Practices. Springer, 2016.

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Book chapters on the topic "Runtime Reconfiguration"

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Bhatia, Dinesh, Parivallal Kannan, Kuldeep S. Simha, and Karthikeya M. Gajjala Purna. "REACT: Reactive environment for runtime reconfiguration." In Lecture Notes in Computer Science, 209–17. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/bfb0055248.

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Kirischian, Lev. "RCS Architecture Configuration and Runtime Reconfiguration." In Reconfigurable Computing Systems Engineering, 187–214. Boca Raton : Taylor & Francis Group, 2016.: CRC Press, 2017. http://dx.doi.org/10.1201/9781315374697-8.

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de Filho, Julio Oliveira, Teus Vogel, and Jan de Gier. "Runtime Services and Tooling for Reconfiguration." In Internet of Things, 69–92. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-0715-6_3.

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Yskout, Koen, Olivier-Nathanael Ben David, Riccardo Scandariato, and Benoit Baudry. "Requirements-Driven Runtime Reconfiguration for Security." In Communications in Computer and Information Science, 25–33. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-28033-7_3.

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Ciraci, Selim, Pim van den Broek, and Mehmet Akşit. "Verifying Runtime Reconfiguration Requirements on UML Models." In Views on Evolvability of Embedded Systems, 209–25. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9849-8_13.

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Rehák, Martin, Eugen Staab, Volker Fusenig, Michal Pěchouček, Martin Grill, Jan Stiborek, Karel Bartoš, and Thomas Engel. "Runtime Monitoring and Dynamic Reconfiguration for Intrusion Detection Systems." In Lecture Notes in Computer Science, 61–80. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-04342-0_4.

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Bos, Herbert, and Bart Samwel. "The OKE Corral: Code Organisation and Reconfiguration at Runtime Using Active Linking." In Active Networks, 32–47. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-36199-5_3.

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Bhardwaj, Nikita, and Peter Liggesmeyer. "A Runtime Risk Assessment Concept for Safe Reconfiguration in Open Adaptive Systems." In Lecture Notes in Computer Science, 309–16. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66284-8_26.

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Wisniewski, Lukasz. "Seamless Reconfiguration of the Industrial Network System." In New methods to engineer and seamlessly reconfigure time triggered Ethernet based systems during runtime based on the PROFINET IRT example, 125–47. Berlin, Heidelberg: Springer Berlin Heidelberg, 2017. http://dx.doi.org/10.1007/978-3-662-54650-5_5.

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Göhringer, Diana, and Jürgen Becker. "New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems Through Dynamic and Partial Reconfiguration: The RAMPSoC Approach." In Lecture Notes in Electrical Engineering, 335–46. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-1488-5_20.

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Conference papers on the topic "Runtime Reconfiguration"

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McDonald, E. J. "Runtime FPGA Partial Reconfiguration." In 2008 IEEE Aerospace Conference. IEEE, 2008. http://dx.doi.org/10.1109/aero.2008.4526368.

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2

Pionteck, Thilo, Steffen Sammann, and Carsten Albrecht. "Optimizing Runtime Reconfiguration Decisions." In 2010 IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing (EUC) (Co-Located with CSE 2010). IEEE, 2010. http://dx.doi.org/10.1109/euc.2010.16.

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Priesterjahn, Claudia, Christian Heinzemann, Wilhelm Schafer, and Matthias Tichy. "Runtime safety analysis for safe reconfiguration." In 2012 10th IEEE International Conference on Industrial Informatics (INDIN). IEEE, 2012. http://dx.doi.org/10.1109/indin.2012.6300900.

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4

Lee, K., and G. Coulson. "Supporting Runtime Reconfiguration on Network Processors." In 20th International Conference on Advanced Information Networking and Applications - Volume 1 (AINA'06). IEEE, 2006. http://dx.doi.org/10.1109/aina.2006.319.

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5

Damschen, Marvin, Lars Bauer, and Jorg Henkel. "WCET Guarantees for Opportunistic Runtime Reconfiguration." In 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2019. http://dx.doi.org/10.1109/iccad45719.2019.8942065.

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6

Hasan, Muhammad Z., and Sotirios G. Ziavras. "Runtime Partial Reconfiguration for Embedded Vector Processors." In Fourth International Conference on Information Technology (ITNG'07). IEEE, 2007. http://dx.doi.org/10.1109/itng.2007.170.

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7

Jacob, Arpith C., Jeremy D. Buhler, and Roger D. Chamberlain. "Optimal runtime reconfiguration strategies for systolic arrays." In 2009 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2009. http://dx.doi.org/10.1109/fpl.2009.5272515.

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8

Loubach, Denis S. "A runtime reconfiguration design targeting avionics systems." In 2016 IEEE/AIAA 35th Digital Avionics Systems Conference (DASC). IEEE, 2016. http://dx.doi.org/10.1109/dasc.2016.7778089.

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9

Rahmatian, Mehryar, Hessam Kooti, Ian G. Harris, and Elaheh Bozorgzadeh. "Adaptable intrusion detection using partial runtime reconfiguration." In 2012 IEEE 30th International Conference on Computer Design (ICCD 2012). IEEE, 2012. http://dx.doi.org/10.1109/iccd.2012.6378633.

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10

Paul, Kolin, Joel Porquet, and Josep Llosa. "Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration." In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). IEEE, 2007. http://dx.doi.org/10.1109/dsd.2007.4341487.

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