Dissertations / Theses on the topic 'Runtime Reconfiguration'

Partial reconfiguration is a unique capability provided by several Field Programmable Gate Array (FPGA) vendors recently, which involves altering part of the programmed design within an SRAM-based FPGA at run-time. In this dissertation, a Multilayer Runtime Reconfiguration Architecture (MRRA) is developed, evaluated, and refined for Autonomous Runtime Partial Reconfiguration of FPGA devices. Under the proposed MRRA paradigm, FPGA configurations can be manipulated at runtime using on-chip resources. Operations are partitioned into Logic, Translation, and Reconfiguration layers along with a standardized set of Application Programming Interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. An MRRA mapping theory is developed to link the general logic function and area allocation information to the device related physical configuration level data by using mathematical data structure and physical constraints. In certain scenarios, configuration bit stream data can be read and modified directly for fast operations, relying on the use of similar logic functions and common interconnection resources for communication. A corresponding logic control flow is also developed to make the entire process autonomous. Several prototype MRRA systems are developed on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Area, speed and power optimization techniques are developed based on the developed Xilinx prototype. Evaluations and analysis of these prototype and techniques are performed on a number of benchmark and hashing algorithm case studies. The results indicate that based on a variety of test benches, up to 70% reduction in the resource utilization, up to 50% improvement in power consumption, and up to 10 times increase in run-time performance are achieved using the developed architecture and approaches compared with Xilinx baseline reconfiguration flow. Finally, a Genetic Algorithm (GA) for a FPGA fault tolerance case study is evaluated as a ultimate high-level application running on this architecture. It demonstrated that this is a hardware and software infrastructure that enables an FPGA to dynamically reconfigure itself efficiently under the control of a soft microprocessor core that is instantiated within the FPGA fabric. Such a system contributes to the observed benefits of intelligent control, fast reconfiguration, and low overhead.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Engineering PhD

The integration of miniaturized heterogeneous electronic components has enabled the deployment of tiny sensing platforms empowered by wireless connectivity known as wireless sensor networks. Thanks to an optimized duty-cycled activity, the energy consumption of these battery-powered devices can be reduced to a level where several years of operation is possible. However, the processing capability of currently available wireless sensor nodes does not scale well with the observation of phenomena requiring a high sampling resolution. The large amount of data generated by the sensors cannot be handled efficiently by low-power wireless communication protocols without a preliminary filtering of the information relevant for the application. For this purpose, energy-efficient, flexible, fast and accurate processing units are required to extract important features from the sensor data and relieve the operating system from computationally demanding tasks. Reconfigurable hardware is identified as a suitable technology to fulfill these requirements, balancing implementation flexibility with performance and energy-efficiency. While both static and dynamic power consumption of field programmable gate arrays has often been pointed out as prohibitive for very-low-power applications, recent programmable logic chips based on non-volatile memory appear as a potential solution overcoming this constraint. This thesis first verifies this assumption with the help of a modular sensor node built around a field programmable gate array based on Flash technology. Short and autonomous duty-cycled operation combined with hardware acceleration efficiently drop the energy consumption of the device in the considered context. However, Flash-based devices suffer from restrictions such as long configuration times and limited resources, which reduce their suitability for complex processing tasks. A template of a dynamically reconfigurable architecture built around coarse-grained reconfigurable function units is proposed in a second part of this work to overcome these issues. The module is conceived as an overlay of the sensor node FPGA increasing the implementation flexibility and introducing a standardized programming model. Mechanisms for virtual reconfiguration tailored for resource-constrained systems are introduced to minimize the overhead induced by this genericity. The definition of this template architecture leaves room for design space exploration and application- specific customization. Nevertheless, this aspect must be supported by appropriate design tools which facilitate and automate the generation of low-level design files. For this purpose, a software tool is introduced to graphically configure the architecture and operation of the hardware accelerator. A middleware service is further integrated into the wireless sensor network operating system to bridge the gap between the hardware and the design tools, enabling remote reprogramming and scheduling of the hardware functionality at runtime. At last, this hardware and software toolchain is applied to real-world wireless sensor network deployments in the domain of condition monitoring. This category of applications often require the complex analysis of signals in the considered range of sampling frequencies such as vibrations or electrical currents, making the proposed system ideally suited for the implementation. The flexibility of the approach is demonstrated by taking examples with heterogeneous algorithmic specifications. Different data processing tasks executed by the sensor node hardware accelerator are modified at runtime according to application requests.

Due to their programmable nature, Field Programmable Gate Arrays (FPGAs) offer a good test environment for reconfigurable systems. FPGAs can be reconfigured during the operation with changing demands. This feature, known as Runtime Reconfiguration (RTR), can be used to speed-up computations and reduce system cost. Moreover, it can be used in a wide range of applications such as adaptable hardware, fault tolerant architectures. This thesis is mostly concentrated on the runtime reconfigurable architectures. Critical properties of runtime reconfigurable architectures are examined. As a case study, a Triple Modular Redundant (TMR) system has been implemented on a runtime reconfigurable FPGA. The runtime reconfigurable structure increases the system reliability against faults. Especially, the weakness of SRAM based FPGAs against Single Event Upsets (SEUs) is eliminated by the designed system. Besides, the system can replace faulty elements with non-faulty elements during the operation. These features of the developed architecture provide extra safety to the system also prolong the life of the FPGA device without interrupting the whole system.

Les véhicules modernes sont de plus en plus informatisés pour satisfaire les exigences de sureté les plus strictes et pour fournir de meilleures expériences de conduite. Par conséquent, le nombre d'unités de contrôle électronique (ECU) dans les véhicules modernes a augmenté de façon continue au cours des dernières années. En outre, les applications à calcul complexe offrent une demande de calcul plus élevée sur les ECU et ont des contraintes de temps-réel dures et souples, d'où le besoin d’une approche unifiée traitant les deux types de contraintes. Les architectures multi-cœur permettent d'intégrer plusieurs niveaux de criticité de sureté sur la même plate-forme. De telles applications ont été conçues à l'aide d'approches statiques; cependant, les approches dites statiques ne sont plus réalisables dans des environnements très dynamiques en raison de la complexité croissante et les contraintes de coûts strictes, d’où la nécessite des solutions plus souples. Cela signifie que, pour faire face aux environnements dynamiques, un système automobile doit être adaptatif; c'est-à-dire qu'il doit pouvoir adapter sa structure et / ou son comportement à l'exécution en réponse à des changements fréquents dans son environnement. Ces nouvelles exigences ne peuvent être confrontées aux approches actuelles des systèmes et logiciels automobiles. Ainsi, une nouvelle conception de l'architecture électrique / électronique (E / E) d'un véhicule doit être développé. Récemment, l'industrie automobile a convenu de changer la plate-forme AUTOSAR actuelle en "AUTOSAR Adaptive Platform". Cette plate-forme est développée par le consortium AUTOSAR en tant que couche supplémentaire de la plate-forme classique. Il s'agit d'une étude de faisabilité continue basée sur le système d'exploitation POSIX qui utilise une communication orientée service pour intégrer les applications dans le système à tout moment. L'idée principale de cette thèse est de développer de nouveaux concepts d'architecture basés sur l'adaptation pour répondre aux besoins d'une nouvelle architecture E / E pour les véhicules entièrement électriques (VEF) concernant la sureté, la fiabilité et la rentabilité, et les intégrer à AUTOSAR. Nous définissons l'architecture ASLA (Adaptive System Level in AUTOSAR), qui est un cadre qui fournit une solution adaptative pour AUTOSAR. ASLA intègre des fonctions de reconfiguration au niveau des tâches telles que l'addition, la suppression et la migration des tâches dans AUTOSAR. La principale différence entre ASLA et la plate-forme Adaptive AUTOSAR est que ASLA permet d'attribuer des fonctions à criticité mixtes sur le même ECU ainsi que des adaptations bornées temps-réel, tant dis que Adaptive AUTOSAR sépare les fonctions temps réel critiques (fonctionnant sur la plate-forme classique) des fonctions temps réel non critiques (fonctionnant sur la plate-forme adaptative). Pour évaluer la validité de notre architecture proposée, nous fournissons une implémentation prototype de notre architecture ASLA et nous évaluons sa performance à travers des expériences
Modern vehicles have become increasingly computerized to satisfy the more strict safety requirements and to provide better driving experiences. Therefore, the number of electronic control units (ECUs) in modern vehicles has continuously increased in the last few decades. In addition, advanced applications put higher computational demand on ECUs and have both hard and soft timing constraints, hence a unified approach handling both constraints is required. Moreover, economic pressures and multi-core architectures are driving the integration of several levels of safety-criticality onto the same platform. Such applications have been traditionally designed using static approaches; however, static approaches are no longer feasible in highly dynamic environments due to increasing complexity and tight cost constraints, and more flexible solutions are required. This means that, to cope with dynamic environments, an automotive system must be adaptive; that is, it must be able to adapt its structure and/or behaviour at runtime in response to frequent changes in its environment. These new requirements cannot be faced by the current state-of-the-art approaches of automotive software systems. Instead, a new design of the overall Electric/Electronic (E/E) architecture of a vehicle needs to be developed. Recently, the automotive industry agreed upon changing the current AUTOSAR platform to the “AUTOSAR Adaptive Platform”. This platform is being developed by the AUTOSAR consortium as an additional product to the current AUTOSAR classic platform. This is an ongoing feasibility study based on the POSIX operating system and uses service-oriented communication to integrate applications into the system at any desired time. The main idea of this thesis is to develop novel architecture concepts based on adaptation to address the needs of a new E/E architecture for Fully Electric Vehicles (FEVs) regarding safety, reliability and cost-efficiency, and integrate these in AUTOSAR. We define the ASLA (Adaptive System Level in AUTOSAR) architecture, which is a framework that provides an adaptive solution for AUTOSAR. ASLA incorporates tasks-level reconfiguration features such as addition, deletion and migration of tasks in AUTOSAR. The main difference between ASLA and the Adaptive AUTOSAR platform is that ASLA enables the allocation of mixed critical functions on the same ECU as well as time-bound adaptations while adaptive AUTOSAR separates critical, hard real-time functions (running on the classic platform) from non-critical/soft-real-time functions (running on the adaptive platform). To assess the validity of our proposed architecture, we provide an early prototype implementation of ASLA and evaluate its performance through experiments

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The Internet of Things (IoT) connects the Internet all kinds of “things” or “smart objects” such as devices, sensors, actuators, mobile phones, home appliances, cars and even furniture. IIoT is characterized by the ubiquity and dynamism of its environment and connected objects. Thus, the environment of the IoT is highly volatile and heterogeneous as it counts with the presence of different objects able to interact and to cooperate with each other over the Internet. While Smart Objects become more ubiquitous, there is growing uncertainty about the environment, which contributes to a greater appearance of security threats not foreseen in the design phase. This thesis presents a solution that aims to ensure flexibility by allowing the safety requirements to be changed at runtime by the user, systematically reflecting these changes to the security settings for objects connected to the IoT. Therefore, this work presents an architecture of middleware and implementation of an algorithm for assessment requirements and security reconfiguration as well as its evaluation. In addition, this work presents a domain-specific modeling language using models@runtime for specifying the user’s security requirements. About the contributions of this work, we can mention the proposed architecture of middleware, a requirements synthesis algorithm for reconfiguration of security at runtime, a security requirement modeling language, the application of models@runtime approach for reconfiguration of security and the construction of a metamodel for capturing application security aspects running on devices in the IoT.
A Internet das Coisas (IoT) conecta na Internet todo tipo de coisas ou objetos inteligentes, tais como dispositivos, sensores, atuadores, telefones celulares, eletrodomésticos, carros e até mesmo móveis. Ela caracteriza-se pela ubiquidade e dinamismo do seu ambiente e objetos conectados. Com isso, o ambiente da IoT é altamente volátil e heterogêneo, pois ele conta com a presença de diferentes objetos capazes de interagir e cooperar uns com os outros através da Internet. Ao passo que objetos inteligentes se tornam mais ubíquos, há uma crescente incerteza sobre o ambiente, o que contribui com um maior surgimento de ameaças de segurança não previstas na fase de projeto. Esta dissertação apresenta uma solução que objetiva garantir flexibilidade nos requisitos de segurança para serem alterados pelo usuário em tempo de execução e refletir sistematicamente sobre essas mudanças nas configurações de segurança em objetos conectados na IoT. Para isso, este trabalho apresenta uma arquitetura de middleware e a implementação de um algoritmo para avaliação de requisitos e reconfiguração da segurança. Além disso, este trabalho apresenta uma linguagem de modelagem de domínio específico usando models@ runtime para especificação dos requisitos de segurança do usuário. Entre as contribuições deste trabalho, podemos citar a proposta de arquitetura de middleware, um algoritmo de síntese de requisitos para reconfiguração da segurança em tempo de execução, a linguagem de modelagem de requisitos de segurança, a aplicação da abordagem de modelos em tempo de execução para reconfiguração da segurança e a construção de um metamodelo que captura de aspectos de segurança de aplicações executando em dispositivos na IoT.

Les domaines de recherche actuels, tels que l'informatique ubiquitaire et l'informatique en nuage (cloud computing), considèrent que ces environnements d'exécution sont en changement continue. Les applications dynamiques, où les composants peuvent être ajoutés et supprimés pendant l'exécution, permettent à un logiciel de s'adapter et de s'ajuster à l'évolution des environnements, et de tenir compte de l'évolution du logiciel. Malheureusement, les applications dynamiques soulèvent des questions de conception et de développement qui n'ont pas encore été pleinement explorées.Dans cette thèse, nous montrons que le dynamisme est une préoccupation transversale qui rompt avec un grand nombre d'hypothèses que les développeurs d'applications classiques sont autorisés à prendre. Le dynamisme affecte profondément la conception et développement de logiciels. S'il n'est pas manipulé correctement, le dynamisme peut " silencieusement " corrompre l'application. De plus, l'écriture d'applications dynamiques est complexe et sujette à erreur. Et compte tenu du niveau de complexité et de l'impact du dynamisme sur le processus du développement, le logiciel ne peut pas devenir dynamique sans (de large) modification et le dynamisme ne peut pas être totalement transparent (bien que beaucoup de celui-ci peut souvent être externalisées ou automatisées).Ce travail a pour but d'offrir à l'architecte logiciel le contrôle sur le niveau, la nature et la granularité du dynamisme qui est nécessaire dans les applications dynamiques. Cela permet aux architectes et aux développeurs de choisir les zones de l'application où les efforts de programmation des composants dynamiques seront investis, en évitant le coût et la complexité de rendre tous les composants dynamiques. L'idée est de permettre aux architectes de déterminer l'équilibre entre les efforts à fournir et le niveau de dynamisme requis pour les besoins de l'application.

Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Reconfigurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria.
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering

碩士
國立臺灣大學
資訊網路與多媒體研究所
94
Reconfigurable hardwares can provide multiple functions with low cost and power consumption. Field Programmable Gate Array (FPGA), a form of reconfigurable hardware, is developing rapidly to handle high speed and complex applications. SRAM-based FPGA can be reconfigured during runtime to provide functionalities as they are required, thus reducing cost and power assumption. However, the reconfiguration delay time and resource management of FPGA poses new challenges to traditional real-time scheduling algorithms. In order to optimize hardware usage and reconfiguration delay time, the scheduling and resource management on FPGA requires new techniques. In this thesis, we study the constraints of FPGA and propose a template-based approach to reuse hardware resources without compromising performances and violating the reconfiguration deadline constraint. The proposed solution uses offline generated templates to assist the job of generating schedules during runtime.

碩士
國立中央大學
資訊工程研究所
97
As the evolution of the Internet continues, it is possible to share and integrate resources of computers in several different ways. The Internet aggregates all computers over the world as a whole and creates numerous groups of computers with great computing power. People can use them to solve many complicated problems which were considered too hard to be solved. However, those powerful computing resources are usually dynamic. There are often new arrivals and departures of computing nodes and constant changes of the computing resources on the hosts in the network. As a result, a P2P dynamic reconfiguration approach is more appropriate on such a system to achieve load balancing. Thus we can maximize the utilization of the resources in a self-adaptive manner. In this thesis, we propose a P2P, runtime reconfiguration model to judge whether or not a computing entity should migrate to improve overall performance on a given distributed computing environment. In addition to computation-intensive applications, the model also considers data-intensive applications which usually spend much time on I/O transmission. We also introduce the concept of “debt” to prevent a computing entity from frequent, unnecessary migrations which usually result from wrong migration decisions on an unstable computing environment. Our model is extensible: it is possible to add new types of resources as new model parameters because of the symmetry of the model parameters.