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Journal articles on the topic 'Runtime Reconfiguration'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Loukil, Sihem, Slim Kallel, and Mohamed Jmaiel. "Managing Architectural Reconfiguration at Runtime." International Journal of Web Portals 5, no. 1 (January 2013): 55–72. http://dx.doi.org/10.4018/jwp.2013010105.

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Managing dynamic reconfiguration of software systems is a tedious task in the software development because of the substantially increasing need for continuously available systems even at runtime. In particular, the software architecture of dynamically adaptive systems must continuously adapt to varying environmental conditions and user requirements. Therefore, they propose a wide range of possible configurations. The static enumeration of all the possible configurations is a difficult task. Moreover, not all dynamic reconfiguration operations can be foreseen at design time. Some reconfigurations may appear when the system is already deployed. In this context, we propose to combine the Architecture Description Languages and the Aspect-Oriented Software Development paradigm in order to make the dynamic reconfiguration process easier to design, understand and possible to validate. Also, this combination allows to easily evolving the reconfiguration policies even at runtime.

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2

McDonald, Eric. "Runtime FPGA partial reconfiguration." IEEE Aerospace and Electronic Systems Magazine 23, no. 7 (July 2008): 10–15. http://dx.doi.org/10.1109/maes.2008.4579286.

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3

Chen, Wei, Xiaoqiang Qiao, Jun Wei, Hua Zhong, and Tao Huang. "A Virtual Machine Placement and Reconfiguration Framework for Cloud Computing Platforms." International Journal of Adaptive, Resilient and Autonomic Systems 5, no. 2 (April 2014): 1–22. http://dx.doi.org/10.4018/ijaras.2014040101.

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As a rising application paradigm and technology, cloud computing can leverage the efficient pooling of on-demand, self-managed virtual infrastructure. How to maximize the resource utilization and how to reduce the cost of configuration are essential issues in cloud computing. In this paper, the authors propose a framework to achieve these objectives by optimizing VM placement and deciding when and how to perform the VM reconfigurations. The authors leverage the vector arithmetic to model the objective of balancing the multiple resource utilization and propose an optimization method for the static VM placement. Then the authors propose a two-level runtime reconfiguration policy, including the local adjustment and the parallel migration, to minimize the reconfiguration cost. Finally, the authors implement a prototype to validate and evaluate the proposed mechanism with a set of preliminary experiments, which shows that our work can maximize the resource utilization while effectively reducing the cost of the runtime reconfiguration.

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LEE, KEVIN, and GEOFFREY COULSON. "SUPPORTING RUNTIME RECONFIGURATION ON NETWORK PROCESSORS." Journal of Interconnection Networks 07, no. 04 (December 2006): 475–92. http://dx.doi.org/10.1142/s0219265906001818.

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Network Processors (NPs) are set to play a key role in the next generation of networking technology. They have the performance of ASIC-based routers whilst offering a high degree of programmability. However, the programmability potential of NPs can only be realised with appropriate software. In this paper we argue that specialised software to support runtime reconfiguration is needed to fully exploit the potential of NPs. We first justify supporting runtime reconfiguration on NPs by offering real-world scenarios and discussing the issues associated with these. We then demonstrate how runtime reconfiguration can be achieved in practice through a case study of our component-based programming approach on the Intel IXP2400 NP.

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Wildermann, S., J. Angermeier, E. Sibirko, and J. Teich. "Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures." International Journal of Reconfigurable Computing 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/608312.

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By means of partial reconfiguration, parts of the hardware can be dynamically exchanged at runtime. This allows that streaming application running in different modes of the systems can share resources. In this paper, we discuss the architectural issues to design such reconfigurable systems. For being able to reduce reconfiguration time, this paper furthermore proposes a novel algorithm to aggregate several streaming applications into a single representation, called merge graph. The paper also proposes an algorithm to place streaming application at runtime which not only considers the placement and communication constraints, but also allows to place merge tasks. In a case study, we implement the proposed algorithm as runtime support on an FPGA-based system on chip. Furthermore, experiments show that reconfiguration time can be considerably reduced by applying our approach.

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Puranik, Dipti Anil. "Runtime Reconfiguration of FPGA for Biomedical Applications." Indian Journal of Science and Technology 9, no. 1 (January 20, 2016): 1–15. http://dx.doi.org/10.17485/ijst/2016/v9i47/106429.

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Ali, M. Mubarak, R. Arun, and S. Saravanan. "Runtime Partial Reconfiguration of FPGAs for DSP Applications." Procedia Engineering 30 (2012): 514–18. http://dx.doi.org/10.1016/j.proeng.2012.01.892.

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Niu, Xinyu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu, and Oliver Pell. "Automating Elimination of Idle Functions by Runtime Reconfiguration." ACM Transactions on Reconfigurable Technology and Systems 8, no. 3 (May 19, 2015): 1–28. http://dx.doi.org/10.1145/2700415.

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Bingxiong Xu and D. H. Albonesi. "Runtime reconfiguration techniques for efficient general-purpose computation." IEEE Design & Test of Computers 17, no. 1 (2000): 42–52. http://dx.doi.org/10.1109/54.825676.

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10

Purnaprajna, Madhura, Mario Porrmann, Ulrich Rueckert, Michael Hussmann, Michael Thies, and Uwe Kastens. "Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis." ACM Transactions on Reconfigurable Technology and Systems 3, no. 3 (September 2010): 1–25. http://dx.doi.org/10.1145/1839480.1839487.

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11

Taher, Mohamed, and Tarek El-Ghazawi. "Virtual Configuration Management: A Technique for Partial Runtime Reconfiguration." IEEE Transactions on Computers 58, no. 10 (October 2009): 1398–410. http://dx.doi.org/10.1109/tc.2009.81.

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12

El-Araby, Esam, Ivan Gonzalez, and Tarek El-Ghazawi. "Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing." ACM Transactions on Reconfigurable Technology and Systems 1, no. 4 (January 2009): 1–23. http://dx.doi.org/10.1145/1462586.1462590.

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13

Liu, Shaoshan, Richard Neil Pittman, Alessandro Forin, and Jean-Luc Gaudiot. "Minimizing the runtime partial reconfiguration overheads in reconfigurable systems." Journal of Supercomputing 61, no. 3 (July 22, 2011): 894–911. http://dx.doi.org/10.1007/s11227-011-0657-6.

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14

Dickens, Michael, J. Nicholas Laneman, and Brian P. Dunn. "Seamless Dynamic Runtime Reconfiguration in a Software-Defined Radio." Journal of Signal Processing Systems 69, no. 1 (December 30, 2011): 87–94. http://dx.doi.org/10.1007/s11265-011-0645-3.

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15

Oreizy, P., and R. N. Taylor. "On the role of software architectures in runtime system reconfiguration." IEE Proceedings - Software 145, no. 5 (1998): 137. http://dx.doi.org/10.1049/ip-sen:19982296.

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16

Liu, Shaoshan, Richard Neil Pittman, Alessandro Forin, and Jean-Luc Gaudiot. "Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systems." ACM Transactions on Embedded Computing Systems 12, no. 3 (March 10, 2013): 1–21. http://dx.doi.org/10.1145/2442116.2442122.

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17

Lam, Siew-Kei, Christopher T. Clarke, and Thambipillai Srikanthan. "Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration." ACM Transactions on Reconfigurable Technology and Systems 7, no. 3 (August 2014): 1–15. http://dx.doi.org/10.1145/2655240.

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18

Vaquero, Luis M., Daniel Morán, Fermín Galán, and Jose M. Alcaraz-Calero. "Towards Runtime Reconfiguration of Application Control Policies in the Cloud." Journal of Network and Systems Management 20, no. 4 (August 8, 2012): 489–512. http://dx.doi.org/10.1007/s10922-012-9251-3.

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19

Zhao, Weisheng, Eric Belhaire, Claude Chappert, and Pascale Mazoyer. "Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit." ACM Transactions on Embedded Computing Systems 9, no. 2 (October 2009): 1–16. http://dx.doi.org/10.1145/1596543.1596548.

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20

Tang, Feng, Geng Sheng Rao, Qiang Chen, and Ping Zhang. "Open Robot Control Platform Based on LSOA." Applied Mechanics and Materials 341-342 (July 2013): 719–26. http://dx.doi.org/10.4028/www.scientific.net/amm.341-342.719.

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Aims to address the restrictions imposed by tranditional robot Control system development approach such as close structure, function immobility, lack of reconfiguration at run time, hard to guarantee. a lightweight service-oriented architectures (LSOA) for robot control system is proposed. The main features of this architecture include central control mode, message-based interaction and configuration system based on embedded database. This architecture provides good supports for runtime reconfiguration, and allows integrating different components with the aid of a configuration system. The experiment indicates that the LSOA approach can improve the flexibility, reconfiguration and agility of the system.

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21

Shafique, Ayesha, Guo Cao, Muhammad Aslam, Muhammad Asad, and Dengpan Ye. "Application-Aware SDN-Based Iterative Reconfigurable Routing Protocol for Internet of Things (IoT)." Sensors 20, no. 12 (June 22, 2020): 3521. http://dx.doi.org/10.3390/s20123521.

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The central intelligence offered by Software Defined Networking (SDN) promise the smart and reliable reconfiguration which enables the scalability of dynamic enterprise networks. The decoupled forwarding plane and control plane of SDN infrastructure is a key feature that supports the SDN controller to extract the physical network topology information at runtime to formulate network reconfigurations. This SDN-based network reconfiguration enables application-aware routing capability for Internet of Thing (IoT). However, these IoT enabled SDN-based routing protocols face some performance limitations in iterative reconfiguration process due to complete centralized path selection mechanism To this end, in this paper, we propose SDN-Based Application-aware Distributed adaptive Flow Iterative Reconfiguring (SADFIR) routing protocol. The proposed routing protocol enables the distributed SDN iterative solver controller to maintain the load-balancing between flow reconfiguration and flow allocation cost. In particular, the proposed routing protocol of SADFIR implements multiple SDN controllers that collaborate with network devices at forwarding plane to develop appropriate clustering strategy for routing the sensed information. This distributed SDN controllers are assisted to clustering topology that successfully map the residual network resources and also enable unique multi-hop application-aware data transmission. In addition, the proposed SADFIR monitor the iterative reconfiguration settings according to the network traffic of heterogeneity-aware network devices. The simulation experiments are conducted in comparison with the state-of-the-art routing protocols which demonstrates that SADFIR is heterogeneity-aware which is able to adopt the different scales of network with maximum network lifetime.

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22

Ji-Wei, Liu, and Mao Xin-Jun. "Towards Dynamic Evolution of Runtime Variability Based on Computational Reflection." International Journal of Software Engineering and Knowledge Engineering 28, no. 03 (March 2018): 259–85. http://dx.doi.org/10.1142/s0218194018500092.

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Given the frequently changing nature of the user requirements and environments in software systems, runtime variability in today’s software systems should be capable of evolving during execution. Computational reflection is required to facilitate accessing and customizing runtime variability during this evolution process. However, realizing this computational reflection includes various practical complexities since the runtime variability is typically neither explicitly represented in software systems nor changeable during runtime. To address this problem, this paper proposes a software architecture to support computational reflection of runtime variability, along with a corresponding causal-connection mechanism to realize the introspection and intercession (i.e. representing runtime variability model, and adding, removing, replacing variability elements and their relations). The proposed software architecture consists of a meta level that represents runtime variability model using objectification, and a base level that organizes and manipulates the implementation of variability elements via reconfiguration. The causal-connection mechanism integrated in our proposed model is designed to synchronize the representation and the implementation. Further, we developed a Reflective Runtime Variability Framework (R2VF) to support the development and operation of the systems with the reflection of runtime variability. The effectiveness and applicability of our approach has been evaluated by applying R2VF to Personal Data Resource Network.

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23

Wirkus, Malte, Sascha Arnold, and Elmar Berghöfer. "Online Reconfiguration of Distributed Robot Control Systems for Modular Robot Behavior Implementation." Journal of Intelligent & Robotic Systems 100, no. 3-4 (September 18, 2020): 1283–308. http://dx.doi.org/10.1007/s10846-020-01234-9.

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AbstractThe use of autonomous robots in areas that require executing a broad range of different tasks is currently hampered by the high complexity of the software that adapts the robot controller to different situations the robot would face. Current robot software frameworks facilitate implementing controllers for individual tasks with some variability, however, their possibilities for adapting the controllers at runtime are very limited and don’t scale with the requirements of a highly versatile autonomous robot. With the software presented in this paper, the behavior of robots is implemented modularly by composing individual controllers, between which it is possible to switch freely at runtime, since the required transitions are calculated automatically. Thereby the software developer is relieved of the task to manually implement and maintain the transitions between different operational modes of the robot, what largely reduces software complexity for larger amounts of different robot behaviors. The software is realized by a model-based development approach. We will present the metamodels enabling the modeling of the controllers as well as the runtime architecture for the management of the controllers on distributed computation hardware. Furthermore, this paper introduces an algorithm that calculates the transitions between two controllers. A series of technical experiments verifies the choice of the underlying middleware and the performance of online controller reconfiguration. A further experiment demonstrates the applicability of the approach to real robotics applications.

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24

Damschen, Marvin, Lars Bauer, and Jorg Henkel. "CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time Systems." IEEE Embedded Systems Letters 9, no. 3 (September 2017): 77–80. http://dx.doi.org/10.1109/les.2017.2714844.

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25

Zhao, Weisheng, Eric Belhaire, Claude Chappert, Bernard Dieny, and Guillaume Prenat. "TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA." ACM Transactions on Reconfigurable Technology and Systems 2, no. 2 (June 2009): 1–19. http://dx.doi.org/10.1145/1534916.1534918.

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26

Wang, Fei, and Jack Jean. "Architecture and operating system support for two-dimensional runtime partial reconfiguration." Journal of Supercomputing 59, no. 2 (June 18, 2010): 610–35. http://dx.doi.org/10.1007/s11227-010-0457-4.

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27

Loubach, Denis. "An analysis of power consumption and performance in runtime hardware reconfiguration." International Journal of Embedded Systems 1, no. 1 (2021): 1. http://dx.doi.org/10.1504/ijes.2021.10035365.

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28

Loubach, Denis S. "An analysis on power consumption and performance in runtime hardware reconfiguration." International Journal of Embedded Systems 14, no. 3 (2021): 277. http://dx.doi.org/10.1504/ijes.2021.116114.

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29

GRANADO-CRIADO, JOSÉ MARÍA, MIGUEL ÁNGEL VEGA-RODRÍGUEZ, JUAN MANUEL SÁNCHEZ-PÉREZ, and JUAN ANTONIO GÓMEZ-PULIDO. "PARALLEL AND RUNTIME RECONFIGURABLE IMPLEMENTATION OF THE IDEA ALGORITHM." Journal of Circuits, Systems and Computers 18, no. 01 (February 2009): 133–50. http://dx.doi.org/10.1142/s0218126609004983.

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Cryptographic algorithms are a fundamental tool nowadays, and information networks continue to grow exponentially every year. Moreover, these algorithms need to be very fast due to the new standards. In order to achieve this characteristic, a good choice is to use FPGAs, which mix the advantages of software flexibility and hardware performance. In this work, we present a super-pipelined and parallel implementation of the IDEA cryptographic algorithm by using partial and dynamic reconfiguration. Our implementation reaches a performance of 26.028 Gb/s, and therefore, it obtains better results than those found in the literature.

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30

Göhringer, Diana, Michael Hübner, Etienne Nguepi Zeutebouo, and Jürgen Becker. "Operating System for Runtime Reconfigurable Multiprocessor Systems." International Journal of Reconfigurable Computing 2011 (2011): 1–16. http://dx.doi.org/10.1155/2011/121353.

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Operating systems traditionally handle the task scheduling of one or more application instances on processor-like hardware architectures. RAMPSoC, a novel runtime adaptive multiprocessor System-on-Chip, exploits the dynamic reconfiguration on FPGAs to generate, start and terminate hardware and software tasks. The hardware tasks have to be transferred to the reconfigurable hardware via a configuration access port. The software tasks can be loaded into the local memory of the respective IP core either via the configuration access port or via the on-chip communication infrastructure (e.g. a Network-on-Chip). Recent-series of Xilinx FPGAs, such as Virtex-5, provide two Internal Configuration Access Ports, which cannot be accessed simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled, e.g. by a special-purpose operating system running on an embedded processor. For that purpose and to handle the relations between temporally and spatially scheduled operations, the novel approach of an operating system is of high importance. This special purpose operating system, called CAP-OS (Configuration Access Port-Operating System), which will be presented in this paper, supports the clients using the configuration port with the services of priority-based access scheduling, hardware task mapping and resource management.

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31

He, Pan, Gang Liu, and Yue Yuan. "An Adaptive Reconfiguration Mechanism for Periodic Software Rejuvenation based on Transient Reliability Analysis." MATEC Web of Conferences 232 (2018): 03045. http://dx.doi.org/10.1051/matecconf/201823203045.

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While software rejuvenation is used to prevent severe software failures, existing researches generally choose the constant-value periodic policy through steady-state reliability optimization. Since the software reliability declines with the execution time, a steady policy either introduces extra overhead or could not guarantee the reliability constraints. So an adaptive mechanism is proposed to reconfigure the software rejuvenation in the runtime. The transient reliability analysis is used to choose an optimal rejuvenation policy which maintains the software reliability for a certain period of time. A dynamic time series is generated for the reconfiguration process and the optimal rejuvenation policy is re-calculated according to the reconfiguration intervals during the software execution. Experimental studies results show that as the execution time increases, the software reliability drops continuously and the optimal rejuvenation interval should be decreased to maintain the same reliability constraints. This mechanism guarantees the software reliability constraint by resetting the optimal rejuvenation policy dynamically according to a reconfiguration interval time series.

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Vera, G. Alonzo, Marios Pattichis, and James Lyke. "A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs." International Journal of Reconfigurable Computing 2011 (2011): 1–19. http://dx.doi.org/10.1155/2011/518602.

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In FPGA embedded systems, designers usually have to make a compromise between numerical precision and logical resources. Scientific computations in particular, usually require highly accurate calculations and are computing intensive. In this context, a designer is left with the task of implementing several arithmetic cores for parallel processing while supporting high numerical precision with finite logical resources. This paper introduces an arithmetic architecture that uses runtime partial reconfiguration to dynamically adapt its numerical precision, without requiring significant additional logical resources. The paper also quantifies the relationship between reduced logical resources and savings in power consumption, which is particularly important for FPGA implementations. Finally, our results show performance benefits when this approach is compared to alternative static solutions within bounds on the reconfiguration rate.

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33

Hanna, Darrin M., and Michael DuChene. "Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration." Microprocessors and Microsystems 31, no. 5 (August 2007): 302–12. http://dx.doi.org/10.1016/j.micpro.2006.10.001.

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34

Vavousis, Alexandros, Andreas Apostolakis, and Mihalis Psarakis. "A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration." Journal of Electronic Testing 29, no. 6 (December 2013): 805–23. http://dx.doi.org/10.1007/s10836-013-5420-x.

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35

Schuck, Christian, Bastian Haetzer, and Jürgen Becker. "Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs." International Journal of Reconfigurable Computing 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/671546.

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Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to support high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in place to generate the desired frequency and to drive the clock networks with different sources, respectively. Currently, almost all designs run at a fixed clock frequency determined statically during design time. Such systems cannot take the full advantage of partial and dynamic self-reconfiguration. Therefore, we introduce a new methodology that allows the implemented hardware to dynamically self-adopt the clock frequency during runtime by reconfiguring the Digital Clock Managers. We also present a method for online speed monitoring which is based on a two-dimensional online routing. The created speed maps of the FPGA area can be used as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given. Further, the tradeoffs for reconfiguration effort using this method are evaluated. Results show the high potential and importance of the distributed dynamic frequency scaling method with little additional overhead.

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36

VADHIYAR, SATHISH S., and JACK J. DONGARRA. "SRS: A FRAMEWORK FOR DEVELOPING MALLEABLE AND MIGRATABLE PARALLEL APPLICATIONS FOR DISTRIBUTED SYSTEMS." Parallel Processing Letters 13, no. 02 (June 2003): 291–312. http://dx.doi.org/10.1142/s0129626403001288.

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The ability to produce malleable parallel applications that can be stopped and reconfigured during the execution can offer attractive benefits for both the system and the applications. The reconfiguration can be in terms of varying the parallelism for the applications, changing the data distributions during the executions or dynamically changing the software components involved in the application execution. In distributed and Grid computing systems, migration and reconfiguration of such malleable applications across distributed heterogeneous sites which do not share common file systems provides flexibility for scheduling and resource management in such distributed environments. The present reconfiguration systems do not support migration of parallel applications to distributed locations. In this paper, we discuss a framework for developing malleable and migratable MPI message-passing parallel applications for distributed systems. The framework includes a user-level checkpointing library called SRS and a runtime support system that manages the checkpointed data for distribution to distributed locations. Our experiments and results indicate that the parallel applications, with instrumentation to SRS library, were able to achieve reconfigurability incurring about 15-35% overhead.

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Mousavi Khaneghah, Ehsan, and Mohsen Sharifi. "AMRC: an algebraic model for reconfiguration of high performance cluster computing systems at runtime." Journal of Supercomputing 67, no. 1 (July 16, 2013): 1–30. http://dx.doi.org/10.1007/s11227-013-0982-z.

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Klus, Holger, and Dirk Niebuhr. "Integrating Sensor Nodes into a Middleware for Ambient Intelligence." International Journal of Ambient Computing and Intelligence 1, no. 4 (October 2009): 1–11. http://dx.doi.org/10.4018/jaci.2009062201.

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The development of infrastructures enabling dynamic and automated composition of IT systems is a big challenge. This paper addresses a new idea of allowing component-based systems to reconfigure themselves. Therefore, the authors propose DAiSI - a Dynamic Adaptive System Infrastructure for dynamic integration of components as well as their reconfiguration during runtime. Thereby, one of the features of the infrastructure is that it is capable of binding components based on their availability. In this paper the authors concentrate on presenting how resource constrained sensor nodes can be integrated into a system using this infrastructure.

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Manzano, Wallace, Valdemar Vicente Graciano Neto, and Elisa Yumi Nakagawa. "Dynamic-SoS: An Approach for the Simulation of Systems-of-Systems Dynamic Architectures." Computer Journal 63, no. 5 (April 12, 2019): 709–31. http://dx.doi.org/10.1093/comjnl/bxz028.

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Abstract Systems-of-Systems (SoS) combine heterogeneous, independent systems to offer complex functionalities for highly dynamic smart applications. Besides their dynamic architecture with continuous changes at runtime, SoS should be reliable and work without interrupting their operation and with no failures that could cause accidents or losses. SoS architectural design should facilitate the prediction of the impact of architectural changes and potential failures due to SoS behavior. However, existing approaches do not support such evaluation. Hence, these systems have been usually built without a proper evaluation of their architecture. This article presents Dynamic-SoS, an approach to predict/anticipate at design time the SoS architectural behavior at runtime to evaluate whether the SoS can sustain their operation. The main contributions of this approach comprise: (i) characterization of the dynamic architecture changes via a set of well-defined operators; (ii) a strategy to automatically include a reconfiguration controller for SoS simulation; and (iii) a means to evaluate architectural configurations that an SoS could assume at runtime, assessing their impact on the viability of the SoS operation. Results of our case study reveal Dynamic-SoS is a promising approach that could contribute to the quality of SoS by enabling prior assessment of its dynamic architecture.

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40

Kosak, Oliver, Constantin Wanninger, Alwin Hoffmann, Hella Ponsar, and Wolfgang Reif. "Multipotent Systems: Combining Planning, Self-Organization, and Reconfiguration in Modular Robot Ensembles." Sensors 19, no. 1 (December 20, 2018): 17. http://dx.doi.org/10.3390/s19010017.

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Mobile multirobot systems play an increasing role in many disciplines. Their capabilities can be used, e.g., to transport workpieces in industrial applications or to support operational forces in search and rescue scenarios, among many others. Depending on the respective application, the hardware design and accompanying software of mobile robots are of various forms, especially for integrating different sensors and actuators. Concerning this design, robots of one system compared to each other can be classified to exclusively be either homogeneous or heterogeneous, both resulting in different system properties. While homogeneously configured systems are known to be robust against failures through redundancy but are highly specialized for specific use cases, heterogeneously designed systems can be used for a broad range of applications but suffer from their specialization, i.e., they can only hardly compensate for the failure of one specialist. Up to now, there has been no known approach aiming to unify the benefits of both these types of system. In this paper, we present our approach to filling this gap by introducing a reference architecture for mobile robots that defines the interplay of all necessary technologies for achieving this goal. We introduce the class of robot systems implementing this architecture as multipotent systems that bring together the benefits of both system classes, enabling homogeneously designed robots to become heterogeneous specialists at runtime. When many of these robots work together, we call the structure of this cooperation an ensemble. To achieve multipotent ensembles, we also integrate reconfigurable and self-descriptive hardware (i.e., sensors and actuators) in this architecture, which can be freely combined to change the capabilities of robots at runtime. Because typically a high degree of autonomy in such systems is a prerequisite for their practical usage, we also present the integration of necessary mechanisms and algorithms for achieving the systems’ multipotency. We already achieved the first results with robots implementing our approach of multipotent systems in real-world experiments as well as in a simulation environment, which we present in this paper.

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Imran, Naveed, and Ronald F. DeMara. "Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input." International Journal of Reconfigurable Computing 2014 (2014): 1–21. http://dx.doi.org/10.1155/2014/279673.

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Distance-Ranked Fault Identification (DRFI)is a dynamic reconfiguration technique which employs runtime inputs to conduct online functional testing of fielded FPGA logic and interconnect resources without test vectors. At design time, a diverse set of functionally identical bitstream configurations are created which utilize alternate hardware resources in the FPGA fabric. An ordering is imposed on the configuration pool as updated by the PageRank indexing precedence. The configurations which utilize permanently damaged resources and hence manifest discrepant outputs, receive lower rank are thus less preferred for instantiation on the FPGA. Results indicate accurate identification of fault-free configurations in a pool of pregenerated bitstreams with a low number of reconfigurations and input evaluations. For MCNC benchmark circuits, the observed reduction in input evaluations is up to 75% when comparing the DRFI technique to unguided evaluation. The DRFI diagnosis method is seen to isolate all 14 healthy configurations from a pool of 100 pregenerated configurations, and thereby offering a 100% isolation accuracy provided the fault-free configurations exist in the design pool. When a complete recovery is not feasible, graceful degradation may be realized which is demonstrated by the PSNR improvement of images processed in a video encoder case study.

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Souza-Júnior, Milton Secundino de, Nelson Souto Rosa, and Fernando Antônio Aires Lins. "An execution environment as a service for adaptive long-running workflows." International Journal of Web Information Systems 17, no. 2 (March 12, 2021): 117–39. http://dx.doi.org/10.1108/ijwis-12-2020-0077.

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Purpose This paper aims to present Long4Cloud (long-running workflows execution environment for cloud), a distributed and adaptive LRW execution environment delivered “as a service” solution. Design/methodology/approach LRWs last for hours, days or even months and their duration open the possibility of changes in business rules, service interruptions or even alterations of formal regulations of the business before the workflow completion. These events can lead to problems such as loss of intermediary results or exhaustion of computational resources used to manage the workflow execution. Existing solutions face those problems by merely allowing the replacement (at runtime) of services associated with activities of the LRW. Findings LONG4Cloud extends the previous works in two main aspects, namely, the inclusion of dynamic reconfiguration capabilities and the adoption of an “as a service” delivery mode. The reconfiguration mechanism uses quiescence principles, data and state management and provides multiple adaptive strategies. Long4Cloud also adopts a scenario-based analysis to decide the adaptation to be performed. Events such as changes in business rules or service failures trigger reconfigurations supported by the environment. These features have been put together in a solution delivered “as a service” that takes advantage of cloud elasticity and allows to better allocate cloud resources to fit into the demands of LRWs. Originality/value The original contribution of Long4Cloud is to incorporate adaptive capabilities into the LRW execution environment as an effective way to handle the specificities of this kind of workflow. Experiments using current data of a Brazilian health insurance company were carried out to evaluate Long4Cloud and show performance gains in the execution of LRWs submitted to the proposed environment.

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Torres, Romina, Rodrigo Salas, Nelly Bencomo, and Hernan Astudillo. "An architecture based on computing with words to support runtime reconfiguration decisions of service-based systems." International Journal of Computational Intelligence Systems 11, no. 1 (2018): 272. http://dx.doi.org/10.2991/ijcis.11.1.21.

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Wang, Jian, and Ying Li. "RDAMS: An Efficient Run-Time Approach for Memory Fault and Hardware Trojans Detection." Information 12, no. 4 (April 14, 2021): 169. http://dx.doi.org/10.3390/info12040169.

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Ensuring the security of IoT devices and chips at runtime has become an urgent task as they have been widely used in human life. Embedded memories are vital components of SoC (System on Chip) in these devices. If they are attacked or incur faults at runtime, it will bring huge losses. In this paper, we propose a run-time detection architecture for memory security (RDAMS) to detect memory threats (fault and Hardware Trojans attack). The architecture consists of a Security Detection Core (SDC) that controls and enforces the detection procedure as a “security brain”, and a memory wrapper (MEM_wrapper) which interacts with memory to assist the detection. We also design a low latency response mechanism to solve the SoC performance degradation caused by run-time detection. A block-based multi-granularity detection approach is proposed to render the design flexible and reduce the cost in implementation using the FPGA’s dynamic partial reconfigurable (DPR) technology, which enables online detection mode reconfiguration according to the requirements. Experimental results show that RDAMS can correctly detect and identify 10 modeled memory faults and two types of Hardware Trojans (HTs) attacks without leading a great performance degradation to the system.

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Meloni, Paolo, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, and Menno Lindwer. "Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper." VLSI Design 2012 (March 29, 2012): 1–16. http://dx.doi.org/10.1155/2012/580584.

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Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

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da Silva, Bruno, An Braeken, Federico Domínguez, and Abdellah Touhafi. "Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network Emulator." International Journal of Reconfigurable Computing 2018 (2018): 1–16. http://dx.doi.org/10.1155/2018/3214679.

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The current Microelectromechanical Systems (MEMS) technology enables the deployment of relatively low-cost wireless sensor networks composed of MEMS microphone arrays for accurate sound source localization. However, the evaluation and the selection of the most accurate and power-efficient network’s topology are not trivial when considering dynamic MEMS microphone arrays. Although software simulators are usually considered, they consist of high-computational intensive tasks, which require hours to days to be completed. In this paper, we present an FPGA-based platform to emulate a network of microphone arrays. Our platform provides a controlled simulated acoustic environment, able to evaluate the impact of different network configurations such as the number of microphones per array, the network’s topology, or the used detection method. Data fusion techniques, combining the data collected by each node, are used in this platform. The platform is designed to exploit the FPGA’s partial reconfiguration feature to increase the flexibility of the network emulator as well as to increase performance thanks to the use of the PCI-express high-bandwidth interface. On the one hand, the network emulator presents a higher flexibility by partially reconfiguring the nodes’ architecture in runtime. On the other hand, a set of strategies and heuristics to properly use partial reconfiguration allows the acceleration of the emulation by exploiting the execution parallelism. Several experiments are presented to demonstrate some of the capabilities of our platform and the benefits of using partial reconfiguration.

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Wannagat, A., and B. Vogel-Heuser. "Increasing Flexibility and Availability of Manufacturing Systems - Dynamic Reconfiguration of Automation Software at Runtime on Sensor Faults." IFAC Proceedings Volumes 41, no. 3 (2008): 278–83. http://dx.doi.org/10.3182/20081205-2-cl-4009.00049.

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Yoshitomi, Hiroyuki. "OrientalHydrocyphon(Coleoptera: Scirtidae: Scirtinae): Seven New Species from Indonesia, Thailand, Malaysia, and India." Psyche: A Journal of Entomology 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/603875.

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Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

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Silva, Vítor, Paulo Pinto, Paulo Cardoso, Jorge Cabral, and Adriano Tavares. "HAL-ASOS Accelerator Model: Evolutive Elasticity by Design." Electronics 10, no. 17 (August 27, 2021): 2078. http://dx.doi.org/10.3390/electronics10172078.

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To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual file system. The proposed HAL-ASOS accelerator model is split into a user-defined Hardware Task and a parameterizable Hardware Kernel with three differentiated transfer channels, aiming to explore distinct BUS technology interfaces and promote the accelerator to a first-class computing unit. This paper focuses on the Hardware Kernel and mainly its microcode control unit, which will leverage the elasticity to naturally evolve with Linux OS through key differentiating capabilities of field programmable gate arrays (FPGAs) when compared to the state of the art. To comply with the evolutive nature of Linux OS, or any Hardware Task incremental features, the proposed model generates page-faults signaling runtime errors that are handled at the kernel level as part of the virtual file system runtime. To evaluate the accelerator model’s programmability and its performance, a client-side application based on the AES 128-bit algorithm was implemented. Experiments demonstrate a flexible design approach in terms of hardware and software reconfiguration and significant performance increases consistent with rising processing demands or clock design frequencies.

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Al-Wattar, Ahmed, Shawki Areibi, and Gary Grewal. "An Efficient Framework for Floor-plan Prediction of Dynamic Runtime Reconfigurable Systems." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 2 (July 1, 2015): 99. http://dx.doi.org/10.11591/ijres.v4.i2.pp99-121.

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<p>Several embedded application domains for reconfigurable systems tend to combine <br />frequent changes with high performance demands of their workloads such as image processing, wearable computing and<br />network processors. Time multiplexing of reconfigurable hardware resources raises a number of new issues, ranging <br />from run-time systems to complex programming models that usually form a Reconfigurable<br />hardware Operating System (ROS). The Operating System performs online task scheduling and handles resource management.<br />There are many challenges in adaptive computing and dynamic reconfigurable systems. One of the major understudied challenges<br />is estimating the required resources in terms of soft cores, Programmable Reconfigurable Regions (PRRs), <br />the appropriate communication infrastructure, and to predict a near optimal layout and floor-plan of the reconfigurable logic fabric. <br />Some of these issues are specific to the application being designed, while others are more general and relate to the underlying run-time environment.<br />Static resource allocation for Run-Time Reconfiguration (RTR) often leads to inferior and unacceptable results. <br />In this paper, we present a novel adaptive and dynamic methodology, based on a Machine Learning approach, for predicting and<br />estimating the necessary resources for an application based on past historical information.<br />An important feature of the proposed methodology is that the system is able to learn and generalize and, therefore, is expected to improve <br />its accuracy over time. The goal of the entire process is to extract useful hidden knowledge from the data. This knowledge is the prediction <br />and estimation of the necessary resources for an unknown or not previously seen application.<br /><br /></p>

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