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Journal articles on the topic 'Scalable Performance'

Author: Grafiati

Published: 5 June 2025

Last updated: 12 July 2025

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1

J Mounika K, Balasirisha. "High Performance and Scalable Microservices Architecture using Kubernetes." International Journal of Science and Research (IJSR) 12, no. 1 (2023): 85–90. http://dx.doi.org/10.21275/sr221229142739.

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2

Tao, Can, He Yanmin, and Zhu Weile. "High performance scalable image coding." Journal of Systems Engineering and Electronics 18, no. 4 (2007): 795–800. http://dx.doi.org/10.1016/s1004-4132(08)60022-5.

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3

Pauer, Eric K. "High Performance Scalable Computing Performance Modelling Using Ptolemy." International Journal of Modelling and Simulation 19, no. 4 (1999): 341–51. http://dx.doi.org/10.1080/02286203.1999.11760433.

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4

Giannakakis, Panagiotis, Panagiotis Laskaridis, Theoklis Nikolaidis, and Anestis I. Kalfas. "Toward a Scalable Propeller Performance Map." Journal of Propulsion and Power 31, no. 4 (2015): 1073–82. http://dx.doi.org/10.2514/1.b35498.

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5

MOTLAGH, BAHMAN S., and RONALD F. DeMARA. "PERFORMANCE OF SCALABLE SHARED-MEMORY ARCHITECTURES." Journal of Circuits, Systems and Computers 10, no. 01n02 (2000): 1–22. http://dx.doi.org/10.1142/s0218126600000068.

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Analytical models were developed and simulations of memory latency were performed for Uniform Memory Access (UMA), Non-Uniform Memory Access (NUMA), Local-Remote-Global (LRG), and RCR architectures for hit rates from 0.1 to 0.9 in steps of 0.1, memory access times of 10 to 100 ns, proportions of read/write access from 0.01 to 0.1, and block sizes of 8 to 64 words. The RCR architecture provides favorable performance over UMA and NUMA architectures for all ranges of application and system parameters. RCR outperforms LRG architectures when the hit rates of the processor cache exceed 80%and replicated memory exceed 25%. Thus, inclusion of a small replicated memory at each processor significantly reduces expected access time since all replicated memory hits become independent of global traffic. For configurations of up to 32 processors, results show that latency is further reduced by distinguishing burst-mode transfers between isolated memory accesses and those which are incrementally outside the working set.

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6

Arafa, Yehia, Abdel-Hameed A. Badawy, Gopinath Chennupati, Nandakishore Santhi, and Stephan Eidenbenz. "PPT-GPU: Scalable GPU Performance Modeling." IEEE Computer Architecture Letters 18, no. 1 (2019): 55–58. http://dx.doi.org/10.1109/lca.2019.2904497.

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7

Zaki, Omer, Ewing Lusk, William Gropp, and Deborah Swider. "Toward Scalable Performance Visualization with Jumpshot." International Journal of High Performance Computing Applications 13, no. 3 (1999): 277–88. http://dx.doi.org/10.1177/109434209901300310.

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8

Wu, Xingfu, and Wei Li. "Performance models for scalable cluster computing." Journal of Systems Architecture 44, no. 3-4 (1998): 189–205. http://dx.doi.org/10.1016/s1383-7621(97)00036-2.

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9

Kim, Yongtae, Jinhyuk Choi, and Haechul Choi. "Performance Analysis of Scalable HEVC Coding Tools." Journal of Broadcast Engineering 20, no. 4 (2015): 497–508. http://dx.doi.org/10.5909/jbe.2015.20.4.497.

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10

Chorng-Kuang Wang, R. Castello, and P. Gray. "A scalable high-performance switched-capacitor filter." IEEE Transactions on Circuits and Systems 33, no. 2 (1986): 167–74. http://dx.doi.org/10.1109/tcs.1986.1085890.

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11

Wang, C. K., R. Castello, and P. R. Gray. "A scalable high-performance switched-capacitor filter." IEEE Journal of Solid-State Circuits 21, no. 1 (1986): 57–64. http://dx.doi.org/10.1109/jssc.1986.1052482.

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12

Vingralek, Radek, Yuri Breitbart, and Gerhard Weikum. "Distributed file organization with scalable cost/performance." ACM SIGMOD Record 23, no. 2 (1994): 253–64. http://dx.doi.org/10.1145/191843.191889.

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13

Merrill, Duane, Michael Garland, and Andrew Grimshaw. "High-Performance and Scalable GPU Graph Traversal." ACM Transactions on Parallel Computing 1, no. 2 (2015): 1–30. http://dx.doi.org/10.1145/2717511.

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14

Sun, Xian-He, Thomas Fahringer, and Mario Pantano. "Scala: A Performance System for Scalable Computing." International Journal of High Performance Computing Applications 16, no. 4 (2002): 357–70. http://dx.doi.org/10.1177/109434200201600401.

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Summary Lack of effective performance-evaluation environments is a major barrier to the broader use of high performance computing. Conventional performance environments are based on profiling and event instrumentation. It becomes problematic as parallel systems scale to hundreds of nodes and beyond. A framework of developing an integrated performance modeling and prediction system, SCALability Analyzer (SCALA), is presented in this study. In contrast to existing performance tools, the program performance model generated by SCALA is based on scalability analysis. SCALA assumes the availability of modern compiler technology, adopts statistical and symbolic methodologies, and has the support of browser interface. These technologies, together with anew approach of scalability analysis, enable SCALA to provide the user with a more intuitive level of performance analysis for scalable computing. A prototype SCALA system has been implemented. Initial experimental results show that SCALA is unique in its ability of revealing the scaling properties of a computing system.

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15

Alhaddad, Ebraheem M., and Fathy E. Eassa. "High Performance and Scalable Big Data Manager." Journal of Computational and Theoretical Nanoscience 14, no. 9 (2017): 4603–11. http://dx.doi.org/10.1166/jctn.2017.6861.

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16

Decasper, D. S., B. Plattner, G. M. Parulkar, Sumi Choi, J. D. DeHart, and T. Wolf. "A scalable high-performance active network node." IEEE Network 13, no. 1 (1999): 8–19. http://dx.doi.org/10.1109/65.750445.

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17

Rolinger, Thomas B., Tyler A. Simon, and Christopher D. Krieger. "Performance considerations for scalable parallel tensor decomposition." Journal of Parallel and Distributed Computing 129 (July 2019): 83–98. http://dx.doi.org/10.1016/j.jpdc.2017.10.013.

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18

Clement, Mark J., and Michael J. Quinn. "Automated performance prediction for scalable parallel computing." Parallel Computing 23, no. 10 (1997): 1405–20. http://dx.doi.org/10.1016/s0167-8191(97)00066-5.

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19

Ikedo, Tsuneo. "A scalable high-performance graphics processor: GVIP." Visual Computer 11, no. 3 (1995): 121–33. http://dx.doi.org/10.1007/s003710050008.

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20

Desell, Travis, Kaoutar El Maghraoui, and Carlos A. Varela. "Malleable applications for scalable high performance computing." Cluster Computing 10, no. 3 (2007): 323–37. http://dx.doi.org/10.1007/s10586-007-0032-9.

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21

Taubman, D. "High performance scalable image compression with EBCOT." IEEE Transactions on Image Processing 9, no. 7 (2000): 1158–70. http://dx.doi.org/10.1109/83.847830.

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22

Bertsimas, Dimitris, Jean Pauphilet, and Bart Van Parys. "Sparse Regression: Scalable Algorithms and Empirical Performance." Statistical Science 35, no. 4 (2020): 555–78. http://dx.doi.org/10.1214/19-sts701.

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23

Brightwell, R., K. T. Pedretti, K. D. Underwood, and T. Hudson. "SeaStar Interconnect: Balanced Bandwidth for Scalable Performance." IEEE Micro 26, no. 3 (2006): 41–57. http://dx.doi.org/10.1109/mm.2006.65.

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24

Ikedo, Tsuneo. "A scalable high-performance graphics processor: GVIP." Visual Computer 11, no. 3 (1995): 121–33. http://dx.doi.org/10.1007/bf01898598.

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25

Upot, Nithin Vinod, Kazi Fazle Rabbi, Alireza Bakhshi, Johannes Kohler Mendizabal, Anthony M. Jacobi, and Nenad Miljkovic. "Etching-enabled ultra-scalable micro and nanosculpturing of metal surfaces for enhanced thermal performance." Applied Physics Letters 122, no. 3 (2023): 031603. http://dx.doi.org/10.1063/5.0134608.

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Incorporation of micro- and nanostructures on metals can improve thermal performance in a variety of applications. In this work, we demonstrate two independent highly scalable and cost-effective methods to generate micro- and nanostructures on copper and stainless steel, two widely used metals in energy and thermal applications. The performance of the developed structures, fabricated using scalable chemical etching techniques, is compared against their respective base metals. Our results demonstrate significant flow boiling heat transfer coefficient improvements up to 89% for etched copper and 104% for etched stainless steel. Mercury porosimetry is used to demonstrate that the varying pore-size distributions and presence of micro/nanoscale channels help to regulate heat transfer mechanisms, such as nucleate and convective flow boiling. Furthermore, structure integrity after 7-day flow boiling tests demonstrate surface structure resiliency to damage, a key challenge to implementation. This work combines advances in thermal performance with surface structure durability to provide guidelines for broader application of similar chemical etching methods to scalably create micro- and nanosculptured surfaces.

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26

Alazzawi, L., and A. Elkateeb. "Performance Evaluation of the WSN Routing Protocols Scalability." Journal of Computer Systems, Networks, and Communications 2008 (2008): 1–9. http://dx.doi.org/10.1155/2008/481046.

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Scalability is an important factor in designing an efficient routing protocol for wireless sensor networks (WSNs). A good routing protocol has to be scalable and adaptive to the changes in the network topology. Thus scalable protocol should perform well as the network grows larger or as the workload increases. In this paper, routing protocols for wireless sensor networks are simulated and their performances are evaluated to determine their capability for supporting network scalability.

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27

Pushkar, Mehendale. "Scalable Architecture for Machine Learning Applications." Journal of Scientific and Engineering Research 11, no. 8 (2024): 111–17. https://doi.org/10.5281/zenodo.13753585.

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In the realm of Machine Learning (ML) applications, scalable architectures are crucial for addressing the challenges posed by large-scale ML tasks. This paper explores the integration of distributed computing and cloud infrastructures to ensure scalability, efficiency, and reliability while maintaining optimal performance and cost-effectiveness. It compares different cloud platforms, evaluates design patterns and architectural strategies, presents case studies from real-world ML deployments, and analyzes emerging technologies shaping the landscape of ML in the cloud. The paper concludes by providing best practices for designing and deploying scalable ML applications in the cloud, empowering ML practitioners with the knowledge and tools to build robust and scalable ML solutions.

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28

Wang, Chengwei, Oliver Spatscheck, Vijay Gopalakrishnan, Yang Xu, and David Applegate. "Toward High-Performance and Scalable Network Functions Virtualization." IEEE Internet Computing 20, no. 6 (2016): 10–20. http://dx.doi.org/10.1109/mic.2016.111.

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29

Mannapur, Sandeep Bharadwaj. "OPTIMIZING AI PERFORMANCE: STRATEGIES FOR SCALABLE MODEL OBSERVABILITY." INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND INFORMATION TECHNOLOGY 8, no. 1 (2025): 992–1006. https://doi.org/10.34218/ijrcait_08_01_074.

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30

Bentaleb, Abdelhak, Saad Harous, and Abdelhak Boubetra. "A scalable clustering scheme and its performance evaluation." International Journal of Pervasive Computing and Communications 10, no. 1 (2014): 27–42. http://dx.doi.org/10.1108/ijpcc-01-2014-0004.

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31

Boukerche, Azzedine, Raed A. Al-Shaikh, and Mirela Sechi Moretti Annoni Notare. "Towards highly available and scalable high performance clusters." Journal of Computer and System Sciences 73, no. 8 (2007): 1240–51. http://dx.doi.org/10.1016/j.jcss.2007.02.011.

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32

Hai Le Vu, A. Zalesky, E. W. M. Wong, et al. "Scalable performance evaluation of a hybrid optical switch." Journal of Lightwave Technology 23, no. 10 (2005): 2961–73. http://dx.doi.org/10.1109/jlt.2005.855689.

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33

Behr, Marek, Daniel M. Pressel, and Walter B. Sturek, Sr. "Comments on CFD code performance on scalable architectures." Computer Methods in Applied Mechanics and Engineering 190, no. 3-4 (2000): 263–77. http://dx.doi.org/10.1016/s0045-7825(00)00201-2.

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34

Loredo, Juan C., Nor A. Zakaria, Niccolo Somaschi, et al. "Scalable performance in solid-state single-photon sources." Optica 3, no. 4 (2016): 433. http://dx.doi.org/10.1364/optica.3.000433.

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35

Bertsimas, Dimitris, Jean Pauphilet, and Bart Van Parys. "Rejoinder: Sparse Regression: Scalable Algorithms and Empirical Performance." Statistical Science 35, no. 4 (2020): 623–24. http://dx.doi.org/10.1214/20-sts701rej.

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36

Hasegawa, Go, Tatsuhiko Terai, Takuya Okamoto, and Masayuki Murata. "Scalable resource management for high-performance Web servers." International Journal of Communication Systems 17, no. 5 (2004): 389–406. http://dx.doi.org/10.1002/dac.650.

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37

Narra, Sudhakar Reddy. "KUBERNETES FOR PERFORMANCE ENGINEERING: A SCALABLE TESTING FRAMEWORK." INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND INFORMATION TECHNOLOGY 8, no. 1 (2025): 441–58. https://doi.org/10.34218/ijrcait_08_01_037.

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38

Pitchanathan, Arjun, Kunwar Grover, and Tobias Grosser. "Falcon: A Scalable Analytical Cache Model." Proceedings of the ACM on Programming Languages 8, PLDI (2024): 1854–78. http://dx.doi.org/10.1145/3656452.

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Compilers often use performance models to decide how to optimize code. This is often preferred over using hardware performance measurements, since hardware measurements can be expensive, limited by hardware availability, and makes the output of compilation non-deterministic. Analytical models, on the other hand, serve as efficient and noise-free performance indicators. Since many optimizations focus on improving memory performance, memory cache miss rate estimations can serve as an effective and noise-free performance indicator for superoptimizers, worst-case execution time analyses, manual program optimization, and many other performance-focused use cases. Existing methods to model the cache behavior of affine programs work on small programs such as those in the Polybench benchmark but do not scale to the larger programs we would like to optimize in production, which can be orders of magnitude bigger by lines of code. These analytical approaches hand of the whole program to a Presburger solver and perform expensive mathematical operations on the huge resulting formulas. We develop a scalable cache model for affine programs that splits the computation into smaller pieces that do not trigger the worst-case asymptotic behavior of these solvers. We evaluate our approach on 46 TorchVision neural networks, finding that our model has a geomean runtime of 44.9 seconds compared to over 32 minutes for the state-of-the-art prior cache model, and the latter is actually smaller than the true value because the prior model reached our four hour time limit on 54% of the networks, and this limit was never reached by our tool. Our model exploits parallelism effectively: running it on sixteen cores is 8.2x faster than running it single-threaded. While the state-of-the-art model takes over four hours to analyze a majority of the benchmark programs, Falcon produces results in at most 3 minutes and 3 seconds; moreover, after a local modification to the program being analyzed, our model efficiently updates the predictions in 513 ms on average (geomean). Thus, we provide the first scalable analytical cache model.

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39

Lulla, Karan. "Scalable Acoustic and Thermal Validation Strategies in GPU Manufacturing." International journal of data science and machine learning 5, no. 1 (2025): 193–214. https://doi.org/10.55640/ijdsml-05-01-19.

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As high-performance computing becomes increasingly popular, graphics processing units (GPUS) are finding their place in multiple industries, such as gaming, artificial intelligence and data processing. With continued evolutionary changes in performance and complexity of GPUS, the issue of using scalable acoustic and thermal validation strategies to guarantee the reliability and efficiency of these devices has become a major challenge for manufacturers. This article discusses how important it is to have a linear approach to validation procedures for acoustic and thermal properties in the case of GPU production. Acoustic validation targets noise control, critical for user satisfaction in quiet operating environments. Thermal validation provides an ideal heat dissipation to prevent performance throttling and hardware degradation. Both factors greatly contribute to making GPUS faster, longer-lasting, and providing a better user experience. The article discusses current standards of verification, problems with scaling current strategies to mass production, and developing trends (e.g. the use of artificial intelligence and machine learning for predictive testing). It indicates the necessity for more sophisticated and convenient validation methods to fit the increased complexity and needs for GPUS. Manufacturers are encouraged to use innovative validation systems like AI-driven systems to enhance testing accuracy and reduce costs and production timelines. The article ends with a call to action that urges manufacturers to embrace scalable validation methods to guarantee further success and development of GPUS in an ever more competitive environment.

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40

Arun, Balaji, and Binoy Ravindran. "Scalable byzantine fault tolerance via partial decentralization." Proceedings of the VLDB Endowment 15, no. 9 (2022): 1739–52. http://dx.doi.org/10.14778/3538598.3538599.

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Byzantine consensus is a critical component in many permissioned Blockchains and distributed ledgers. We propose a new paradigm for designing BFT protocols called DQBFT that addresses three major performance and scalability challenges that plague past protocols: (i) high communication costs to reach geo-distributed agreement, (ii) uneven resource utilization hampering performance, and (iii) performance degradation under varying node and network conditions and high-contention workloads. Specifically, DQBFT divides consensus into two parts: 1) durable command replication without a global order, and 2) consistent global ordering of commands across all replicas. DQBFT achieves this by decentralizing the heavy task of replicating commands while centralizing the ordering process. Under the new paradigm, we develop a new protocol, Destiny that uses a combination of three techniques to achieve high performance and scalability: using a trusted subsystem to decrease consensus's quorum size, using threshold signatures to attain linear communication costs, reducing client communication. Our evaluations on 300-replica geo-distributed deployment reveal that DQBFT protocols achieve significant performance gains over prior art: ≈3x better throughput and ≈50% better latency.

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41

Hiraga, Kohei, Osamu Tatebe, and Hideyuki Kawashima. "Scalable Distributed Metadata Server Based on Nonblocking Transactions." JUCS - Journal of Universal Computer Science 26, no. 1 (2020): 89–106. http://dx.doi.org/10.3897/jucs.2020.006.

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Metadata performance scalability is critically important in high-performance computing when accessing many small files from millions of clients. This paper proposes a design of a scalable distributed metadata server, PPMDS, for parallel file systems using multiple key-value servers. In PPMDS, hierarchical namespace of a file system is efficiently managed by multiple servers. Multiple entries can be atomically updated using a nonblocking distributed transaction based on an algorithm of dynamic software transactional memory. This paper also proposes optimizations to further improve the metadata performance by introducing a server-side transaction processing, multiple readers, and a shared lock mode, which reduce the number of remote procedure calls and prevent unnecessary blocking. Performance evaluation shows the scalable performance up to 3 servers, and achieves 62,000 operations per second, which is 2.58x performance improvement compared to a single metadata performance.

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42

Hiraga, Kohei, Osamu Tatebe, and Hideyuki Kawashima. "Scalable Distributed Metadata Server Based on Nonblocking Transactions." JUCS - Journal of Universal Computer Science 26, no. (1) (2020): 89–106. https://doi.org/10.3897/jucs.2020.006.

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Metadata performance scalability is critically important in high-performance computing when accessing many small files from millions of clients. This paper proposes a design of a scalable distributed metadata server, PPMDS, for parallel file systems using multiple key-value servers. In PPMDS, hierarchical namespace of a file system is efficiently managed by multiple servers. Multiple entries can be atomically updated using a nonblocking distributed transaction based on an algorithm of dynamic software transactional memory. This paper also proposes optimizations to further improve the metadata performance by introducing a server-side transaction processing, multiple readers, and a shared lock mode, which reduce the number of remote procedure calls and prevent unnecessary blocking. Performance evaluation shows the scalable performance up to 3 servers, and achieves 62,000 operations per second, which is 2.58x performance improvement compared to a single metadata performance.

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43

Bagam, Naveen. "Implementing Scalable Data Architecture for Financial Institutions." Stallion Journal for Multidisciplinary Associated Research Studies 2, no. 3 (2023): 27–40. https://doi.org/10.55544/sjmars.2.3.5.

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The finance sector generates vast volumes of complex data, which require scalable and robust architectures for efficient storage, processing, and analytics. Scalable data architecture is the basis that will make financial institutions competitive, compliant, and innovative in the modern fast-developing digital landscape. This paper addresses the principles, technologies, and methodologies necessary to implement scalable data architecture, keeping in mind high availability, security, and performance optimization as challenges. This paper is geared with real-world examples, technical frameworks, and performance metrics to provide actionable insights on scalability: both for legacy systems and new implementations.

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44

Irwin, Barry V. W., and Franco Loyola. "Towards Scalable Secure Syslog Compatible Remote Logging." International Conference on Intelligent and Innovative Computing Applications 2022 (December 31, 2022): 13–21. http://dx.doi.org/10.59200/iconic.2022.002.

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This research explains both why logging is useful and why the integrity of logs and the logging process is important. This is followed by a discussion of the design and implementation of a high-performance secure logging framework, implemented in Golang (Go). This is implemented as a server-client for *nix-like systems, with a focus on security first. While a custom protocol is introduced for security, the server remains compatible with traditional syslog log messages, albeit without the added performance and security features. The functionality of the implementation is reflected on along with preliminary performance bench-marking. While most of the design goals are satisfied, one notable area of concern is the performance hit caused through the use of RSA encryption. Aside from this the system was found to perform well with logging rates in excess of 20 thousand events per second achieved. The work concludes with some suggestions for improvements and future work.

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45

Sachin, Samrat Medavarapu. "Crafting Scalable Web Architectures: An In-Depth Exploration of ASP.NET Core and Azure." European Journal of Advances in Engineering and Technology 10, no. 5 (2023): 101–4. https://doi.org/10.5281/zenodo.13627397.

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Scalability in web architectures is crucial for handling increasing loads and ensuring performance stability. This paper explores the design and implementation of scalable web architectures using ASP.NET Core and Azure. It provides a comprehensive review of the current methodologies, presents experimental results, and discusses future research directions. The findings aim to serve as a guide for developers and researchers in building efficient, scalable web applications.

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46

Hou, Yanzhao, Nan Hu, Qimei Cui, and Xiaofeng Tao. "Performance analysis of scalable video transmission in machine-type-communication caching network." International Journal of Distributed Sensor Networks 15, no. 1 (2019): 155014771881585. http://dx.doi.org/10.1177/1550147718815851.

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In this article, different from the traditional Device-to-Device caching wireless cellular networks, we consider the scalable video coding performance in cache-based machine-type communication network, where popular videos encoded by scalable video coding method can be cached at machine-type devices with limited memory space. We conduct a comprehensive analysis of the caching hit probability using stochastic geometry, which measures the probability of requested video files cached by nearby local devices and the user satisfaction index, which is essential to delay sensitive video streams. Simulation results prove the derivation of the performance metrics to be correct, using Random cache method and Popularity Priority cache method. It is also demonstrated that scalable video coding–based caching method can be applied according to different user requirements as well as video-type requests, to achieve a better performance.

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47

Park, Seongmo, Hyunmi Kim, and Kyungjin Byun. "High Performance and FPGA Implementation of Scalable Video Encoder." IEIE Transactions on Smart Processing and Computing 3, no. 6 (2014): 353–57. http://dx.doi.org/10.5573/ieiespc.2014.3.6.353.

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48

Pankratov, Dmitry, Richard Sundberg, Javier Sotres, et al. "Scalable, high performance, enzymatic cathodes based on nanoimprint lithography." Beilstein Journal of Nanotechnology 6 (June 22, 2015): 1377–84. http://dx.doi.org/10.3762/bjnano.6.142.

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Here we detail high performance, enzymatic electrodes for oxygen bio-electroreduction, which can be easily and reproducibly fabricated with industry-scale throughput. Planar and nanostructured electrodes were built on biocompatible, flexible polymer sheets, while nanoimprint lithography was used for electrode nanostructuring. To the best of our knowledge, this is one of the first reports concerning the usage of nanoimprint lithography for amperometric bioelectronic devices. The enzyme (Myrothecium verrucaria bilirubin oxidase) was immobilised on planar (control) and artificially nanostructured, gold electrodes by direct physical adsorption. The detailed electrochemical investigation of bioelectrodes was performed and the following parameters were obtained: open circuit voltage of approximately 0.75 V, and maximum bio-electrocatalytic current densities of 18 µA/cm2 and 58 µA/cm2 in air-saturated buffers versus 48 µA/cm2 and 186 µA/cm2 in oxygen-saturated buffers for planar and nanostructured electrodes, respectively. The half-deactivation times of planar and nanostructured biocathodes were measured to be 2 h and 14 h, respectively. The comparison of standard heterogeneous and bio-electrocatalytic rate constants showed that the improved bio-electrocatalytic performance of the nanostructured biocathodes compared to planar biodevices is due to the increased surface area of the nanostructured electrodes, whereas their improved operational stability is attributed to stabilisation of the enzyme inside nanocavities.

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49

Chennupati, Gopinath, Nandakishore Santhi, Phill Romero, and Stephan Eidenbenz. "Machine Learning–enabled Scalable Performance Prediction of Scientific Codes." ACM Transactions on Modeling and Computer Simulation 31, no. 2 (2021): 1–28. http://dx.doi.org/10.1145/3450264.

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Hardware architectures become increasingly complex as the compute capabilities grow to exascale. We present the Analytical Memory Model with Pipelines (AMMP) of the Performance Prediction Toolkit (PPT). PPT-AMMP takes high-level source code and hardware architecture parameters as input and predicts runtime of that code on the target hardware platform, which is defined in the input parameters. PPT-AMMP transforms the code to an (architecture-independent) intermediate representation, then (i) analyzes the basic block structure of the code, (ii) processes architecture-independent virtual memory access patterns that it uses to build memory reuse distance distribution models for each basic block, and (iii) runs detailed basic-block level simulations to determine hardware pipeline usage. PPT-AMMP uses machine learning and regression techniques to build the prediction models based on small instances of the input code, then integrates into a higher-order discrete-event simulation model of PPT running on Simian PDES engine. We validate PPT-AMMP on four standard computational physics benchmarks and present a use case of hardware parameter sensitivity analysis to identify bottleneck hardware resources on different code inputs. We further extend PPT-AMMP to predict the performance of a scientific application code, namely, the radiation transport mini-app SNAP. To this end, we analyze multi-variate regression models that accurately predict the reuse profiles and the basic block counts. We validate predicted SNAP runtimes against actual measured times.

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Eswaramurthy, V., and A. P. V. Raghavendra. "Ensure Security and Scalable Performance in Multiple Relay Networks." International Journal of Computer Applications Technology and Research 3, no. 11 (2014): 682–84. http://dx.doi.org/10.7753/ijcatr0311.1006.

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