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Journal articles on the topic 'Schmitt trigger based SRAM'

Author: Grafiati

Published: 3 June 2025

Last updated: 19 July 2025

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1

NA, Hyoungjun, and Tetsuo ENDOH. "A Schmitt Trigger Based SRAM with Vertical MOSFET." IEICE Transactions on Electronics E95.C, no. 5 (2012): 792–801. http://dx.doi.org/10.1587/transele.e95.c.792.

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2

Jyoti, Dabass*, Pradeep Dimiri Dr., and Dabas Kadyan Manju. "ADAPTIVE SCHMITT TRIGGER BASED ON OTA DRIVEN BY DIFFERENTIAL INPUT VOLTAGE FOR SETTING QUIESCENT HYSTERESIS AND COMPENSATING AMPLIFIER OFFSET." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 4 (2016): 204–7. https://doi.org/10.5281/zenodo.48875.

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Schmitt Trigger, first presented by Schmitt in 1938 is extensively used in Pulse Width Modulation Circuits, Sensors, Square Wave Generators, buffers and Sub threshold SRAM. It utilizes the fundamental concept of bi-stable  state i.e.  for positive and negative going input signals, Schmitt Trigger shows different switching thresholds which is termed as Hysteresis. Slew rate and bandwidth of the op-amp restricts the performance of Schmitt Trigger based on op-amp. Schmitt Trigger using Current Conveyors lack electronically tuned hysteresis level.  CDTA and CCCDTA based Schmitt Trig

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3

Kulkarni, Jaydeep P., Keejong Kim, and Kaushik Roy. "A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM." IEEE Journal of Solid-State Circuits 42, no. 10 (2007): 2303–13. http://dx.doi.org/10.1109/jssc.2007.897148.

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4

Jain, Sarthak, Gamad R S, and Gurjar R C. "SCHMITT-TRIGGER-BASED SINGLE-ENDED LOW-POWER 8T SRAM CELL." ICTACT Journal on Microelectronics 7, no. 3 (2021): 1178–88. https://doi.org/10.21917/ijme.2021.0203.

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This article presents a new design of a single-ended low-power 8 transistor (8T) Static Random-Access Memory (SRAM) bitcell based on Schmitt-Trigger. The proposed cell is designed using a single bitline architecture that eradicates the conflict of design requirements on the access transistors. The proposed cell uses a Schmitt-Trigger based inverter which helps to increase the hold, read and write ability of the bitcell. A selective power gating transistor is also used which increases the write ability and also lowers the power consumption during write operations. Various parameters such as sig

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5

Achankunju, Priyanka Lee, Sreekala K S, and Marie K. James. "DESIGN AND READ STABILITYANALYSIS OF 8T SCHMITT TRIGGER BASED SRAM." ICTACT Journal on Microelectronics 02, no. 04 (2017): 323–28. http://dx.doi.org/10.21917/ijme.2017.0056.

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6

Ahmad, Sayeed, Mohit Kumar Gupta, Naushad Alam, and Mohd Hasan. "Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 8 (2016): 2634–42. http://dx.doi.org/10.1109/tvlsi.2016.2520490.

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7

Shrivastava, Manish, and Vimal Kishore Yadav. "Low power schmitt trigger based sram using 32nm finfet devices." Materials Today: Proceedings 5, no. 1 (2018): 1578–84. http://dx.doi.org/10.1016/j.matpr.2017.11.249.

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8

Kulkarni, Jaydeep P., and Kaushik Roy. "Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 2 (2012): 319–32. http://dx.doi.org/10.1109/tvlsi.2010.2100834.

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9

Sachdeva, Ashish, and V. K. Tomar. "A Schmitt-trigger based low read power 12T SRAM cell." Analog Integrated Circuits and Signal Processing 105, no. 2 (2020): 275–95. http://dx.doi.org/10.1007/s10470-020-01718-6.

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10

Pandey, Neeta, Aditya Singh Mann, and Abhay Setia. "Design of 8T DTMOS Schmitt Trigger SRAM Cell for IOT Applications." IOP Conference Series: Materials Science and Engineering 1316, no. 1 (2024): 012006. http://dx.doi.org/10.1088/1757-899x/1316/1/012006.

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Abstract Internet of things (IoT) based systems require power-efficient circuits to raise the battery lifeline. This study presents a single-ended 8T SRAM cell. The core of the proposed 8T SRAM cell is composed of a Schmitt-Trigger circuit which a dynamic body bias technique is applied to a standard CMOS inverter through a feedback mechanism, whereby the threshold voltages of two MOSFETs can be changed, thus changing the switching voltage. Read operation of the proposed cell is conducted using the shared footer per word transistor. The write path is cut-off during the read operation, improving

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11

Sowmya, Lalitha. "Low power/ Low Voltage Cross Coupled SRAM – Based on Schmitt Trigger." IOSR Journal of VLSI and Signal Processing 3, no. 2 (2013): 30–34. http://dx.doi.org/10.9790/4200-0323034.

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12

Suresh, Nakkala. "Low Voltage Low Power SRAM design based on Schmitt Trigger technique." IOSR Journal of VLSI and Signal Processing 3, no. 5 (2013): 01–06. http://dx.doi.org/10.9790/4200-0350106.

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13

Mansore, S. R., and Amit Naik. "Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell." Journal of VLSI Design and Signal Processing 8, no. 3 (2022): 18–22. http://dx.doi.org/10.46610/jovdsp.2022.v08i03.003.

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Technology scaling is done in order to accommodate more and more transistors in today’s high performance VLSI circuits. These high-performance digital circuits demand large capacity of memory to accomplish faithful operations. However, at scaled technology, SRAM-cell stability is a major issue of concern. Also, increased integration density of these VLSI circuits causes increased power consumption. Leakage power in today’s VLSI circuits has become comparable to dynamic power consumption which also needs to be addressed. In this work, a Schmitt-trigger (ST) based 10T SRAM cell with single-ended

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14

Mucherla Usha Rani, Et al. "-Memory Computing Based Reliable and High Speed Schmitt trigger 10T SRAM cell design." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 10 (2023): 1389–97. http://dx.doi.org/10.17762/ijritcc.v11i10.8681.

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Static random access memories (SRAM) are useful building blocks in various applications, including cache memories, integrated data storage systems, and microprocessors. The von Neumann bottleneck difficulties are solved by in-memory computing. It eliminates unnecessary frequent data transfer between memory and processing units simultaneously. In this research, the replica-based 10T SRAM design for in-memory computing (IMC) is designed by adapting the word line control scheme in 14nm CMOS technology. In order to achieve high reading and writing capability, the Schmitt trigger inverter was used

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15

Srinivasan, Vinesh, R. Varshad Venkatraman, and K. K. Senthil kumar. "Schmitt Trigger based SRAM Cell for Ultralow Power Operation- A CNFET based Approach." Procedia Engineering 64 (2013): 115–24. http://dx.doi.org/10.1016/j.proeng.2013.09.082.

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16

MAJA, M. PAD, and N. V. MAHESWARA RAO. "Low Power Design of Schmitt Trigger Based SRAM Cell Using NBTI Technique." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 03, no. 10 (2014): 16664–70. http://dx.doi.org/10.15662/ijareeie.2014.0310021.

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17

Cho, Keonhee, Juhyun Park, Tae Woo Oh, and Seong-Ook Jung. "One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 5 (2020): 1551–61. http://dx.doi.org/10.1109/tcsi.2020.2964903.

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18

Jain, Prashant Udaychand, and Vinaykumar Tomar. "Expanded Noise Margin 10T SRAM Cell using Finfet Device." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 9s (2023): 767–76. http://dx.doi.org/10.17762/ijritcc.v11i9s.7959.

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Static random access memory (SRAM) cells are being improved in order to increase resistance to device level changes and satisfy the requirements of low-power applications. A unique 10-transistor FinFET-based SRAM cell with single-ended read and differential write functionality is presented in this study. This cutting-edge architecture is more power-efficient than ST (Schmitt trigger) 10T or traditional 6T SRAM cells, using only 1.87 and 1.6 units of power respectively during read operations. The efficiency is attributable to a lower read activity factor, which saves electricity. The read stati

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19

Artola, Laurent, Benjamin Ruard, Julien Forest, and Guillaume Hubert. "Soft Error Simulation of Near-Threshold SRAM Design for Nanosatellite Applications." Electronics 12, no. 18 (2023): 3968. http://dx.doi.org/10.3390/electronics12183968.

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This paper presents the benefit of the near-threshold design of random-access memory (SRAM) design to reduce software errors during very low-power operations in nanosatellites. The near-threshold design is based on an optimization of the use of the Schmitt trigger structure for a 45 nm technology. The results of the soft error susceptibility of the optimized design are compared to a standard 6T SRAM cell. These two designs are modeled and validated by comparing the results with experimental measurements of both static noise margin (SNM) and single event upset (SEU). The optimized circuit reduc

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20

S, R. Mansore, and S. Gamad R. "Single-Ended 10T SRAM Cell with Improved Stability." Journal of VLSI Design and Signal Processing 5, no. 3 (2019): 19–25. https://doi.org/10.5281/zenodo.3491402.

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<em>In this work, a single-ended 10T static random access memory (SRAM) cell is presented. Proposed cell employs Schmitt- trigger (ST) based inverter to enhance read stability. Single ended feature of the cell saves switching power. Simulation is carried out on 180nm technology using Cadence. Results revealed that our cell provides 1.40x larger read static noise margin (RSNM) compared to conventional 6T cell at 0.7V. During write ‘0’ proposed cell offers 312mV of write static noise margin (WSNM) at 0.7V. During read operation, our cell offers 3.29x lower switching power compared to

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21

Ganesh, Chokkakula, Fazal Noorbasha, and Korlapati Satyanarayana Murthy. "Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 4 (2023): 3747. http://dx.doi.org/10.11591/ijece.v13i4.pp3747-3755.

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<span lang="EN-US">This paper presents a reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuit for the 9T Schmitt trigger-based static random-access memory (SRAM) cell (9T-ST), significantly improving write performance for real-time memory applications. In deep sub-micron technology, increasing device parameter deviations significantly reduce SRAM cells' write-ability. The proposed RNBLCS write-assist driver for 9T-ST SRAM cell has 0.84×, 0.48×, 0.27× optimized write access delay and 1.05×, 1.08×, 1.19× improvement in write static noise margin (WSNM), 1.05×, 1.1

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22

Mansore, S., and Amit Naik. "A Read-Decoupled Error-Tolerant 10T SRAM Cell in 32nm CMOS Technology." Jordan Journal of Electrical Engineering 9, no. 4 (2023): 481. http://dx.doi.org/10.5455/jjee.204-1670239866.

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Stability of static random access memory (SRAM) cells has become a growing concern in the nanometer regime. In order to address this issue, this paper proposes a read-decoupled 10 transistor (10T) SRAM cell. The decoupled-read feature of the proposed 10T SRAM cell protects it from the read-disturbance problem, thereby achieving enhanced read stability. Additionally, the bit interleaving capability of the cell provides immunity to soft errors. The simulation is performed on TSPICE software using a 32 nm CMOS predictive technology model. The obtained results reveal that the read static noise mar

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23

Chokkakula, Ganesh, Noorbasha Fazal, and Satyanarayana Murthy Korlapati. "Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 4 (2023): 3747–55. https://doi.org/10.11591/ijece.v13i4.pp3747-3755.

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This paper presents a reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuit for the 9T Schmitt trigger-based static random-access memory (SRAM) cell (9T-ST), significantly improving write performance for real-time memory applications. In deep sub-micron technology, increasing device parameter deviations significantly reduce SRAM cells' write-ability. The proposed RNBLCS write-assist driver for 9T-ST SRAM cell has 0.84×, 0.48×, 0.27× optimized write access delay and 1.05×, 1.08×, 1.19× improvement in write static noise margin (WS

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24

Sanapala, Kishore, Sakthivel R, and Sang-Soo Yeo. "Schmitt trigger-based single-ended 7T SRAM cell for Internet of Things (IoT) applications." Journal of Supercomputing 74, no. 9 (2018): 4613–22. http://dx.doi.org/10.1007/s11227-018-2433-3.

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25

Shirode, Ujwal R., Rajendra D. Kanphade, and Ajjay S. Gaadhe. "Stability and Power Analysis of Schmitt Trigger Based Low Power SRAM Bit-Cell Using CMOS and CNTFET Technology at 22nm Technology Node." Key Engineering Materials 945 (May 19, 2023): 41–46. http://dx.doi.org/10.4028/p-73f387.

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SRAM (Static Random Access Memory) is an essential component of memory devices such as laptops, phones, etc., which act as a semiconductor memory. The “Carbon Nanotube Field Effect Transistor (CNTFET)” is silicon associated high-stability, low-power device with excellent performance. CNTFET has been verified to be very advantageous for Very large-scale integration circuit designs in the nanoscale range because of its remarkable properties of metal oxide semiconductor field effect transistor (MOSFET). The material was brought to light because of its genuinely incredible electrochemical performa

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26

Dargupally, Mahipal, T. Vasudeva Reddy, and Udary Gnaneshwara Chary. "Design and Modeling of Schmitt Trigger-based Sub-Threshold 8T SRAM for Low Power Applications." International Journal of Computer Applications 104, no. 12 (2014): 37–40. http://dx.doi.org/10.5120/18257-9416.

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27

Sharma, Prakhar, Shourya Gupta, Kirti Gupta, and Neeta Pandey. "A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability." Microelectronics Journal 97 (March 2020): 104703. http://dx.doi.org/10.1016/j.mejo.2020.104703.

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28

Abbasian, Erfan, and Morteza Gholipour. "Design of a Schmitt-Trigger-Based 7T SRAM cell for variation resilient Low-Energy consumption and reliable internet of things applications." AEU - International Journal of Electronics and Communications 138 (August 2021): 153899. http://dx.doi.org/10.1016/j.aeue.2021.153899.

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29

Jyoti, Dabass* Dr. Pradeep Dimiri. "PROPOSED SRAM CELL USING LOW POWER SCHMITT TRIGGER IN SUB-THRESHOLD REGION WHICH ADAPTS ITS OWN THRESHOLD." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 5 (2016): 795–99. https://doi.org/10.5281/zenodo.51962.

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In 1950, an American biophysicist and polymath Otto Schmitt coined the term ‘Biomimetics’ (imitation of nature element, systems, models for the purpose of solving complex problems of the human). Proceeding on the same concept, finally he developed the Schmitt Trigger by studying the nerves in squid, attempting to engineer a device that replicated the nerve propagation’s biological system during his doctoral research. Many researchers proposed the numerous designs, advantages and implementation of Schmitt Trigger for different applications.   This paper reveals a detail r

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30

Singh, Damyanti, Neeta Pandey, and Kirti Gupta. "Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell." Microelectronics Journal 135 (May 2023): 105773. http://dx.doi.org/10.1016/j.mejo.2023.105773.

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31

Yang, Jun, Na Bai, Wei Qi Wu, Wei Wei Shan, and Zhi Kuang Cai. "A Robust SRAM Design for Ultra Dynamic Voltage Scalable VLSI System." Applied Mechanics and Materials 182-183 (June 2012): 450–55. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.450.

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In this paper, a SRAM array targeting IBM 130nm CMOS technology is proposed for ultra dynamic voltage scaling (UDVS) application with better immunity against process variation. A type of modified Schmitt Trigger inverter is adopted in the SRAM design, which guarantee stable operations in both superthreshold and subthreshold supply voltage regions. Testing results demonstrate that the proposed SRAM array functions well in the supply voltage range of 150 mV to 1200 mV. The optimum-energy supply voltage point is about 400 mV for proposed UDVS SRAM array. And the energy at 400 mV decreases by 62.5

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32

Surjith.N, Surjith N. "Improving Vmin of Sram by Schmitt-Trigger/Read-Write Techniques." IOSR journal of VLSI and Signal Processing 2, no. 1 (2013): 15–20. http://dx.doi.org/10.9790/4200-0211520.

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33

Vidhyadharan, Abhay Sanjay, and Sanjay Vidhyadharan. "Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications." World Journal of Engineering 18, no. 5 (2021): 750–59. http://dx.doi.org/10.1108/wje-08-2020-0367.

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Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMO

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34

AlAhdal, A., and C. Toumazou. "ISFET-based chemical Schmitt trigger." Electronics Letters 48, no. 10 (2012): 549. http://dx.doi.org/10.1049/el.2011.3781.

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35

Bastan, Yasin, and Parviz Amiri. "A Digital-Based Ultra-Low-Voltage Pseudo-Differential CMOS Schmitt Trigger." Journal of Circuits, Systems and Computers 29, no. 04 (2019): 2020002. http://dx.doi.org/10.1142/s0218126620200029.

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A digital-based Pseudo-differential Schmitt trigger is proposed in this paper which is suitable for ultra-low voltages and pure digital integrated circuit technologies. The proposed Schmitt trigger is implemented according to the design procedure of an analog Schmitt trigger and only using digital CMOS inverters. It is composed of a differential comparator consisting of two CMOS inverters and a cross-coupled inverter pair positive feedback which has simultaneously two outputs of noninverting and inverting. The proposed circuit is the only digital Schmitt trigger which operates in differential

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36

Soni, Lokesh, and Neeta Pandey. "A low power Schmitt-trigger driven 10T SRAM Cell for high speed applications." Integration 97 (July 2024): 102187. http://dx.doi.org/10.1016/j.vlsi.2024.102187.

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37

Singh, Nikhil, Siddharth Shekhar, Anita Angeline, and Kanchana Bhaaskaran V. S. "Schmitt Trigger Designs Using Domino Logic Style." ECS Transactions 107, no. 1 (2022): 8885–96. http://dx.doi.org/10.1149/10701.8885ecst.

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The advancements in the VLSI regime at lower technology node necessitate robust circuit design. Schmitt trigger design using domino logic style exhibit better hysteresis, higher noise margin, and reduced power consumption while compared to static CMOS Schmitt trigger design. This paper proposes three different Schmitt trigger designs based on domino logic style which produces a stable output with increased robustness against noise. The evaluation of dynamic logic-based Schmitt trigger using only NMOS transistors makes high speed operation feasible with reduced power consumption and increased h

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38

Mishra, Vishwas, Abhishek Kumar, Shobhit Tyagi, Neha Verma, and Divya Mishra. "CENSORSHIP OF LEAKAGE PARAMETERS OF A FINFET BASED SCHMITT TRIGGER AT NANO-METER REGIME." International Journal of Students' Research in Technology & Management 8, no. 2 (2020): 01–05. http://dx.doi.org/10.18510/ijsrtm.2020.821.

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Purpose: Recently FinFET technology has gained a lot of attention because of its superior fabrication process that is very similar to the fabrication of a conventional transistor. FinFETs unique feature as well as the potential applications make it a strong contender for the low power chip designs. Research is in full swing to use FinFET in analog circuits like Schmitt trigger, sensors, OPAMP and digital logic. The realization of the FinFET based circuits predicts that it is possible to broaden the concept of Moore’s law without unstoppable scaling of CMOS devices. Methodology: This work

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39

Kumar, Umesh. "Measurements and Analytical Computer-Based Study of CMOS Inverters and Schmitt Triggers." Active and Passive Electronic Components 19, no. 1 (1996): 41–54. http://dx.doi.org/10.1155/1996/52421.

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Modified CMOS inverters with three and four transistors have been made. Two varieties of CMOS Schmitt Triggers have been considered. CMOS Schmitt Trigger with wide hysteresis has been obtained. Complete detailed theoretical, experimental and computer based results are derived and exhibited.

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40

Challa, Padma, Chekuri Nalini, Suguna Tangimi, and Neelima Koppala. "Improved Domino Logic based Low Power CMOS Schmitt Trigger Circuit at Nano Scale Regime." Journal of Advanced Research in Applied Sciences and Engineering Technology 57, no. 2 (2024): 145–56. https://doi.org/10.37934/araset.57.2.145156.

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The requirement of high speed low power square wave generators that yield spike free signal enabled the design of Schmitt Trigger circuit. The designs BJT or FET based circuits have disadvantages like spikes in output signal cannot be suppressed, the output signal gain control is required, low packing density, considerable power dissipation, etc. This has paved way to development of CMOS based design. Further low power requirement enabled the CMOS based low power design aspects for the Schmitt Trigger circuit. The designs are modeled in DSCH and Microwind Tools for schematic and layout develop

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41

Maier, Jurgen, Christian Hartl-Nesic, and Andreas Steininger. "Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses." IEEE Transactions on Circuits and Systems I: Regular Papers 69, no. 3 (2022): 1013–26. http://dx.doi.org/10.1109/tcsi.2021.3130349.

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42

Radfar, Sara, Ali Nejati, Yasin Bastan, et al. "A Sub-Threshold Differential CMOS Schmitt Trigger with Adjustable Hysteresis Based on Body Bias Technique." Electronics 9, no. 5 (2020): 806. http://dx.doi.org/10.3390/electronics9050806.

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This paper presents a sub-threshold differential CMOS Schmitt trigger with tunable hysteresis, which can be used to enhance the noise immunity of low-power electronic systems. By exploiting the body bias technique to the positive feedback transistors, the hysteresis of the proposed Schmitt trigger is generated, and it can be adjusted by the applied bias voltage to the bulk terminal of the utilized PMOS transistors. The principle of operation and the main formulas of the proposed circuit are discussed. The circuit is designed in a 0.18-μm standard CMOS process with a 0.6 V power supply. Post-la

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43

Ahmad, Faroze. "Operational Amplifier based Schmitt Trigger with Digitally Controllable Hysteresis." International Journal of Computer Applications 171, no. 2 (2017): 31–33. http://dx.doi.org/10.5120/ijca2017914988.

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44

Zhao, Yue, Jing Lin Hu, Wen Zhong Lou, and Long Fei Zhang. "The Study of a Fluxgate SPICE Model Based on Schmitt Trigger." Key Engineering Materials 483 (June 2011): 212–18. http://dx.doi.org/10.4028/www.scientific.net/kem.483.212.

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Current fluxgate sensor probe SPICE models constructed by using arc tangent transfer function method and the diode model in fluxgate sensor simulation had some disadvantages which were non convergence, low simulation accuracy, discontinuously adjusted core characteristics and the model couldn’t simulate the hysteresis characteristic. IO characteristics of Schmitt Trigger was similar to the B-H curve of soft magnetic core in shape, for this reason Schmitt trigger was used to construct fluxgate probe SPICE model. HSPICE was used in simulation. Simulation results shown that this model can simulat

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45

Nejati, Ali, Yasin Bastan, Parviz Amiri, and Mohammad Hossein Maghami. "A Low-Voltage Bulk-Driven Differential CMOS Schmitt Trigger with Tunable Hysteresis." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1920004. http://dx.doi.org/10.1142/s0218126619200044.

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This paper describes a low-voltage bulk-driven differential CMOS Schmitt trigger with tunable hysteresis for use in noise removal applications. The hysteresis of the proposed Schmitt trigger is designed based on a regenerative current feedback and its width is adjustable by two control voltages. The center of the hysteresis can also be adjusted by either the control voltages or input common-mode voltage. The principle operation of the proposed circuit is discussed, its main formulas are derived and its performance is verified by Cadence post-layout simulations. Designed in the TSMC 0.18[Formul

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46

Zhang, Ting, and Mohammad Rafiqul Haider. "A Schmitt Trigger Based Oscillatory Neural Network for Reservoir Computing." Journal of Electrical and Electronic Engineering 8, no. 1 (2020): 1. http://dx.doi.org/10.11648/j.jeee.20200801.11.

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47

Singh, Damyanti, Kirti Gupta, and Neeta Pandey. "SCHMITT TRIGGER BASED NVSRAM CELL FOR LOW POWER MOBILE SYSTEMS." Proceedings on Engineering Sciences 6, no. 4 (2024): 1897–904. https://doi.org/10.24874/pes.si.25.03a.004.

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Ghanbari Khorram, Hamidreza, and Alireza Kokabi. "Proposed 3.5 µW CNTFET-MOSFET hybrid CSVCO for power-efficient gigahertz applications." Circuit World 46, no. 3 (2020): 193–202. http://dx.doi.org/10.1108/cw-03-2019-0022.

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Abstract:

Purpose Several ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are based on the three-stage hybrid circuit of the carbon nanotube field-effect transistors (CNTFETs) and low-power MOSFETs. The topologies exploit modified and compensated Schmitt trigger comparator parts to demonstrate better consumption power and frequency characteristics. The basic idea in the presented topologies is to compensate the Schmitt trigger comparator part of the basic CSVCO for achieving faster carrier mobilit

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Kushwah, Ravindra Singh, and Shyam Akashe. "FinFET Based Tunable Analog Circuit: Design and Analysis at 45 nm Technology." Chinese Journal of Engineering 2013 (October 24, 2013): 1–8. http://dx.doi.org/10.1155/2013/165945.

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We included a designing of low power tunable analog circuits built using independently driven FinFETs devices, where the controlling of the back gate provide the output on the front gate. We show that this could be an effective solution to conveniently tune the output of bulk CMOS analog circuits particularly for Schmitt trigger and operational transconductance amplifier circuits. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both are independently controlled. FinFET device has a higher controllability

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50

Polzer, Thomas, Robert Najvirt, Florian Beck, and Andreas Steininger. "On the Appropriate Handling of Metastable Voltages in FPGAs." Journal of Circuits, Systems and Computers 25, no. 03 (2015): 1640020. http://dx.doi.org/10.1142/s021812661640020x.

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Abstract:

The significant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper,

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