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Journal articles on the topic 'Schmitt Trigger'

Author: Grafiati

Published: 4 June 2021

Last updated: 12 February 2022

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1

Vidhyadharan, Abhay Sanjay, and Sanjay Vidhyadharan. "Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications." World Journal of Engineering 18, no. 5 (March 26, 2021): 750–59. http://dx.doi.org/10.1108/wje-08-2020-0367.

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Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

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2

Filanovsky, I. M., and H. Baltes. "CMOS Schmitt trigger design." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 41, no. 1 (1994): 46–49. http://dx.doi.org/10.1109/81.260219.

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3

Ramkumar, K., and K. Nagaraj. "A ternary Schmitt trigger." IEEE Transactions on Circuits and Systems 32, no. 7 (July 1985): 732–35. http://dx.doi.org/10.1109/tcs.1985.1085779.

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4

Steyaert, M., and W. Sansen. "Novel CMOS Schmitt trigger." Electronics Letters 22, no. 4 (1986): 203. http://dx.doi.org/10.1049/el:19860142.

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5

Kumar, Umesh. "Measurements and Analytical Computer-Based Study of CMOS Inverters and Schmitt Triggers." Active and Passive Electronic Components 19, no. 1 (1996): 41–54. http://dx.doi.org/10.1155/1996/52421.

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Modified CMOS inverters with three and four transistors have been made. Two varieties of CMOS Schmitt Triggers have been considered. CMOS Schmitt Trigger with wide hysteresis has been obtained. Complete detailed theoretical, experimental and computer based results are derived and exhibited.

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6

Wang, C. S., S. Y. Yuan, and S. Y. Kuo. "Full-swing BiCMOS Schmitt trigger." IEE Proceedings - Circuits, Devices and Systems 144, no. 5 (1997): 303. http://dx.doi.org/10.1049/ip-cds:19971142.

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7

Wang, Z., and W. Guggenbohl. "Novel CMOS current Schmitt trigger." Electronics Letters 24, no. 24 (1988): 1514. http://dx.doi.org/10.1049/el:19881034.

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8

Al-Sarawi, S. F. "Low power Schmitt trigger circuit." Electronics Letters 38, no. 18 (2002): 1009. http://dx.doi.org/10.1049/el:20020687.

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9

AlAhdal, A., and C. Toumazou. "ISFET-based chemical Schmitt trigger." Electronics Letters 48, no. 10 (2012): 549. http://dx.doi.org/10.1049/el.2011.3781.

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10

Bastan, Yasin, and Parviz Amiri. "A Digital-Based Ultra-Low-Voltage Pseudo-Differential CMOS Schmitt Trigger." Journal of Circuits, Systems and Computers 29, no. 04 (June 26, 2019): 2020002. http://dx.doi.org/10.1142/s0218126620200029.

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A digital-based Pseudo-differential Schmitt trigger is proposed in this paper which is suitable for ultra-low voltages and pure digital integrated circuit technologies. The proposed Schmitt trigger is implemented according to the design procedure of an analog Schmitt trigger and only using digital CMOS inverters. It is composed of a differential comparator consisting of two CMOS inverters and a cross-coupled inverter pair positive feedback which has simultaneously two outputs of noninverting and inverting. The proposed circuit is the only digital Schmitt trigger which operates in differential mode and its hysteresis center can be changed by the input voltage. Implementing the circuit in digital-based allows the proposed Schmitt trigger to operate in 0.4[Formula: see text]V ultra-low-voltage. Principle operation of the proposed circuit is discussed theoretically and using formulas and its performance is verified by simulation in TSMC 0.18[Formula: see text][Formula: see text]m CMOS process. The proposed circuit occupies only [Formula: see text][Formula: see text][Formula: see text]m2 chip area due to the very low number of transistors. The hysteresis width of the proposed Schmitt trigger is 205[Formula: see text]mV and consumes only 6.64[Formula: see text]nW power.

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11

ABUELMA'ATTI, MUHAMMAD TAHER. "Simple approximation for Schmitt trigger characteristics." International Journal of Electronics 58, no. 5 (May 1985): 871–73. http://dx.doi.org/10.1080/00207218508939081.

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12

Law, O. M. K., and C. A. T. Salama. "GaAs Schmitt trigger memory cell design." IEEE Journal of Solid-State Circuits 31, no. 8 (1996): 1190–92. http://dx.doi.org/10.1109/4.508268.

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13

Ramirez Chavez, S. R. "Mixed-mode Schmitt trigger equivalent circuit." Electronics Letters 31, no. 3 (February 2, 1995): 152–54. http://dx.doi.org/10.1049/el:19950107.

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14

Zhang, C., A. Srivastava, and P. K. Ajmera. "Low voltage CMOS Schmitt trigger circuits." Electronics Letters 39, no. 24 (2003): 1696. http://dx.doi.org/10.1049/el:20031131.

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15

Hang, Guo Qiang, Xuan Chang Zhou, Dan Yan Zhang, and Yang Yang. "Voltage-Mode Multi-Valued Schmitt Trigger with Neuron-MOS Transistors." Applied Mechanics and Materials 273 (January 2013): 310–15. http://dx.doi.org/10.4028/www.scientific.net/amm.273.310.

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A novel design scheme of multiple-valued Schmitt trigger using neuron-MOS transistors is presented. By controlling the voltages of the multiple-input gates, the neuron-MOS literal circuits with hysteresis characteristics are firstly designed. Then, the transmission switches used to pass quaternary signal are controlled by the outputs of these literal circuits to realize three hysteresis loops of quaternary Schmitt circuit. The benefit of the proposed quaternary Schmitt trigger is that the circuit can be fabricated by standard CMOS process with a 2-ploy layer. The three hysteresis loops are fully adjustable by sizing the ratio of capacitive coupling coefficients. The effectiveness of the proposed Schmitt trigger has been validated by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology, and the discrepancy of hysteresis values between the simulated and theoretical results is smaller than 6%.

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16

Mishra, Vishwas, Abhishek Kumar, Shobhit Tyagi, Neha Verma, and Divya Mishra. "CENSORSHIP OF LEAKAGE PARAMETERS OF A FINFET BASED SCHMITT TRIGGER AT NANO-METER REGIME." International Journal of Students' Research in Technology & Management 8, no. 2 (June 16, 2020): 01–05. http://dx.doi.org/10.18510/ijsrtm.2020.821.

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Purpose: Recently FinFET technology has gained a lot of attention because of its superior fabrication process that is very similar to the fabrication of a conventional transistor. FinFETs unique feature as well as the potential applications make it a strong contender for the low power chip designs. Research is in full swing to use FinFET in analog circuits like Schmitt trigger, sensors, OPAMP and digital logic. The realization of the FinFET based circuits predicts that it is possible to broaden the concept of Moore’s law without unstoppable scaling of CMOS devices. Methodology: This work is carried out on the Candence Simulation tool. After the simulation, all these parameters have been compared with previous published 4T Schmitt trigger at 45nm with this design and found that they are in close vicinity. Main Findings: By combining the superior flexibility and reduced short channel effects (SCEs) of FinFET devices offers a promising approach to implement highly integrated, power-efficient Schmitt Trigger circuit for low power digital applications. Schmitt trigger is a device capable of removing unwanted noise from the input and prevent the other operations from this unwanted noise and improve the performance of the device. Implications: This study is discussing and performs a comparative analysis of different leakage parameters of a FinFET based Schmitt Trigger with previous 4T Schmitt Trigger at 45nm. The novelty of Study: Size, power, speed, Cost etc. are important factors for designing any new circuits in the field of Electronics. Various eminent researchers have been making efforts for this. This paper makes some effort to discuss about past research and design a new circuit where the value of delay, leakage power and dynamic power reduces when compared to previously published circuits.

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17

Yuan, Fei. "Differential CMOS Schmitt trigger with tunable hysteresis." Analog Integrated Circuits and Signal Processing 62, no. 2 (August 13, 2009): 245–48. http://dx.doi.org/10.1007/s10470-009-9366-y.

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18

FILANOVSKY, I. M. "A Schmitt trigger with current mirror feedback." International Journal of Electronics 65, no. 4 (October 1988): 837–44. http://dx.doi.org/10.1080/00207218808945284.

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19

RAMKUMAR, K., and M. SATYAM. "Research note A novel BIMOS Schmitt trigger." International Journal of Electronics 66, no. 2 (February 1989): 267–71. http://dx.doi.org/10.1080/00207218908925382.

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20

Marchesoni, F., F. Apostolico, and S. Santucci. "Stochastic resonance in an asymmetric Schmitt trigger." Physical Review E 59, no. 4 (April 1, 1999): 3958–63. http://dx.doi.org/10.1103/physreve.59.3958.

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21

Pfister, A. "Novel CMOS Schmitt trigger with controllable hysteresis." Electronics Letters 28, no. 7 (1992): 639. http://dx.doi.org/10.1049/el:19920404.

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22

Zou, Zhige, Xuecheng Zou, Xiaowu Dai, and Jianming Lei. "Novel Schmitt trigger with wide temperature range." Wuhan University Journal of Natural Sciences 13, no. 2 (April 2008): 191–94. http://dx.doi.org/10.1007/s11859-008-0212-3.

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23

Siripruchyanun, Montree, Pracharat Satthaphol, and Kangwal Payakkakul. "A Simple Fully Controllable Schmitt Trigger with Electronic Method Using VDTA." Applied Mechanics and Materials 781 (August 2015): 180–83. http://dx.doi.org/10.4028/www.scientific.net/amm.781.180.

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A simple Schmitt trigger employing single VDTA (Voltage Difference Transconductance Amplifier) and one grounded resistor is proposed. The feature of the proposed Schmitt trigger is that its output hysteresis and amplitude can be independently adjusted. The PSpice simulation results are disclosed, it agrees well with the theoretical anticipation. The total power consumption approximately 443µW at ±1.5V supply voltages.

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24

NA, Hyoungjun, and Tetsuo ENDOH. "A Schmitt Trigger Based SRAM with Vertical MOSFET." IEICE Transactions on Electronics E95.C, no. 5 (2012): 792–801. http://dx.doi.org/10.1587/transele.e95.c.792.

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25

Zimpeck, A. L., C. Meinhardt, L. Artola, G. Hubert, F. L. Kastensmidt, and R. A. L. Reis. "Circuit design using Schmitt Trigger to reliability improvement." Microelectronics Reliability 114 (November 2020): 113754. http://dx.doi.org/10.1016/j.microrel.2020.113754.

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26

Arith, Faiz. "Low voltage CMOS Schmitt Trigger in 0.18μm technology." IOSR Journal of Engineering 03, no. 03 (March 2013): 08–15. http://dx.doi.org/10.9790/3021-03320815.

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27

RIDDERS, C. J. F. "Simulation of the hysteresis of a Schmitt trigger." International Journal of Electronics 60, no. 4 (April 1986): 541–42. http://dx.doi.org/10.1080/00207218608920814.

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28

Melnikov, V. I. "Schmitt trigger: A solvable model of stochastic resonance." Physical Review E 48, no. 4 (October 1, 1993): 2481–89. http://dx.doi.org/10.1103/physreve.48.2481.

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29

Smith, M. J. S. "On the circuit analysis of the Schmitt trigger." IEEE Journal of Solid-State Circuits 23, no. 1 (1988): 292–94. http://dx.doi.org/10.1109/4.293.

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30

Marchesoni, F., F. Apostolico, L. Gammaitoni, and S. Santucci. "Color effects in a near-threshold Schmitt trigger." Physical Review E 58, no. 6 (December 1, 1998): 7079–84. http://dx.doi.org/10.1103/physreve.58.7079.

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31

Diutaldo, G., G. Palumbo, and S. Pennisi. "A schmitt trigger by means of a ccii+." International Journal of Circuit Theory and Applications 23, no. 2 (March 1995): 161–65. http://dx.doi.org/10.1002/cta.4490230207.

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32

Tache, Mihai, Walid Ibrahim, Fekri Kharbash, and Valeriu Beiu. "Reliability and performance of optimised Schmitt trigger gates." Journal of Engineering 2018, no. 8 (August 1, 2018): 735–44. http://dx.doi.org/10.1049/joe.2018.0091.

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33

Wang, Z., and W. GuggenbÜhl. "CMOS current schmitt trigger with fully adjustable hysteresis." Electronics Letters 25, no. 6 (1989): 397. http://dx.doi.org/10.1049/el:19890273.

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34

He, Lin, Gang Li, and Meng Tang. "Relaxation Oscillator Exploiting PTAT Hysteresis of Differential Schmitt Trigger." Journal of Circuits, Systems and Computers 24, no. 10 (October 25, 2015): 1550147. http://dx.doi.org/10.1142/s0218126615501479.

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In this paper, we proposed a novel relaxation oscillator to address the frequency variation caused by the comparator delay. The conventional operational transconductance amplifiers (OTAs)-comparator is replaced with a Schmitt trigger to significantly reduce the delay. This Schmitt trigger is implemented by a differential structure operating in the subthreshold region to generate a proportional to absolute temperature (PTAT) hysteresis. Both the voltage reference and the current source are made PTAT as well. The proposed oscillator can be made ultra-low power and have excellent frequency stability over process, voltage and temperature (PVT) variation.

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35

Radfar, Sara, Ali Nejati, Yasin Bastan, Parviz Amiri, Mohammad Hossein Maghami, Mehdi Nasrollahpour, and Sotoudeh Hamedi-Hagh. "A Sub-Threshold Differential CMOS Schmitt Trigger with Adjustable Hysteresis Based on Body Bias Technique." Electronics 9, no. 5 (May 14, 2020): 806. http://dx.doi.org/10.3390/electronics9050806.

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This paper presents a sub-threshold differential CMOS Schmitt trigger with tunable hysteresis, which can be used to enhance the noise immunity of low-power electronic systems. By exploiting the body bias technique to the positive feedback transistors, the hysteresis of the proposed Schmitt trigger is generated, and it can be adjusted by the applied bias voltage to the bulk terminal of the utilized PMOS transistors. The principle of operation and the main formulas of the proposed circuit are discussed. The circuit is designed in a 0.18-μm standard CMOS process with a 0.6 V power supply. Post-layout simulation results show that the hysteresis width of the Schmitt trigger can be adjusted from 45.5 mV to 162 mV where the ratio of the hysteresis width variation to supply voltage is 19.4%. This circuit consumes 10.52 × 7.91 μm2 of silicon area, and its power consumption is only 1.38 µW, which makes it a suitable candidate for low-power applications such as portable electronic, biomedical, and bio-implantable systems.

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36

Nejati, Ali, Yasin Bastan, Parviz Amiri, and Mohammad Hossein Maghami. "A Low-Voltage Bulk-Driven Differential CMOS Schmitt Trigger with Tunable Hysteresis." Journal of Circuits, Systems and Computers 28, no. 07 (June 27, 2019): 1920004. http://dx.doi.org/10.1142/s0218126619200044.

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This paper describes a low-voltage bulk-driven differential CMOS Schmitt trigger with tunable hysteresis for use in noise removal applications. The hysteresis of the proposed Schmitt trigger is designed based on a regenerative current feedback and its width is adjustable by two control voltages. The center of the hysteresis can also be adjusted by either the control voltages or input common-mode voltage. The principle operation of the proposed circuit is discussed, its main formulas are derived and its performance is verified by Cadence post-layout simulations. Designed in the TSMC 0.18[Formula: see text][Formula: see text]m standard CMOS process, the circuit consumes [Formula: see text]m2 of silicon area. Post-layout simulation results indicate that the hysteresis width of the Schmitt trigger can be adjusted from 170 to 270[Formula: see text]mV and the ratio of the hysteresis width variation to supply voltage is 11.11%. Operated with 0.8[Formula: see text]V supply voltage, the power consumption of the circuit ranges from 0.48 to 1.12[Formula: see text]mW.

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37

Abrar, Md Moyeed. "Design and Implementation of Schmitt Trigger using Operational Amplifier." International Journal of Engineering Research and Applications 7, no. 01 (January 2017): 05–09. http://dx.doi.org/10.9790/9622-0701040509.

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38

Chawla, Chanchal. "A Modified High Hysteresis Low Power CMOS Schmitt Trigger." International Journal for Research in Applied Science and Engineering Technology V, no. IX (September 30, 2017): 341–46. http://dx.doi.org/10.22214/ijraset.2017.9051.

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39

Ahmad, Faroze. "Operational Amplifier based Schmitt Trigger with Digitally Controllable Hysteresis." International Journal of Computer Applications 171, no. 2 (August 17, 2017): 31–33. http://dx.doi.org/10.5120/ijca2017914988.

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40

Hsieh, Chien-Yu, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, and Ching-Te Chuang. "Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 7 (July 2012): 1201–10. http://dx.doi.org/10.1109/tvlsi.2011.2156435.

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41

Kumar, A., and B. Chaturvedi. "Fully electronically controllable Schmitt trigger circuit with dual hysteresis." Electronics Letters 53, no. 7 (March 2017): 459–61. http://dx.doi.org/10.1049/el.2016.4770.

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42

Kulkarni, Jaydeep P., Keejong Kim, and Kaushik Roy. "A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM." IEEE Journal of Solid-State Circuits 42, no. 10 (October 2007): 2303–13. http://dx.doi.org/10.1109/jssc.2007.897148.

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43

Liao, Tai-Shan, and Chun-Ming Chang. "Current mode Schmitt trigger for a phototransistor/resistor detector." Review of Scientific Instruments 71, no. 8 (August 2000): 3233. http://dx.doi.org/10.1063/1.1304860.

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44

Lo, Yu-Kang, Hung-Chun Chien, and Huang-Jen Chiu. "Current-input OTRA Schmitt trigger with dual hysteresis modes." International Journal of Circuit Theory and Applications 38, no. 7 (February 27, 2009): 739–46. http://dx.doi.org/10.1002/cta.584.

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45

Çelen, S. "Mathematical principle of cellular accommodation: A Schmitt trigger approach." Materialwissenschaft und Werkstofftechnik 47, no. 4 (April 2016): 301–6. http://dx.doi.org/10.1002/mawe.201600500.

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46

Ridders, C. "Accurate determination of threshold voltage levels of Schmitt trigger." IEEE Transactions on Circuits and Systems 32, no. 9 (September 1985): 969–70. http://dx.doi.org/10.1109/tcs.1985.1085805.

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47

Carroll, Thomas L. "Multiple time scale chaos in a Schmitt trigger circuit." Chaos: An Interdisciplinary Journal of Nonlinear Science 15, no. 3 (September 2005): 033104. http://dx.doi.org/10.1063/1.1984768.

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48

Ghanbari Khorram, Hamidreza, and Alireza Kokabi. "Proposed 3.5 µW CNTFET-MOSFET hybrid CSVCO for power-efficient gigahertz applications." Circuit World 46, no. 3 (January 30, 2020): 193–202. http://dx.doi.org/10.1108/cw-03-2019-0022.

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Purpose Several ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are based on the three-stage hybrid circuit of the carbon nanotube field-effect transistors (CNTFETs) and low-power MOSFETs. The topologies exploit modified and compensated Schmitt trigger comparator parts to demonstrate better consumption power and frequency characteristics. The basic idea in the presented topologies is to compensate the Schmitt trigger comparator part of the basic CSVCO for achieving faster carrier mobility of the holes, reducing transistor leakage current and eliminating dummy transistors. Design/methodology/approach This study aims to propose and compare three different comparator-based VCOs that have been implemented using the CNTFETs. The considered circuits are shown to be capable of delivering the maximum 35 tuning frequency in the order of 1 GHz to 5 GHz. A major power thirsty part of the high-frequency ring VCOs is the Schmitt trigger stage. Here, several fast and low-power Schmitt trigger topologies are exploited to mitigate the dissipation power and enhance the oscillation frequency. Findings As a result of proposed modifications, more than one order of magnitude mitigation in the VCO power consumption with respect to the previously presented three-stage CSVCO is reported here. Thus, a VCO dissipation power of 3.5 µW at the frequency of 1.1 GHz and the tuning range of 26 per cent is observed for the well-established 32 nm technology and the supply voltage of 1 V. Such a low dissipation power is obtained around the operating frequency of the battery-powered cellular phones. In addition, using the p-carrier mobility compensation and enhancing the rise time of the Schmitt trigger part of the CSVCO, a maximum of 2.38 times higher oscillation frequency and 72 per cent wider tuning range with respect to Rahane and Kureshi (2017) are observed. Simultaneously, this topology exhibits an average of 20 per cent reduction in the power consumption. Originality/value Several new VCO topologies are presented here, and it is shown that they can significantly enhance the power dissipation of the GHz CSVCOs.

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49

Marzaki, Abderrezak, V. Bidal, R. Laffont, W. Rahajandraibe, J.-M. Portal, and R. Bouchakour. "New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)." International Journal of Reconfigurable and Embedded Systems (IJRES) 2, no. 1 (March 1, 2013): 49. http://dx.doi.org/10.11591/ijres.v2.i1.pp49-54.

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This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages <em>V<sub>TH- </sub></em>(low switching voltage) and <em>V<sub>TH+ </sub></em>(high switching voltage).

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50

Polzer, Thomas, Robert Najvirt, Florian Beck, and Andreas Steininger. "On the Appropriate Handling of Metastable Voltages in FPGAs." Journal of Circuits, Systems and Computers 25, no. 03 (December 28, 2015): 1640020. http://dx.doi.org/10.1142/s021812661640020x.

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The significant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high- and low-threshold buffers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an “in situ reliability assessment” of the specific Schmitt-trigger element under consideration, which also applies to metastability containment with high- or low-threshold buffers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.

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