Relevant bibliographies by topics / Secure Circuit

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Secure Circuit'

Author: Grafiati
Published: 4 June 2021
Last updated: 17 February 2022

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Journal articles on the topic "Secure Circuit"

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Abadi, Martín, and Joan Feigenbaum. "Secure circuit evaluation." Journal of Cryptology 2, no. 1 (1990): 1–12. http://dx.doi.org/10.1007/bf02252866.

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Alexeyev, Alexander A., and Michael M. Green. "Secure Communications Based on Variable Topology of Chaotic Circuits." International Journal of Bifurcation and Chaos 07, no. 12 (1997): 2861–69. http://dx.doi.org/10.1142/s0218127497001941.

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A new technique for synchronization of chaotic circuits is proposed. This technique, based on varying a circuit's overall topology rather than varying a set of continuous parameters, offers a possible resolution to the tradeoff between security and synchronizability inherent in existing chaotic systems. The encryption key is represented by a mapping from a set of nodes to a set of switches in the circuit. This method significantly improves reliability and can be easily interfaced to digital control circuits.
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CHEN, Huanhuan. "Quantum secure circuit evaluation." Science in China Series F 47, no. 6 (2004): 717. http://dx.doi.org/10.1360/03yf0457.

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ÇİÇEK, SERDAR, YILMAZ UYAROĞLU, and İHSAN PEHLİVAN. "SIMULATION AND CIRCUIT IMPLEMENTATION OF SPROTT CASE H CHAOTIC SYSTEM AND ITS SYNCHRONIZATION APPLICATION FOR SECURE COMMUNICATION SYSTEMS." Journal of Circuits, Systems and Computers 22, no. 04 (2013): 1350022. http://dx.doi.org/10.1142/s0218126613500229.

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Nowadays, many simulations, implementations, synchronization and secure communication applications of chaotic circuits have been introduced in literature. However, electronics circuit design and implementation of nonlinear Sprott Case H chaotic system and its synchronization were not found in the literature. In this paper, numerical model, electronics circuit simulation and implementation electronics circuits of the Sprott Case H chaotic system and its synchronization by the method of Pecora and Carroll (P–C) complete replacement (CR) were performed. The simulation and implementation results s
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Yuan, Xingliang, Jian Weng, Cong Wang, and Kui Ren. "Secure Integrated Circuit Design via Hybrid Cloud." IEEE Transactions on Parallel and Distributed Systems 29, no. 8 (2018): 1851–64. http://dx.doi.org/10.1109/tpds.2018.2807844.

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Storace, M. "Secure communication by hysteresis-based chaotic circuit." Electronics Letters 34, no. 11 (1998): 1077. http://dx.doi.org/10.1049/el:19980796.

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Fang, Xin, Stratis Ioannidis, and Miriam Leeser. "SIFO: Secure Computational Infrastructure Using FPGA Overlays." International Journal of Reconfigurable Computing 2019 (December 6, 2019): 1–18. http://dx.doi.org/10.1155/2019/1439763.

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Secure Function Evaluation (SFE) has received recent attention due to the massive collection and mining of personal data, but remains impractical due to its large computational cost. Garbled Circuits (GC) is a protocol for implementing SFE which can evaluate any function that can be expressed as a Boolean circuit and obtain the result while keeping each party’s input private. Recent advances have led to a surge of garbled circuit implementations in software for a variety of different tasks. However, these implementations are inefficient, and therefore GC is not widely used, especially for larg
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Alibeigi, Iman, Abdolah Amirany, Ramin Rajaei, Mahmoud Tabandeh, and Saeed Bagheri Shouraki. "A Low-Cost Highly Reliable Spintronic True Random Number Generator Circuit for Secure Cryptography." SPIN 10, no. 01 (2019): 2050003. http://dx.doi.org/10.1142/s2010324720500034.

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Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in
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Xiong, Li, Zhenlai Liu, and Xinguo Zhang. "Dynamical Analysis, Synchronization, Circuit Design, and Secure Communication of a Novel Hyperchaotic System." Complexity 2017 (2017): 1–23. http://dx.doi.org/10.1155/2017/4962739.

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This paper is devoted to introduce a novel fourth-order hyperchaotic system. The hyperchaotic system is constructed by adding a linear feedback control level based on a modified Lorenz-like chaotic circuit with reduced number of amplifiers. The local dynamical entities, such as the basic dynamical behavior, the divergence, the eigenvalue, and the Lyapunov exponents of the new hyperchaotic system, are all investigated analytically and numerically. Then, an active control method is derived to achieve global chaotic synchronization of the novel hyperchaotic system through making the synchronizati
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Ding, Hangchao, Han Jiang, and Qiuliang Xu. "Postquantum Cut-and-Choose Oblivious Transfer Protocol Based on LWE." Security and Communication Networks 2021 (September 8, 2021): 1–15. http://dx.doi.org/10.1155/2021/9974604.

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We propose postquantum universal composable (UC) cut-and-choose oblivious transfer (CCOT) protocol under the malicious adversary model. In secure two-party computation, we construct s copies’ garbled circuits, including half check circuit and half evaluation circuit. The sender can transfer the key to the receiver by CCOT protocol. Compared to PVW-OT [6] framework, we invoke WQ-OT [35] framework with reusability of common random string ( crs ) and better security. Relying on LWE’s assumption and the property of the Rounding function, we construct an UC-CCOT protocol, which can resist quantum a
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Dissertations / Theses on the topic "Secure Circuit"

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Yu, Pengyuan. "Implementation of DPA-Resistant Circuit for FPGA." Thesis, Virginia Tech, 2007. http://hdl.handle.net/10919/32053.

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In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an existing circuit within the same FPGA fabric. We have solved this problem in a way that still enables us to modify the logic function of the copied submodule. Our technique has important applications in the design of side-channel resistant implementations in FPGA. Starting from an existing single-ended design, we are able to create a complementary circuit. The resulting overall circuit strongly reduces the power-consump
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Sundström, Timmy. "A comparison of circuit implementations from a security perspective." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-401.

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<p>In the late 90's research showed that all circuit implementations were susceptible to power analysis and that this analysis could be used to extract secret information. Further research to counteract this new threat by adding countermeasures or modifying the nderlaying algorithm only seemed to slow down the attack.</p><p>There were no objective analysis of how different circuit implementations leak information and by what magnitude.</p><p>This thesis will present such an objective comparison on five different logic styles. The comparison results are based on simulations performed on transis
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Sinha, Ambuj Sudhir. "Design Techniques for Side-channel Resistant Embedded Software." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/34465.

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Side Channel Attacks (SCA) are a class of passive attacks on cryptosystems that exploit implementation characteristics of the system. Currently, a lot of research is focussed towards developing countermeasures to side channel attacks. In this thesis, we address two challenges that are an inherent part of the efficient implementation of SCA countermeasures. While designing a system, design choices made for enhancing the efficiency or performance of the system can also affect the side channel security of the system. The first challenge is that the effect of different design choices on the side c
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Pehlivanoglu, Serdar. "Rijndael Circuit Level Cryptanalysis." Link to electronic thesis, 2005. http://www.wpi.edu/Pubs/ETD/Available/etd-050505-121816/.

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Thesis (M.S.) -- Worcester Polytechnic Institute.<br>Keywords: private-key cryptography; Advanced Encryption Standard; K-secure; hermetic; block cipher; circuit complexity. Includes bibliographical references (p. 75-79).
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Sundaresan, Vijay. "Architectural Synthesis Techniques for Design of Correct and Secure ICs." University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1217424117.

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Chen, Zhimin. "SCA-Resistant and High-Performance Embedded Cryptography Using Instruction Set Extensions and Multi-Core Processors." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/51256.

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Nowadays, we use embedded electronic devices in almost every aspect of our daily lives. They represent our electronic identity; they store private information; they monitor health status; they do confidential communications, and so on. All these applications rely on cryptography and, therefore, present us a research objective: how to implement cryptography on embedded systems in a trustworthy and efficient manner. Implementing embedded cryptography faces two challenges - constrained resources and physical attacks. Due to low cost constraints and power budget constraints, embedded device
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Nejat, Arash. "Tirer parti du masquage logique pour faciliter les méthodes de détection des chevaux de Troie hardware." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT004.

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La complexité sans cesse croissante de la conception et de la fabrication de circuits intégrés (CI) a nécessité l'emploi de tiers tels que des bureaux d'études, des fournisseurs de propriété intellectuelle (PI) et des fonderies de fabrication afin d'accélérer et d'économiser le processus de développement. La séparation de ces parties entraîne certaines menaces pour la sécurité. Les fonderies de fabrication non fiables sont suspectées de trois menaces de sécurité: chevaux de Troie matériels, piratage IP et surproduction de circuits intégrés. Les chevaux de Troie matériels sont des modifications
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Tobich, Karim. "Évaluation de l’efficacité des techniques d’injection de fautes, au sein de microcontrôleurs, par agression électromagnétique." Thesis, Montpellier 2, 2013. http://www.theses.fr/2013MON20017.

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De nos jours, le LASER reste l'outil le plus efficace et le plus utilisé pour injecter des fautes au sein des micro-contrôleurs sécurisés modernes. Parmi ses principaux avantages nous pouvons citer ses fortes résolutions spatiale et temporelle. Ces avantages ne sont toutefois accessibles qu'au prix d'investissements conséquents en temps et argent avec un coût oscillant entre deux et quatre centaines de milliers d'euros selon la qualité du LASER.Outre ces aspects financiers, la publication par les scientifiques, ainsi que l'intégration par les fabricants de cartes à puce, de contre-mesures effi
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Desai, Nachiket Venkappayya. "Circuits for efficient and secure power delivery in distributed applications." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/109004.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 159-167).<br>The growing number of widely distributed IoT devices presents new challenges in power delivery. Existing frameworks for charging electronic devices, be they wired or wireless, either end up limiting the amount devices can be shrunk due to the size of standardized connectors or end up restricting their free placement due to their reliance on charging mats. The large amounts of v
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Dupin, Aurélien. "Secure Multi-Party Computation and Privacy." Thesis, CentraleSupélec, 2019. http://www.theses.fr/2019CSUP0010.

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Les calculs multi-parties sécurisés (MPC) sont une branche de la cryptographie qui a pour objectif de concevoir des solutions permettant à plusieurs parties de calculer ensemble une fonction de leurs données, tout en gardant ces données secrètes. Contrairement à la cryptographie classique, où l’on cherche à assurer la sécurité malgré la présence d’un adversaire extérieur, le MPC garantit la sécurité face à un adversaire interne contrôlant un ou plusieurs participants. Cette thèse apporte à la fois des contributions théoriques et pratiques dans le domaine du MPC. D’un point de vue théorique, un
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Books on the topic "Secure Circuit"

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Verbauwhede, Ingrid. Secure integrated circuits and systems. Springer, 2010.

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Verbauwhede, Ingrid M. R., ed. Secure Integrated Circuits and Systems. Springer US, 2010. http://dx.doi.org/10.1007/978-0-387-71829-3.

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Lavery, Niall. Secure communications through the use of synchronised chaotic circuits. The Author], 1996.

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Bonnenberg, Heinz. Secure testing of VLSI cryptographic equipment. Hartung-Gorre, 1993.

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Bastos, Rodrigo Possamai, and Frank Sill Torres. On-Chip Current Sensors for Reliable, Secure, and Low-Power Integrated Circuits. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-29353-6.

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Peeters, Eric. Advanced DPA Theory and Practice: Towards the Security Limits of Secure Embedded Circuits. Springer New York, 2013.

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Myasnikov, Alexei G. Non-commutative cryptography and complexity of group-theoretic problems. American Mathematical Society, 2011.

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Clancy, Tom. Net Force. Penguin USA, Inc., 2009.

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Clancy, Tom. Tom Clancy's Net force. Berkley Books, 1999.

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R, Pieczenik Steve, ed. Hidden agendas. Berkley Books, 1999.

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Book chapters on the topic "Secure Circuit"

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Schneider, Thomas. "Circuit Optimizations and Constructions." In Engineering Secure Two-Party Computation Protocols. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-30042-4_3.

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Xiao, Kan, Domenic Forte, and Mohammad (Mark) Tehranipoor. "Circuit Timing Signature (CTS) for Detection of Counterfeit Integrated Circuits." In Secure System Design and Trustable Computing. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-14971-4_6.

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Schneider, Thomas. "Hardware-Assisted Garbled Circuit Protocols." In Engineering Secure Two-Party Computation Protocols. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-30042-4_4.

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Kennedy, W. Sean, Vladimir Kolesnikov, and Gordon Wilfong. "Overlaying Conditional Circuit Clauses for Secure Computation." In Advances in Cryptology – ASIACRYPT 2017. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-70697-9_18.

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Abadi, Martín, and Joan Feigenbaum. "A simple protocol for secure circuit evaluation." In STACS 88. Springer Berlin Heidelberg, 1988. http://dx.doi.org/10.1007/bfb0035850.

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Heldmann, Tim, Thomas Schneider, Oleksandr Tkachenko, Christian Weinert, and Hossein Yalame. "LLVM-Based Circuit Compilation for Practical Secure Computation." In Applied Cryptography and Network Security. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-78375-4_5.

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Toma, Diana, Dominique Borrione, and Ghiath Al Sammane. "Combining Several Paradigms for Circuit Validation and Verification." In Construction and Analysis of Safe, Secure, and Interoperable Smart Devices. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/978-3-540-30569-9_12.

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Hubert Chan, T. H., and Elaine Shi. "Circuit OPRAM: Unifying Statistically and Computationally Secure ORAMs and OPRAMs." In Theory of Cryptography. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-70503-3_3.

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Manoj, Palavlasa, and Datti Venkata Ramana. "Designing of DPA Resistant Circuit Using Secure Differential Logic Gates." In Advances in Intelligent Systems and Computing. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2734-2_45.

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Boyle, Elette, Niv Gilboa, and Yuval Ishai. "Breaking the Circuit Size Barrier for Secure Computation Under DDH." In Advances in Cryptology – CRYPTO 2016. Springer Berlin Heidelberg, 2016. http://dx.doi.org/10.1007/978-3-662-53018-4_19.

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Conference papers on the topic "Secure Circuit"

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Gomez, Mario N. "DoD Design Cloud Analysis: Securing the Integrated Circuit Design Process." In ASME 2012 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2012. http://dx.doi.org/10.1115/detc2012-70256.

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The use of unsecure foundries has allowed and is still providing a pathway for counterfeit microelectronics into U.S. defense systems. As a result, the Warfighter has been put at risk and a solution is needed. To counter this dilemma, this study looks into the feasibility of creating a Department of Defense (DoD) - wide design cloud that would provide circuit designers with a more secure and economical way of designing and fabricating circuits. The design cloud would include secure communication to trusted foundries along with needed circuit design software. Factors such as security, costs, be
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Saini, Sanju, and J. S. Saini. "Secure communication using memristor based chaotic circuit." In 2014 International Conference on Parallel, Distributed and Grid Computing (PDGC). IEEE, 2014. http://dx.doi.org/10.1109/pdgc.2014.7030734.

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Taheri, Shayan, and Jiann-Shiun Yuan. "Security analysis of computing systems from circuit-architectural perspective." In 2017 IEEE Conference on Dependable and Secure Computing. IEEE, 2017. http://dx.doi.org/10.1109/desec.2017.8073843.

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Jugale, Abhinandan Ajit, C. M. Bhoomika, B. T. Anjanakumari, and Mohammed Riyaz Ahmed. "Memristor based Chaotic Circuit Design for Secure Communication." In 2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI). IEEE, 2019. http://dx.doi.org/10.1109/icoei.2019.8862515.

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Irfan, Sk, Ch Rupa, K. Vinay, M. Krishna Veni, and R. Rachana. "Smart Virtual Circuit based Secure Vehicle Operating System." In 2020 2nd International Conference on Innovative Mechanisms for Industry Applications (ICIMIA). IEEE, 2020. http://dx.doi.org/10.1109/icimia48430.2020.9074940.

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Deniz, Halil Ibrahim, Zehra Gulru Cam Taskiran, and Herman Sedef. "Chaotic Lorenz Synchronization Circuit Design for Secure Communication." In 2018 6th International Conference on Control Engineering & Information Technology (CEIT). IEEE, 2018. http://dx.doi.org/10.1109/ceit.2018.8751890.

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Chen, Zhimin, Ambuj Sinha, and Patrick Schaumont. "Implementing virtual secure circuit using a custom-instruction approach." In the 2010 international conference. ACM Press, 2010. http://dx.doi.org/10.1145/1878921.1878933.

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Wang, Xueyan, Xiaotao Jia, Qiang Zhou, et al. "Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers." In GLSVLSI '16: Great Lakes Symposium on VLSI 2016. ACM, 2016. http://dx.doi.org/10.1145/2902961.2903000.

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Riazi, M. Sadegh, Mojan Javaheripi, Siam U. Hussain, and Farinaz Koushanfar. "MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation." In 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2019. http://dx.doi.org/10.1109/hst.2019.8740831.

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Ostanin, S., A. Matrosova, N. Butorina, and V. Lavrov. "A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit." In 2016 IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2016. http://dx.doi.org/10.1109/ewdts.2016.7807676.

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Reports on the topic "Secure Circuit"

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Payment Systems Report - June of 2020. Banco de la República de Colombia, 2021. http://dx.doi.org/10.32468/rept-sist-pag.eng.2020.

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With its annual Payment Systems Report, Banco de la República offers a complete overview of the infrastructure of Colombia’s financial market. Each edition of the report has four objectives: 1) to publicize a consolidated account of how the figures for payment infrastructures have evolved with respect to both financial assets and goods and services; 2) to summarize the issues that are being debated internationally and are of interest to the industry that provides payment clearing and settlement services; 3) to offer the public an explanation of the ideas and concepts behind retail-value paymen
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