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Relevant bibliographies by topics / Secure microarchitecture

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Journal articles
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Academic literature on the topic 'Secure microarchitecture'

Author: Grafiati

Published: 6 September 2023

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Journal articles on the topic "Secure microarchitecture"

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Li, Xinyao, and Akhilesh Tyagi. "Cross-World Covert Channel on ARM Trustzone through PMU." Sensors 22, no. 19 (2022): 7354. http://dx.doi.org/10.3390/s22197354.

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The TrustZone technology is incorporated in a majority of recent ARM Cortex A and Cortex M processors widely deployed in the IoT world. Security critical code execution inside a so-called secure world is isolated from the rest of the application execution within a normal world. It provides hardware-isolated area called a trusted execution environment (TEE) in the processor for sensitive data and code. This paper demonstrates a vulnerability in the secure world in the form of a cross-world, secure world to normal world, covert channel. Performance counters or Performance Monitoring Unit (PMU) e

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Gnanavel, S., K. E. Narayana, K. Jayashree, P. Nancy, and Dawit Mamiru Teressa. "Implementation of Block-Level Double Encryption Based on Machine Learning Techniques for Attack Detection and Prevention." Wireless Communications and Mobile Computing 2022 (July 9, 2022): 1–9. http://dx.doi.org/10.1155/2022/4255220.

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Cloud computing is one of the most important business models of modern information technology. It provides a minimum of various services to the user interaction and low cost (hardware and software). Cloud services are based on the newline architectures on virtualization by using the multitenancy for better resource management and newline strong isolation between several virtual machines (VMs). The spying on a victim VM is challenging, particularly when one wants to use per-core microarchitectural features as a side channel. For example, the cache contains the most potential for damaging side c

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Stolz, Florian, Jan Philipp Thoma, Pascal Sasdrich, and Tim Güneysu. "Risky Translations: Securing TLBs against Timing Side Channels." IACR Transactions on Cryptographic Hardware and Embedded Systems, November 29, 2022, 1–31. http://dx.doi.org/10.46586/tches.v2023.i1.1-31.

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Microarchitectural side-channel vulnerabilities in modern processors are known to be a powerful attack vector that can be utilized to bypass common security boundaries like memory isolation. As shown by recent variants of transient execution attacks related to Spectre and Meltdown, those side channels allow to leak data from the microarchitecture to the observable architectural state. The vast majority of attacks currently build on the cache-timing side channel, since it is easy to exploit and provides a reliable, fine-grained communication channel. Therefore, many proposals for side-channel s

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Sahni, Abdul Rasheed, Hamza Omar, Usman Ali, and Omer Khan. "ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes." ACM Transactions on Architecture and Code Optimization, March 17, 2023. http://dx.doi.org/10.1145/3587480.

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With the ever-increasing virtualization of software and hardware, the privacy of user-sensitive data is a fundamental concern in computation outsourcing. Secure processors enable a trusted execution environment to guarantee security properties based on the principles of isolation, sealing, and integrity. However, the shared hardware resources within the microarchitecture are increasingly being used by co-located adversarial software to create timing-based side-channel attacks. State-of-the-art secure processors implement the strong isolation primitive to enable non-interference for shared hard

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Cabrera Aldaya, Alejandro, and Billy Bob Brumley. "Online Template Attacks: Revisited." IACR Transactions on Cryptographic Hardware and Embedded Systems, July 9, 2021, 28–59. http://dx.doi.org/10.46586/tches.v2021.i3.28-59.

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An online template attack (OTA) is a powerful technique previously used to attack elliptic curve scalar multiplication algorithms. This attack has only been analyzed in the realm of power consumption and EM side channels, where the signals leak related to the value being processed. However, microarchitecture signals have no such feature, invalidating some assumptions from previous OTA works.In this paper, we revisit previous OTA descriptions, proposing a generic framework and evaluation metrics for any side-channel signal. Our analysis reveals OTA features not previously considered, increasing

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Narayan, Akhilesh S., Ashish J, Noor Afreen, Lithesh V S, and Sandeep R. "RTL Design, Verification and Synthesis of Secure Hash Algorithm to implement on an ASIC Processor." International Journal of Scientific Research in Science, Engineering and Technology, May 1, 2019, 70–75. http://dx.doi.org/10.32628/ijsrset196318.

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In this project we are comparing different architectures and adding the features that increases the efficiency of our architecture. Few of them are including multiplexers in the message digester, using different adder architectures in the required places, reducing the critical path by breaking the longest path and making them to operate parallelly. Use of multiplexers reduces the number of registers required in the message expander. It simply transfers the output of expander to compressor block in every clock cycle. Whenever the number of cycle is greater than 16, the multiplexer switches the

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Yu, Jiyong, Lucas Hsiung, Mohamad El Hajj, and Christopher Fletcher. "Creating Foundations for Secure Microarchitectures with Data-Oblivious ISA Extensions." IEEE Micro, 2020, 1. http://dx.doi.org/10.1109/mm.2020.2985366.

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Sakalis, Christos, Stefanos Kaxiras, and Magnus Själander. "Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks." ACM Transactions on Architecture and Code Optimization, September 19, 2022. http://dx.doi.org/10.1145/3563695.

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MicroScope and other similar microarchitectural replay attacks take advantage of the characteristics of speculative execution to trap the execution of the victim application in a loop, enabling the attacker to amplify a side-channel attack by executing it indefinitely. Due to the nature of the replay, it can be used to effectively attack software that are shielded against replay, even under conditions where a side-channel attack would not be possible (e.g., in secure enclaves). At the same time, unlike speculative side-channel attacks, microarchitectural replay attacks can be used to amplify t

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Naghibijouybari, Hoda, Esmaeil Mohammadian Koruyeh, and Nael Abu-Ghazaleh. "Microarchitectural Attacks in Heterogeneous Systems: A Survey." ACM Computing Surveys, June 15, 2022. http://dx.doi.org/10.1145/3544102.

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With the increasing proliferation of hardware accelerators and the predicted continued increase in the heterogeneity of future computing systems, it is necessary to understand the security properties of such systems. In this survey article, we consider the security of heterogeneous systems against microarchitectural attacks, with a focus on covert- and side-channel attacks, as well as fault injection attacks. We review works that have explored the vulnerability of the individual accelerators (such as Graphical Processing Units, GPUs and Field Programmable Gate Arrays, FPGAs) against these atta

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Dissertations / Theses on the topic "Secure microarchitecture"

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Zabel, Martin, Thomas B. Preußer, Peter Reichel, and Rainer G. Spallek. "SHAP-Secure Hardware Agent Platform." Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200701011.

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This paper presents a novel implementation of an embedded Java microarchitecture for secure, realtime, and multi-threaded applications. Together with the support of modern features of object-oriented languages, such as exception handling, automatic garbage collection and interface types, a general-purpose platform is established which also fits for the agent concept. Especially, considering real-time issues, new techniques have been implemented in our Java microarchitecture, such as an integrated stack and thread management for fast context switching, concurrent garbage collection for real-tim

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Jain, Rajat. "Achieving practical secure non-volatile memory system with in-Memory Integrity Verification (iMIV)." Thesis, 2022. https://etd.iisc.ac.in/handle/2005/5867.

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Recent commercialization of Non-Volatile Memory (NVM) technology in the form of Intel Optane enables programmers to write recoverable programs. However, the data on NVM is susceptible to a plethora of data remanence attacks, which makes confidentiality and integrity protection of data essential for a secure NVM system. However, that requires computing and maintaining a large amount of security metadata (encryption counters, message authentication code (MAC), and integrity tree nodes (BMT)). Furthermore, crash consistency guarantees require the system to persist the security metadata and data a

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Book chapters on the topic "Secure microarchitecture"

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Grimsdal, Gunnar, Patrik Lundgren, Christian Vestlund, Felipe Boeira, and Mikael Asplund. "Can Microkernels Mitigate Microarchitectural Attacks?" In Secure IT Systems. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-35055-0_15.

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Sepúlveda, Johanna. "Secure Cryptography Integration: NoC-Based Microarchitectural Attacks and Countermeasures." In Network-on-Chip Security and Privacy. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-69131-8_7.

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Liu, Chen, Xiaobin Li, Shaoshan Liu, and Jean-Luc Gaudiot. "Simultaneous MultiThreading Microarchitecture." In Handbook of Research on Scalable Computing Technologies. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-661-7.ch024.

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Due to the conventional sequential programming model, the Instruction-Level Parallelism (ILP) that modern superscalar processors can explore is inherently limited. Hence, multithreading architectures have been proposed to exploit Thread-Level Parallelism (TLP) in addition to conventional ILP. By issuing and executing instructions from multiple threads at each clock cycle, Simultaneous MultiThreading (SMT) achieves some of the best possible system resource utilization and accordingly higher instruction throughput. In this chapter, the authors describe the origin of SMT microarchitecture, comparing it with other multithreading microarchitectures. They identify several key aspects for high-performance SMT design: fetch policy, handling long-latency instructions, resource sharing control, synchronization and communication. They also describe some potential benefits of SMT microarchitecture: SMT for faulttolerance and SMT for secure communications. Given the need to support sequential legacy code and emerge of new parallel programming model, we believe SMT microarchitecture will play a vital role as we enter the multi-thread multi/many-core processor design era.

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Conference papers on the topic "Secure microarchitecture"

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Kanuparthi, Arun K., Ramesh Karri, Gaston Ormazabal, and Sateesh K. Addepalli. "A high-performance, low-overhead microarchitecture for secure program execution." In 2012 IEEE 30th International Conference on Computer Design (ICCD 2012). IEEE, 2012. http://dx.doi.org/10.1109/iccd.2012.6378624.

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Miao, Chenlu, Kai Bu, Mengming Li, Shaowu Mao, and Jianwei Jia. "SwiftDir: Secure Cache Coherence without Overprotection." In 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2022. http://dx.doi.org/10.1109/micro56248.2022.00052.

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Lehman, Tamara Silbergleit, Andrew D. Hilton, and Benjamin C. Lee. "PoisonIvy: Safe speculation for secure memory." In 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2016. http://dx.doi.org/10.1109/micro.2016.7783741.

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Zabel, Martin, T. B. Preusser, Peter Reichel, and Rainer G. Spallek. "Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture." In 2007 10th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. IEEE, 2007. http://dx.doi.org/10.1109/dsd.2007.4341450.

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Shi, Weidong, and Hsien-Hsin S. Lee. "Authentication Control Point and Its Implications For Secure Processor Design." In 2006 39th IEEE/ACM International Symposium on Microarchitecture. IEEE, 2006. http://dx.doi.org/10.1109/micro.2006.11.

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Wang, Xin, Daulet Talapkaliyev, Matthew Hicks, and Xun Jian. "Self-Reinforcing Memoization for Cryptography Calculations in Secure Memory Systems." In 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2022. http://dx.doi.org/10.1109/micro56248.2022.00055.

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Omar, Hamza, and Omer Khan. "IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications." In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2020. http://dx.doi.org/10.1109/hpca47549.2020.00019.

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He, Zecheng, and Ruby B. Lee. "How secure is your cache against side-channel attacks?" In MICRO-50: The 50th Annual IEEE/ACM International Symposium on Microarchitecture. ACM, 2017. http://dx.doi.org/10.1145/3123939.3124546.

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Freij, Alexander, Huiyang Zhou, and Yan Solihin. "Bonsai Merkle Forests: Efficiently Achieving Crash Consistency in Secure Persistent Memory." In MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture. ACM, 2021. http://dx.doi.org/10.1145/3466752.3480067.

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Saileshwar, Gururaj, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Jose A. Joao, and Moinuddin K. Qureshi. "Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories." In 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2018. http://dx.doi.org/10.1109/micro.2018.00041.

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