Academic literature on the topic 'Self-biased differential amplifier'

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Journal articles on the topic "Self-biased differential amplifier"

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Chae, M., J. Kim, and W. Liu. "Fully-differential self-biased bio-potential amplifier." Electronics Letters 44, no. 24 (2008): 1390. http://dx.doi.org/10.1049/el:20089097.

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Chen, C. L., and Y. C. Chang. "Self-biased cross-coupled low-cost fully-differential CMOS operational amplifier." Electronics Letters 41, no. 9 (2005): 512. http://dx.doi.org/10.1049/el:20057998.

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Singh, Shyam, Ravi Kumar, and K. S. Paraliya. "High Speed and High Resolution Self Biased Differential Amplifier based Latch Comparator." International Journal of Computer Applications 74, no. 3 (2013): 9–13. http://dx.doi.org/10.5120/12863-9653.

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Figueiredo, Michael, Rui Santos-Tavares, Edinei Santin, João Ferreira, Guiomar Evans, and João Goes. "A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency." IEEE Transactions on Circuits and Systems I: Regular Papers 58, no. 7 (2011): 1591–603. http://dx.doi.org/10.1109/tcsi.2011.2150910.

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Rodovalho, Luis Henrique, Cesar Ramos Rodrigues, and Orazio Aiello. "Self-Biased and Supply-Voltage Scalable Inverter-Based Operational Transconductance Amplifier with Improved Composite Transistors." Electronics 10, no. 8 (2021): 935. http://dx.doi.org/10.3390/electronics10080935.

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This paper deals with a single-stage single-ended inverter-based Operational Transconductance Amplifiers (OTA) with improved composite transistors for ultra-low-voltage supplies, while maintaining a small-area, high power-efficiency and low output signal distortion. The improved composite transistor is a combination of the conventional composite transistor and forward-body-biasing to further increase voltage gain. The impact of the proposed technique on performance is demonstrated through post-layout simulations referring to the TSMC 180 nm technology process. The proposed OTA achieves 54 dB differential voltage gain, 210 Hz gain–bandwidth product for a 10 pF capacitive load, with a power consumption of 273 pW with a 0.3 V power supply, and occupies an area of 1026 μm2. For a 0.6 V voltage supply, the proposed OTA improves its voltage gain to 73 dB, and achieves a 15 kHz gain–bandwidth product with a power consumption of 41 nW.
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Sapawi, Rohana. "Review of Efficiency CMOS Class AB Power Amplifier Topology in Gigahertz Frequencies." ASM Science Journal 17 (May 17, 2022): 1–11. http://dx.doi.org/10.32802/asmscj.2022.1224.

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This paper reviewed the efficiency of CMOS class AB power amplifier topology especially in gigahertz frequencies. CMOS class AB power amplifier is a compromise between class A and class B in terms of linearity and efficiency between 50% to 78.5%. However, CMOS class AB power amplifier cannot have good linearity and efficiency simultaneously due to the breakdown in gate-oxide voltage and effects from hot carrier. The breakdown of oxide prevents optimum drain signal and the effect from hot carrier will reduce the quality of the overall PA design. Several works from year 1999 to 2019 with different topology such as multiple gated transistor, cascode, feedforward linearization, differential circuit, transformer combining method with common source harmonic termination and combination of a dual-switching transistor with a third harmonic tuning technique are discussed and the performances of the power amplifier are compared. The best three CMOS class AB power amplifier topologies were chosen in terms of high efficiency. The topologies are two stages with integrated input and interstage matching, Doherty amplifier combined with drain modulation based architectures and self-biased cascode topology that obtained power added efficiency of 45%, 43% and 42%, respectively. Key performance indicators for class AB power amplifier include frequency, power added efficiency, gain and output power are also discussed in this paper.
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Wang, Rong, and Jincai Wen. "A 30–60 GHz Broadband Low LO-Drive Down-Conversion Mixer with Active IF Balun in 65 nm CMOS Technology." Micromachines 15, no. 7 (2024): 845. http://dx.doi.org/10.3390/mi15070845.

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A 30~60 GHz broadband down-conversion mixer driven by low local oscillator (LO) power is presented. The down-conversion mixer utilizes an input signal coupling technique based on the Marchand balun to achieve broadband operation and achieves low LO power drive and low DC power consumption through the use of a weak inversion bias with Gilbert switching devices. The broadband conversion of single-ended to differential signals is achieved using the Marchand balun with compensation lines, and an equivalent circuit analysis is performed. For the intermediate frequency (IF) output, a self-biased IF trans-impedance amplifier with current reusing and an active IF balun structure are used to achieve signal amplification and single-ended signal output. Test results show that the proposed mixer achieves a conversion gain of −1.2 to 6.4 dB in an IF output bandwidth of 0.1 to 5 GHz at radio frequency (RF) input frequencies of 30 to 60 GHz and LO driving power of −10 dBm. The DC power consumption of the core mixing unit of the proposed mixer is 4.8 mW, and the DC power consumption including the IF amplifier is 28.3 mW. The proposed mixer uses a 65 nm CMOS technology with a chip area of 0.26 mm2.
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He, Yuefeng, Guoshun Yuan, Lei Lei, Hongjiang Yu та Dewei Kong. "A 3.95 ppm/°C 7.5 μW Second-Order Curvature Compensated Bandgap Reference in 0.11 μm CMOS". Electronics 11, № 18 (2022): 2869. http://dx.doi.org/10.3390/electronics11182869.

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In order to meet the requirements of modern portable electronics for high accuracy and low power consumption of bandgap reference circuits, a new low-voltage bandgap reference with a second-order compensated circuit at 1.8 V is proposed. It features a new self-biased fully symmetric differential operational amplifier circuit with the help of split transistors for achieving low power consumption and high accuracy; by adding a new sub-threshold compensated circuit. The results of simulation show that the temperature coefficient of the second-order circuit is 3.95 ppm/°C in the temperature range of −40 to 125 °C, and the power consumption is only 7.5 μW; this meets both the requirements of high precision and low power consumption. At the same time, the output noise voltage of the design is less than 30 μV/sqrt (Hz) at a frequency of 100 Hz, and the low-frequency supply voltage rejection ratio is −103 dB@100 Hz; these are acceptable for bandgap reference circuits.
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Pandey, Rakesh Kumar, Vijaya Bhadauria, and Vinod Kumar Singh. "Ultra-low-power super class-AB adaptive biasing operational transconductance amplifier with enhanced gain for biomedical applications." Bulletin of Electrical Engineering and Informatics 13, no. 4 (2024): 2368–80. http://dx.doi.org/10.11591/eei.v13i4.7585.

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The operational transconductance amplifier (OTA) proposed in this article is a bulk-driven (BD), single-stage, super-class-AB, adaptive biasing, functioning in the subthreshold region (ST) with an enormously low power supply of ± 0.25 V, providing high-gain. The input core of the OTA circuit is composed of adaptively biased BD differential input pairs based on flipped voltage follower (FVF), which drive in class-AB mode with a partial positive feedback (PPF) approach. The circuit additionally employs FVF and self-cascode (SC)-based low-power current mirror loads at its output to obtain significantly high gain and unity gain frequency. In addition, using adaptive loads based on source-degenerated metal oxide semiconductor (MOS) resistors raises dynamic current more efficiently, consequently improving the slew rate and unity gain frequency (UGF) without drawing additional power. Employing the cadence spectre tool and the UMC 0.18 μm complementary metal oxide semiconductor (CMOS) process technology, the designed OTA has been simulated. The simulation outcomes substantiate that the amplifier provides high open loop DC gain of 75 dB, 18.75 kHz UGF with a phase margin of 63.93º, and input-referred noise (IRN) of 0.734 µV/Hz0.5 at 1 kHz frequency. The proposed OTA consumes just 60.15 nW of power. The performance results confirmed that the proposed OTA circuit is appropriate in biomedical applications.
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Bazes, M. "Two novel fully complementary self-biased CMOS differential amplifiers." IEEE Journal of Solid-State Circuits 26, no. 2 (1991): 165–68. http://dx.doi.org/10.1109/4.68134.

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Dissertations / Theses on the topic "Self-biased differential amplifier"

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Chang, Yao-Chung, and 張耀中. "Analysis of Self-Biased Cross-coupled Fully-Differential CMOS Operational Amplifier and Applications." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/at8532.

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碩士<br>崑山科技大學<br>電子工程研究所<br>93<br>Nowadays mixed signal SoCs most have several analog circuits, which occupies large chip area. In analog circuits, operational amplifiers are usually the primary cells comprising passive parts. These passive parts are used to achieve high gain, high frequency, stability, and some other performance issues. Under these performance requests, designers must increase extra design circuitry. In nowadays, though CMOS process has reduced transistor dimensions, downsizing chip area is still an important topic. Most studies pay much design effort in this downsizing to integrate mixed signal system with digital system. Therefore, downsizing will lead the technology grows in reducing the cost while increasing SoC efficiency. In this thesis, we propose a low cost fully differential operational amplifier design method, which uses a novel self-biased cascode output stage and a high linearity cross-coupled input stage. We induce a general self-biased model for fully differential operational amplifiers in this thesis. In fact, according to this model, users can change their design at will with different considerations. Furthermore, the self-biased model achieves high common-mode rejectsion ration (CMRR) without common mode feedback (CMFB) circuit and it avoids extra biasing circuits. Consequently, this dramatically reduces the area wasting and achieves high performance. We apply the proposed model in a successful OpAmp design. In this example, we have made comparisons among a lot of analyses and experiments. We find that the analysis results and the experimental results are matched. Because we do not need the current mirrors, extra bias circuit, neither compensating circuit, the chip is fabricated within only a 84´67mm2 area by using TSMC 0.35μm standard CMOS technology. The chip area is only about 1/10 of the state-of-art OpAmps. Loaded with more than 100pF capacitance, the OpAmp possesses 60dB DC gain, 3v/μs slew-rate, 7.8Mhz unity-gain bandwidth, and -48dB THD. Because most voltage mode sigma delta modulator uses OpAmp as kernel element, we apply our OpAmp to complete the first-order sigma delta modulator. After applying our OpAmp in sigma delta modulator, we have successfully improved large dimension problem in the sigma delta modulator design. In the future, we can effectively improve the sigma-delta modulator performance by the analyses of the self-biased model
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Book chapters on the topic "Self-biased differential amplifier"

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Custódio, José Rui, Michael Figueiredo, Edinei Santin, and João Goes. "A CMOS Inverter-Based Self-biased Fully Differential Amplifier." In IFIP Advances in Information and Communication Technology. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11628-5_60.

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Conference papers on the topic "Self-biased differential amplifier"

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Figueiredo, M., E. Santin, J. Goes, R. Santos-Tavares, and G. Evans. "Two-stage fully-differential inverter-based self-biased CMOS amplifier with high efficiency." In 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010. IEEE, 2010. http://dx.doi.org/10.1109/iscas.2010.5536985.

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Kumar, Pattem Sampath, Vijayalakshmi Ch, Swapna Thouti, G. Prasanna Kumar, and N. Rajeswaran. "High Gain More Stable Self Biased Two Stage Differential Amplifier for Bio-signal Processing." In 2023 9th International Conference on Advanced Computing and Communication Systems (ICACCS). IEEE, 2023. http://dx.doi.org/10.1109/icaccs57279.2023.10112830.

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Abdelmoneum, Mohamed, David E. Duarte, and Greg Taylor. "A wide dynamic range self-biased fully differential operational amplifier for micro mechanical sensors and actuators circuitry." In 2010 Ninth IEEE Sensors Conference (SENSORS 2010). IEEE, 2010. http://dx.doi.org/10.1109/icsens.2010.5690386.

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Milovanovic, Vladimir, and Horst Zimmermann. "On fully differential and complementary single-stage self-biased CMOS differential amplifiers." In IEEE EUROCON 2013. IEEE, 2013. http://dx.doi.org/10.1109/eurocon.2013.6625248.

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Milovanovic, V., and H. Zimmermann. "Analyses of single-stage complementary self-biased CMOS differential amplifiers." In 2012 NORCHIP. IEEE, 2012. http://dx.doi.org/10.1109/norchp.2012.6403115.

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Cabrera, Fabian L. "Improved Self-Biased Differential Amplifiers Using Multiple-Vt CMOS Transistors." In 2023 7th International Symposium on Instrumentation Systems, Circuits and Transducers (INSCIT). IEEE, 2023. http://dx.doi.org/10.1109/inscit59673.2023.10258510.

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