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Journal articles on the topic 'Semiconductor chip protection'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Greguras, Fred M., and Neal M. Williams. "US semiconductor chip protection act." Computer Fraud & Security Bulletin 7, no. 7 (1985): 4–12. http://dx.doi.org/10.1016/0142-0496(85)90027-x.

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2

Chesser, James. "Semiconductor Chip Protection: Changing Roles for Copyright and Competition." Virginia Law Review 71, no. 2 (1985): 249. http://dx.doi.org/10.2307/1073018.

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3

SAMUELS, LINDA B., and JEFFREY M. SAMUELS. "SEMICONDUCTOR CHIP PROTECTION ACT OF 1984: AN ANALYTICAL COMMENTARY." American Business Law Journal 23, no. 4 (1985): 601–16. http://dx.doi.org/10.1111/j.1744-1714.1985.tb01584.x.

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4

Rose, Simone A. "Semiconductor Chips, Genes, and Stem Cells: New Wine for New Bottles?" American Journal of Law & Medicine 38, no. 1 (2012): 113–57. http://dx.doi.org/10.1177/009885881203800102.

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This Article analogizes early semiconductor technology and its surrounding economics with isolated genes, stem cells, and related bioproducts, and their surrounding economics, to make the case for sui generis (of its own class) intellectual property protection for isolated bioproducts. Just as early semiconductors failed to meet the patent social bargain requiring novelty and non-obviousness in the 1980s, isolated genes and stem cells currently fail to meet the patent bargain requirements of non-obviousness and eligible subject matter that entitle them to traditional intellectual property prot

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5

Yuan, Qi Ping, Tian Mei Zheng, Zheng Rong Tong, Xiu Feng Yang, and Ye Cao. "A Method of Stabilizing Semiconductor Laser Power." Applied Mechanics and Materials 130-134 (October 2011): 1370–73. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.1370.

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For the influence of the temperature and current, the power of semiconductor laser fluctuates constantly. So this paper comes up with a new method to solve this problem. The design of peripheral circuit contains two parts: temperature control and power control. The system of temperature control uses special laser temperature control chip, which realizes the accuracy of 0.01°C. The system of power control adopts hardware PI control, over-current protection, over-voltage protection, and temperature protection. Temperature compensation is added to the circuit, which realizes the accuracy of 0.01m

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6

Zhao, Qixin, Xiangyi Liu, Hanbing Wang, et al. "Research Progress in Corrosion Protection Technology for Electronic Components." Metals 13, no. 9 (2023): 1508. http://dx.doi.org/10.3390/met13091508.

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As a necessary part of all electronic devices, equipment and systems, electronic components play a vital role in the global economy. Since the corrosion of a single electronic component may directly affect the normal operation of the entire electronic system, the failure of electronic components has now become the most important cause of electrical system failure and has become a major obstacle to China’s transformation into a scientific and technological power. Therefore, it is urgent to study the corrosion failure process of electronic components and the means of effective protection. In thi

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7

Liang, Hailian, Jianfeng Li, Jun Sun, et al. "High-Voltage Electrostatic Discharge/Electrical Overstress Co-Protection Implementing Gradual-Triggered SCR and MOS-Stacked Configuration." Electronics 14, no. 6 (2025): 1076. https://doi.org/10.3390/electronics14061076.

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This paper proposes a monolithic electrostatic discharge/electrical overstress (ESD/EOS) co-protection device featuring gradual triggering by silicon-controlled rectifier (SCR) and metal–oxide semiconductor (MOS) structures, demonstrating enhanced voltage clamping and current-conducting capabilities. Compared with conventional PMOS-triggered SCR (PMOS-SCR) for ESD protection, the proposed dual-PMOS-triggered SCR (DPMOS-SCR) architecture within a compact area achieves monolithic ESD/EOS protection performance due to the strategic semiconductor structures integration. ESD measurement results sho

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Sung, Guo-Ming, Shih-Hao Chen, Venkatesh Choppa, and Chih-Ping Yu. "Hybrid Radio-Frequency-Energy- and Solar-Energy-Harvesting-Integrated Circuit for Internet of Things and Low-Power Applications." Electronics 14, no. 11 (2025): 2192. https://doi.org/10.3390/electronics14112192.

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This paper proposes a hybrid energy-harvesting chip that utilizes both radio-frequency (RF) energy and solar energy for low-power applications and extended service life. The key contributions include a wide input power range, a compact chip area, and a high maximum power conversion efficiency (PCE). Solar energy is a clean and readily available source. The hybrid energy harvesting system has gained popularity by combining RF and solar energy to improve overall energy availability and efficiency. The proposed chip comprises a matching network, rectifier, charge pump, DC combiner, overvoltage pr

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9

Sidiki, Tamim. "Polyamide 4T: A New Lead-Free Solderable Polymer Enabling Packaging Technology Through Micro Molding and LDS." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (2010): 001563–84. http://dx.doi.org/10.4071/2010dpc-wa43.

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The continuous trend towards convergence and miniaturization is recently generating significant interest in new technologies for Electronics. This requires the integration of Semiconductors and Magnetics, two entirely different industries with different players in the value chain. In this paper, we demonstrate, a packaging technology which allows three dimensional stacking of Magnets and Semiconductors. We realized the integration of a Semiconductor chip - which provides protection against electro static discharge (ESD) – and a common mode filter (CMF) into one thermoplastic package. For the f

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10

Xu, Yan Hui, and Dan Tong Zhang. "Research on One Kind of Intellectualization High Accuracy Digital Adjustment Direct Source." Applied Mechanics and Materials 599-601 (August 2014): 608–11. http://dx.doi.org/10.4028/www.scientific.net/amm.599-601.608.

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The power source uses the digital adjustment, the closed loop real-time monitoring.The output precision is vary high. It also has both the dual over-load protection and alarm, which is suitable especially in each kind situation of the high accuracy request.This design intellectualization direct-current power supply uses the self-restraint keyboard entry. The system of intellectualization high accuracy digital adjustmen direct source contains D/A module and A/D module . D/A module adopts low-priced 8 bits DA chip. DAC0832 is a electric current exports type 8 bits D/A converter , adopting to rev

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11

Pharkphoumy, Sakhone, Vallivedu Janardhanam, Moon-Ho Lee, et al. "Development of Semiconductor Bridge Ignition Chip Device with Robust ESD Protection of TVS Diodes." JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 18, no. 6 (2018): 677–84. http://dx.doi.org/10.5573/jsts.2018.18.6.677.

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12

Furuno, Kenta, Shigeyuki Yamashita, Yoji Wakayama, Naoya Saiki, and Shinya Takyu. "A Novel Dicing tape for WLCSP Using Stealth Dicing Through Dicing tape and Back Side Protection-Film." International Symposium on Microelectronics 2019, no. 1 (2019): 000333–37. http://dx.doi.org/10.4071/2380-4505-2019.1.000333.

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Abstract Market demand of information terminals for Internet of Things (IoT) is increasing. So market situation requires various semiconductor packages. Wafer Level Chip Size Package (WLCSP) is one of the most important technology among them. We selected stealth dicing (SD) as a manufacturing method for WLCSP because the cutting speed is higher than blade dicing and the yield of semiconductor chip is higher than blade dicing. But, SD process still has some technical issues. In some cases, when the laser is irradiated from circuit side (from surface side of Si wafer), the metal pattern in circu

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13

Hackler, Doug, and Ed Prack. "Advanced Protected Fan-In WLCSP." International Symposium on Microelectronics 2021, no. 1 (2021): 000089–92. http://dx.doi.org/10.4071/1085-8024-2021.1.000089.

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ABSTRACT With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to single sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)

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Hirosawa, Ryuji, and Junya Kusunoki. "Latest technology of wafer coating material for advanced packages." International Symposium on Microelectronics 2021, no. 1 (2021): 000108–11. http://dx.doi.org/10.4071/1085-8024-2021.1.000108.

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Abstract In recent years, as electronic devices such as smartphones become more functional, more compact, and lower cost, many semiconductor makers are studying the packages such as WLP (Wafer Level Package) having re-distribution layer (RDL).With the miniaturization and the increase in the number of pins of a semiconductor package, the method of conduction between a semiconductor chip and an external electrode has been changed from wire connection to bump connection and RDL. And the application of a wafer coating material is also required to have higher functions from a buffer coat film to bu

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15

Li, Fuxing, Changchun Chai, Yuqian Liu, Yanxing Song, Lei Wang, and Yintang Yang. "Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment." Micromachines 14, no. 3 (2023): 600. http://dx.doi.org/10.3390/mi14030600.

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The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures. In this paper, the mixed TCAD model of the ESD protection circuit is built and simulated, and the negative transmission line pulse (TLP) injection damage experiment is carried out on the CD4069UBC chip. The circuit model consists of three-dimensional shallow trench isolation (STI) diode TCAD models and a three-dimensional multi-gate Complementary Metal-Oxide-Semiconductor (CMOS) inverter TCAD mode

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16

Paynter, Leland S. "Networking Software Copyrights and the Semiconductor Chip Protection Act: A Study of Legal Protection for Application Specific Integrated Circuit Technology." Indiana Law Review 27, no. 2 (1993): 415–48. http://dx.doi.org/10.18060/3067.

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17

Liu, Wei, Xiao-ming Ren, Rui-zhen Xie, et al. "Fabrication and performance of a nickel-chromium (NiCr) igniter integrated with TVS diode for ESD protection." AIP Advances 13, no. 3 (2023): 035207. http://dx.doi.org/10.1063/5.0137883.

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The NiCr igniter is a key element of MEMS-based electro-explosive device (mEED), while electrostatic discharge (ESD) may excite the igniter accidentally. To protect the NiCr igniter from damage by ESD, a novel NiCr igniter by integrating the igniter onto a TVS diode based substrate was designed and fabricated through semiconductor technology. The microscope photograph, resistivity, breakdown voltage, firing performance, and ESD protection ability were tested. The results show that the surface of the chip is smooth, the edges of key structures are clear, and there are no major scratches, cracks

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18

Zhang, Xueping, Huan Zou, Rong Chen, and Zhenrong Liu. "Design of Laser-Powered Opto-Electrical Current Transformer and Its Application in Electrical Automation of Substations." Journal of Nanoelectronics and Optoelectronics 19, no. 5 (2024): 554–63. http://dx.doi.org/10.1166/jno.2024.3605.

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The novel power equipment represented by the Opto-Electrical Current Transformer (OECT) possesses unparalleled advantages compared to traditional Current Transformers (CTs), rendering it with vast potential in power systems. In the design of OECT, this study employs laser power supply and focuses on the overall perspective, particularly the design of the laser power supply module and the optical fiber digital transmission module. The laser power supply module selects a high-power semiconductor laser to provide power to the circuit, incorporating line filters, thermistor resistors, and a laser

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19

Liao, Xiwei. "Research on the Reliability of Semiconductor Chips under Extreme Conditions and Strategies." Applied and Computational Engineering 162, no. 1 (2025): None. https://doi.org/10.54254/2755-2721/2025.gl24395.

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Semiconductor chips face multiple challenges such as high temperatures, radiation, and mechanical vibrations in extreme environment applications like aerospace, automotive electronics, and nuclear energy. Their performance stability is crucial for system reliability. This research systematically analyzes the failure modes of chips under the combined action of multiple fields including temperature, radiation, and humidity. By adopting a technical approach that integrates in-situ testing, numerical simulation, and failure analysis, it reveals the primary failure mechanisms, such as gate oxide la

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20

Ryabov, Kirill I. "The Specter of Digital Rights." Theoretical and Applied Law, no. 3 (June 7, 2021): 61–63. https://doi.org/10.22394/2686-7834-2021-3-61-63.

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In the article, the author examines the problem of the impact of technological changes on the legal regulation of public relations, namely the development of digital technologies, how significant such an impact turned out to be and whether, in this regard, significant changes in the principles and mechanisms of legal regulation are required. It is asserted in the article that the problem how to adapt existing legal forms in order to address inevitable changes in public relationships (does not matter what the cause of these changes is: the so called “digitalization” or something els

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21

Saha, Debasri, and Susmita Sur-Kolay. "SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection." VLSI Design 2011 (April 5, 2011): 1–10. http://dx.doi.org/10.1155/2011/731957.

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Increased design complexity, shrinking design cycle, and low cost—this three-dimensional demand mandates advent of system-on-chip (SoC) methodology in semiconductor industry. The key concept of SoC is reuse of the intellectual property (IP) cores. Reuse of IPs on SoC increases the risk of misappropriation of IPs due to introduction of several new attacks and involvement of various parties as adversaries. Existing literature has huge number of proposals for IP protection (IPP) techniques to be incorporated in the IP design flow as well as in the SoC design methodology. However, these are quite

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22

Chen, Shuai, and Lei Wang. "Transformable Electronics Implantation in ROM for Anti-Reverse Engineering." International Journal of High Speed Electronics and Systems 28, no. 03n04 (2019): 1940021. http://dx.doi.org/10.1142/s0129156419400214.

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The protection of intellectual property (IP) is increasingly critical for IP vendors in the semiconductor industry. Read Only Memories (ROMs) serve as important non-volatile memory in various hardware systems to store predefined data and programs, which is critical to IP protection. Its pre-determined layout pattern makes unauthorized data extraction through chip-level reverse engineering easy to carry out. Advanced reverse engineering techniques can physically disassemble the chip and derive the IPs precisely at a much lower cost than the value of IP design that chips carry. This invasive har

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23

Tien, Chu-Yeh, Ping-Yu Kuei, and Liann-Be Chang. "Improved surge protection of flip-chip gallium nitride-based HEMTs by metal-semiconductor-metal two-dimensional electron gas varactor." Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 33, no. 2 (2015): 021401. http://dx.doi.org/10.1116/1.4914949.

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24

Dasgupta, Aritra, Sudipta Paria, and Swarup Bhunia. "HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction." IACR Transactions on Cryptographic Hardware and Embedded Systems 2025, no. 3 (2025): 781–805. https://doi.org/10.46586/tches.v2025.i3.781-805.

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Hardware intellectual property (IP) blocks have been subjected to various forms of confidentiality and integrity attacks in recent years due to the globalization of the semiconductor industry. System-on-chip (SoC) designers are now considering a zero-trust model for security, where an IP can be attacked at any stage of the manufacturing process for piracy, cloning, overproduction, or malicious alterations. Hardware redaction has emerged as a promising countermeasure to thwart confidentiality and integrity attacks by untrusted entities in the globally distributed supply chain. However, existing

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25

KADIRE, SUMALATA, V. SAI ANJANI, P AKSHITHA, and V. RAMYA SRI. "SECURITY ANALYSIS AND EXPLOITATION OF IC CHIP LEVEL COUNTER QUANTITY AGAINST BODILY OCCURRENCES." Industrial Engineering Journal 53, no. 12 (2024): 154–61. https://doi.org/10.36893/iej.2024.v53i12.020.

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This article addresses the growing concern of security vulnerabilities in hardware systems, particularly in the context of integrated circuit (IC) chips used in cryptographic applications, which are increasingly susceptible to adversarial physical attacks in real-world environments. These attacks, often targeting the physical integrity of ICs, exploit weaknesses in both the design and manufacturing processes of cryptographic circuits. The paper provides a comprehensive overview of these threats, focusing on various physical attack methods, such as sidechannel attacks, electromagnetic (EM) atta

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Ker, Ming-Dou, and Tang-Kui Tseng. "Active Electrostatic Discharge (ESD) Device for On-Chip ESD Protection in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductor (CMOS) Process." Japanese Journal of Applied Physics 43, no. 1A/B (2003): L33—L35. http://dx.doi.org/10.1143/jjap.43.l33.

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27

Tamburrino, A., G. Claps, F. Cordella, F. Murtas, and D. Pacella. "Timepix3 detector for measuring radon decay products." Journal of Instrumentation 17, no. 06 (2022): P06009. http://dx.doi.org/10.1088/1748-0221/17/06/p06009.

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Abstract The present work is focused on the characterization of a Timepix3 (TPX3) based test system for the identification of particles produced by the complex decay chain of 222Rn. The detector used is composed of a pixelated Cadmium Telluride (CdTe) semiconductor (500 μm thick) bump-bonded on an ASIC TPX3 chip. Measurements were carried out at the NIXT Laboratory (ENEA Frascati) using radioactive sources and exploiting the presence of natural radon gas by collecting its decay products on the sensor surface. Estimation of the radon gas risk is one of the most important problems in radiation p

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28

Kim, Seongbin, and Sinsu Kyoung. "On-Chip Gate Electrostatic Discharge Protection Design for 900 V Power Metal Oxide Semiconductor Field Effect Transistor Using Punch-Through Diode Without Degrading Switching Loss." Journal of Nanoscience and Nanotechnology 19, no. 10 (2019): 6781–84. http://dx.doi.org/10.1166/jnn.2019.17121.

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29

Weingarten, Jens, Claus Maximilian Bäcker, Johannes Esser, et al. "Proton radiography for adaptive radiotherapy using ATLAS FE-I4 detectors." Journal of Instrumentation 20, no. 06 (2025): C06031. https://doi.org/10.1088/1748-0221/20/06/c06031.

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Abstract Due to the physical principles of the energy deposition of charged particles in matter, cancer treatment using proton therapy allows more conformal dose deposition in the tumour with respect to conventional photon radiotherapy, which leads to better protection of healthy tissue. At the same time, the maximum dose deposition at the end of the proton trajectory is more sensitive to uncertainties in the range of the protons. A significant source of these uncertainties are inter-fractional anatomical changes in the patient during treatment. Adaptive radiotherapy, where the treatment plan

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30

Ke, Xing, Fengmei Li, Zhenyang Zhao, et al. "(Digital Presentation) Advanced Process Control of Dual Patterns for FinFET Mass Production." ECS Meeting Abstracts MA2022-01, no. 29 (2022): 1270. http://dx.doi.org/10.1149/ma2022-01291270mtgabs.

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ABSTRACT Advanced Process Control (APC) has been widely applied in state-of-the-art semiconductor industries for the everlasting pursuit of cycle time reduction, higher yield and zero scrap. Inline metrology is thus valuable input feeds for the improvement of wafer-to-wafer and within-wafer CD variations originated from either abnormality or noise of different processes. Implementing a suitable APC scheme to process flow remains a challenging task for engineers. In most cases, it is enough to implement the APC to only one single pattern on Chip. However, for multi-purpose chip design, the CD c

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31

Bagul, Priyanka, and Vandana Inamdar. "Hardware Obfuscation Based Watermarking Technique for IPR Ownership Identification." International Journal of Reconfigurable Computing 2023 (July 3, 2023): 1–13. http://dx.doi.org/10.1155/2023/4550758.

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As the reuse of IP cores or the development of frequently used hardware modules is gaining more attention in the semiconductor industry, the misappropriation of the owner’s identity is a rising concern. Therefore, imprinting the owner’s identity in the form of a watermark or signature on the IP core is essential to avoid intellectual property right (IPR) infringement. In view of this, a watermarking technique is proposed in the present manuscript. A constraint-based dynamic watermarking method to generate the owner’s signature is proposed in conjunction with the logic encryption-based hardware

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32

Wicht, Sebastian, Sandra Gozdzik, Kavana Mandya Sreenivasa Setty, Aarushee Rangra, and Niclas Heise. "(Invited) Micro-Transfer-Printing: A Novel Technology for Volume D2W Integration." ECS Meeting Abstracts MA2023-02, no. 33 (2023): 1608. http://dx.doi.org/10.1149/ma2023-02331608mtgabs.

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In the past decade, the semiconductor industry has witnessed an ever-increasing demand in wafer-level integration and packaging technologies driven by increased requirements on functionality, performance, and efficiency. As one of the world’s leading specialty foundry groups for analog/mixed semiconductor technologies and more than thirty years of experience in volume manufacturing for automotive, industrial and medical applications, the X-FAB group has recognized this trend and broadened its offer accordingly. New integration techniques like wafer bonding, through-passivation vias (TSVs) proc

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33

Poluektov, Aleksandr, Roman Medvedev, and Konstantin Zolnikov. "Simulation of the influence of electromagnetic fields on microcircuits." Modeling of systems and processes 17, no. 1 (2024): 129–36. http://dx.doi.org/10.12737/2219-0767-2024-17-1-129-136.

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The article examines the influence of electromagnetic fields on radiation effects in microcircuits, describes the influence of electromagnetic fields depending on the distance from the center of the explosion, and evaluates the degree of protection of microcircuits. Assessments of the impact of electromagnetic fields created by gamma radiation on CMOS microcircuits are considered, the physical process, a mathematical model of the occurrence of leakage current, charge loss, transistor switching speed and electronic mobility are described. The methods of protecting CMOS semiconductors from the e

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DiMarino, Christina, Benjamin Albano, Boyan Wang, and Yuhao Zhang. "(Invited) Considerations and Strategies for High-Temperature Ultra-Wide Bandgap Gallium Oxide Power Modules." ECS Meeting Abstracts MA2022-01, no. 31 (2022): 1320. http://dx.doi.org/10.1149/ma2022-01311320mtgabs.

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There is a compelling need for high-density power electronic components and systems capable of operation at high ambient temperatures in automotive, aerospace, and down-hole applications. However, these needs are challenging the fundamental limit of silicon-based converters. While wide-bandgap (WBG) power semiconductors, particularly silicon carbide (SiC) and gallium nitride (GaN), have become promising alternatives to silicon (Si), they show diminished performance benefits at high temperatures. In the last several years, an ultra-wide-bandgap (UWBG) semiconductor, gallium oxide (Ga2O3), has e

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35

Wang, Baron, Andrea S. Chen, and Randy H. Y. Lo. "Characteristics of Organic-Based Thermal Interface Materials Suitable for High Temperature Operation." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, HiTen (2019): 000041–44. http://dx.doi.org/10.4071/2380-4491.2019.hiten.000041.

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Abstract Historically, for semiconductors subject to standard operating temperatures--which tend not to exceed 125°C--the Tg (glass transition temperatures) of the organic packaging materials protecting the chips is usually around 175°C. Given that, when it comes to electronics operating at high temperatures—typically an environment where the ambient temperature exceeds 200°C—the use of organic materials is generally prohibited due to rapid degradation. At those elevated temperatures, the packaging materials selected are generally composed of metals and ceramics but these materials come with t

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36

Sukumaran Nair, Arya, Peter Czurratis, and Denis Bogucanin. "Application of Machine Learning Algorithm for Defect Analysis in Semiconductors Using High Resolved Scanning Acoustic Microscopy." ECS Meeting Abstracts MA2023-02, no. 33 (2023): 1590. http://dx.doi.org/10.1149/ma2023-02331590mtgabs.

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Scanning Acoustic Microscopy is a dedicated powerful technology in NDT to analyze and characterize bonded interfaces for different technologies. As the complexity of the semiconductor package grows, even seemingly insignificant faults become quite important. Main applications include detection of voids, inclusions and delaminated areas in bonding interfaces and thickness variations in layer structures. The SAM operates with the pulse reflection method. The acoustic lens transforms high frequency electromagnetic vibrations that are transmitted inside the lens as a planar parallel wave field. Th

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Elenius, Peter. "Flip Chip and Wafer Level Packaging - Past, Present and Future." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (2011): 000406–33. http://dx.doi.org/10.4071/2011dpc-keynote2_e_g.

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Flip chip packaging was developed nearly 50 years ago by IBM for the purposes of improved reliability and automated semiconductor assembly. For the first 35 years the use of flip chip technology was limited to a few large IDMs and automotive companies. Beginning fifteen years ago, companies providing flip chip bumping services were established. The primary reason for adoption of flip chip in the 1990s was to enable higher I/O count chips and to improve the power and ground distribution through the use of area array interconnects. Beginning in the early 2000s high speed serial links and other I

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38

Li, Hui, Chunyang Feng, Jianjun Luo, et al. "Research on the electro-magnetic protection technique of SCB bridge based on vertical punch through PN junction." AIP Advances 14, no. 2 (2024). http://dx.doi.org/10.1063/5.0191824.

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Pyrotechnic device is the key initiating component of weapon system, and its function reliability will directly affect the triggering of detonation and actuation mechanism. In order to enhance the survival ability of pyrotechnic device in intricate electromagnetic interference environment, it is necessary to carry out in-depth research on the electromagnetic protection technique of pyrotechnic device. In this paper, a new electromagnetic protection circuit based on vertical punch through PN junction device is proposed, which monolithically integrates the circuit with polysilicon semiconductor

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39

Hackler, Doug, and Ed Prack PhD. "Protected Wafer Level Chip Scale Packaging (P-WLCSP)." IMAPSource Proceedings 2022, Issue 1 (2023). http://dx.doi.org/10.4071/001c.74767.

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With the advent of bumped die, new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip), CBGA (ceramic ball grid array), and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), was built on the wafer with no active side protection, evolving to single sided protection from a package built on the wafer3 , which transitioned to redistribution PSB (passivation stress buffer)4 . PSBs we

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Cheng, Wenzheng, Feiyang Zhao, Tianyi Zhang, Yongjie He, and Hao Zhu. "A review of ultra-wide-bandgap semiconductor radiation detector for high-energy particles and photons." Nanotechnology, February 21, 2025. https://doi.org/10.1088/1361-6528/adb8f2.

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Abstract Radiation detectors have gained significant attention due to their extensive applications in high-energy physics, medical diagnostics, aerospace, and nuclear radiation protection. Advances in relevant technologies have made the drawbacks of traditional semiconductor detectors, including high leakage currents and instability, increasingly apparent. Ga₂O₃, diamond, and BN represent a new generation of semiconductor materials following GaN and SiC, offering wide bandgaps of around 5 eV. These ultra-wide bandgap (UWBG) semiconductors demonstrate excellent properties, including ultra-low d

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Hackler, Doug, and Ed Prack. "Thin and Ultra-thin Sidewall Protected P-WLCSP." IMAPSource Proceedings 2023, DPC (2023). http://dx.doi.org/10.4071/001c.90211.

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Diversity in packaging for a strong supply chain requires higher performance and lower cost processes for new manufacturers. Six-side protected, aka “6S or fully protected”, CSP is an emerging and rapidly growing market. Fully protected CSP (without substrates or lead-frames) was first implemented with processes such as M-series and eWLB. These processes require costly and complex die reconstitution, expensive tapes, molding, and other operations most common to FO to obtain 6-side die protection. These steps can be eliminated in a wafer level process to provide high-performance low-cost P-WLCS

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Hackler, Doug, and Ed Prack. "P-WLCSP: 6-Side Protected WLCSP." IMAPSource Proceedings 2022, DPC (2023). http://dx.doi.org/10.4071/001c.91169.

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The first silicon demonstration of 300mm P-WLCSP was introduced in 2021 at the 54th International Symposium on Microelectronics. This paper reports further developments and new test results for this low cost WLCSP approach to fully protected CSP. The paper briefly summarizes the evolution of protected CSP technology evolution as an introduction for a more extensive discussion of P-WLCSP. With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package) and for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For lo

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Li, Xunyu, Zijin Pan, Weiquan Hao, Runyu Miao, Zijian Yue, and Albert Wang. "Enhancing chip performance and reliability by CMOS+X technologies." Applied Physics Reviews 11, no. 2 (2024). http://dx.doi.org/10.1063/5.0209828.

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Performance, reliability, and costs are the three core attributes of any integrated circuits (IC) and microelectronics system products. Continuous advances of microsystem chips have been made possible by relentless physical scaling-down in IC technologies, predominantly in complementary metal-oxide-semiconductor (CMOS). Rapid ending of Moore's Law calls for smart futuristic chips, toward which CMOS+X heterogeneous integration emerges as the main and viable pathway where X represents various innovative, nontraditional technologies and devices to be hetero-integrated into Si CMOS platform to del

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Hsieh, Timothy T. "A Bridge Between Copyright and Patent Law: Towards a Modern-Day Reapplication of the Semiconductor Chip Protection Act." SSRN Electronic Journal, 2017. http://dx.doi.org/10.2139/ssrn.3029116.

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Kumar, Abhishek, Manoj Gupta, Prakash Pitchappa, et al. "Phototunable chip-scale topological photonics: 160 Gbps waveguide and demultiplexer for THz 6G communication." Nature Communications 13, no. 1 (2022). http://dx.doi.org/10.1038/s41467-022-32909-6.

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AbstractThe revolutionary 5G cellular systems represent a breakthrough in the communication network design to provide a single platform for enabling enhanced broadband communications, virtual reality, autonomous driving, and the internet of everything. However, the ongoing massive deployment of 5G networks has unveiled inherent limitations that have stimulated the demand for innovative technologies with a vision toward 6G communications. Terahertz (0.1-10 THz) technology has been identified as a critical enabler for 6G communications with the prospect of massive capacity and connectivity. None

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Pulivarthy, Padmaja. "AWS Data Lakes, Machine Learning, and AI-Driven Insights for Efficiency, Quality, and Innovation Transforming Semiconductor Manufacturing." International Journal For Multidisciplinary Research 4, no. 6 (2022). https://doi.org/10.36948/ijfmr.2022.v04i06.47401.

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Driving everything from smartphones and autonomous cars to artificial intelligence and high-performance computing systems, the semiconductor industry is pillar of modern technology. Still, the sector is suffering increasing pains in the form of increased chip design complexity, better product quality, faster time-to--market, and more demand for reasonably priced manufacturing. In the middle of these challenges, old models of manufacturing—marked by isolated processes, fragmented data systems, and rigid control mechanisms—are inadequate. This article explores how the convergence of Amazon Web S

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Windsor, Aaron J., Jeremy C. Clark, George McMurdy, et al. "Viability of HFO-1234ze(E) (trans-1,3,3,3-tetrafluoropropene) as a low global warming potential silicon dioxide etch gas." Journal of Vacuum Science & Technology B 43, no. 2 (2025). https://doi.org/10.1116/6.0004194.

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The American Innovation and Manufacturing Act, enacted by Congress in 2020, grants the U.S. Environmental Protection Agency the authority to phase down the production and consumption of hydrofluorocarbons (HFCs), thereby reducing carbon emissions and addressing the negative environmental impact of HFCs. To comply, the semiconductor industry, which uses a variety of processing gases that contain HFCs, must transition to alternative gases in chip manufacturing, particularly in etching processes. Many of the HFC etch gases in current use have high global warming potentials (GWPs). One potential a

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Johnson, Barry C. "Overview of High Performance Packaging Materials." MRS Proceedings 203 (1990). http://dx.doi.org/10.1557/proc-203-209.

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ABSTRACTHigh Performance Integrated Circuits form the basic building blocks of modern electronic systems that are designed to process ever larger numbers of electrical signals at greater signal velocity and fidelity. In such applications, each circuit must be packaged in order to provide it with necessary mechanical support, environmental protection, electrical interconnection and thermal cooling. The package, however, can also impose certain constraints on the chip. It can degrade electrical performance, add size and weight, introduce reliability problems and increase cost. Thus, packaging ca

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Behrmann, Ole, Niklas Kyoushi, Mani Teja Bodduluri, Thomas Lisec, Stefan Schröder, and Björn Gojdka. "Wafer-level chip-scale packaging of MEMS environmental sensors by functionalized porous PowderMEMS® micro-filters." Journal of Micromechanics and Microengineering, January 6, 2025. https://doi.org/10.1088/1361-6439/ada61e.

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Abstract MEMS environmental sensors, including pressure, gas, and humidity sensors, require protection from mechanical damage, particle exposure, and condensing moisture, while maintaining their ability to exchange gases with the environment. This work introduces a novel packaging approach for MEMS environmental sensors using substrate-embedded filters made from microfine powders through PowderMEMS® microfabrication technology. The study demonstrates the successful fabrication of gas permeable, functionalized PowderMEMS® filters on 200 mm Si-wafers for wafer-level packaging of MEMS environment

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Hackler, Doug, and Ed Prack. "P-WLCSP Advanced Packaging Enabling Next Generation Medical Device Applications." IMAPSource Proceedings 2024, DPC (2025). https://doi.org/10.4071/001c.129080.

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Flexible hybrid microelectronics systems are being introduced for wearables, implants, drug delivery, human-machine interfaces, rapid diagnostics and more. These novel medical devices rely on leading-edge thin and flexible microelectronics. Semiconductor-on-Polymer (SoP) 300mm SoP-TM, is a new protected wafer level chip scale advanced packaging process (P-WLCSP) producing six-side (6S) die protection without use of reconstitution. The process produces the thinnest and only physically flexible packaged ICs in the world. SoP packaged devices are currently being adopted in a variety of new medica

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