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1
Qin, Guoshuai, Chunsheng Lu, Xin Zhang, and Minghao Zhao. "Electric Current Dependent Fracture in GaN Piezoelectric Semiconductor Ceramics." Materials 11, no. 10 (2018): 2000. http://dx.doi.org/10.3390/ma11102000.
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In this paper, the fracture behavior of GaN piezoelectric semiconductor ceramics was investigated under combined mechanical and electric loading by using three-point bending tests and numerical analysis. The experimental results demonstrate that, in contrast to traditional insulating piezoelectric ceramics, electric current is a key factor in affecting the fracture characteristics of GaN ceramics. The stress, electric displacement, and electric current intensity factors were numerically calculated and then a set of empirical formulae was obtained. By fitting the experimental data, a fracture criterion under combined mechanical and electrical loading was obtained in the form of an ellipsoid function of intensity factors. Such a fracture criterion can be extended to predict the failure behavior of other piezoelectric semiconductors or devices with a crack, which are useful in their reliability design and applications.
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Morgan, Adam, Ankan De, Haotao Ke, et al. "A Robust, Composite Packaging Approach for a High Voltage 6.5kV IGBT and Series Diode." International Symposium on Microelectronics 2015, no. 1 (2015): 000359–64. http://dx.doi.org/10.4071/isom-2015-wp17.
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The main motivation of this work is to design, fabricate, test, and compare an alternative, robust packaging approach for a power semiconductor current switch. Packaging a high voltage power semiconductor current switch into a single power module, compared to using separate power modules, offers cost, performance, and reliability advantages. With the advent of Wide-Bandgap (WBG) semiconductors, such as Silicon-Carbide, singular power electronic devices, where a device is denoted as a single transistor or rectifier unit on a chip, can now operate beyond 10kV–15kV levels and switch at frequencies within the kHz range. The improved voltage blocking capability reduces the number of series connected devices within the circuit, but challenges power module designers to create packages capable of managing the electrical, mechanical, and thermal stresses produced during operation. The non-sinusoidal nature of this stress punctuated with extremely fast changes in voltage and current, with respect to time, leads to non-ideal electrical and thermal performance. An optimized power semiconductor series current switch is fabricated using an IGBT (6500V/25A die) and SiC JBS Diode (6000V/10A), packaged into a 3D printed housing, to create a composite series current switch package (CSCSP). The final chosen device configuration was simulated and verified in an ANSYS software package. Also, the thermal behavior of such a composite package was simulated and verified using COMSOL. The simulated results were then compared with empirically obtained data, in order to ensure that the thermal ratings of the power devices were not exceeded; directly affecting the maximum attainable frequency of operation for the CSCSP. Both power semiconductor series current switch designs are tested and characterized under hard switching conditions. Special attention is given to ensure the voltage stress across the devices is significantly reduced.
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Zhou, Dao, Yingzhou Peng, Francesco Iannuzzo, Michael Hartmann, and Frede Blaabjerg. "Thermal Mapping of Power Semiconductors in H-Bridge Circuit." Applied Sciences 10, no. 12 (2020): 4340. http://dx.doi.org/10.3390/app10124340.
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In this paper, a universal H-bridge circuit is used as a loading emulator to investigate the loss and thermal models of the power semiconductor. Based on its operation principle and modulation method, the dominating factors’ (e.g., power factor, loading current, fundamental frequency, and switching frequency) impact on the thermal stress of power semiconductors is considerably evaluated. The junction temperature in terms of the mean value and its swing is verified by using Piecewise Linear Electrical Circuit Simulation (PLECS) simulation and experimental setup. It helps to allocate the loading condition in order to obtain the desired thermal stress.
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Chen, Jun, Takashi Sekiguchi, Masami Takase, et al. "Electron-Beam-Induced Current Study of Breakdown Behavior of High-K Gate MOSFETs." Solid State Phenomena 156-158 (October 2009): 461–66. http://dx.doi.org/10.4028/www.scientific.net/ssp.156-158.461.
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We report a dynamic and microscopic investigation of electrical stress induced defects in metal-oxide-semiconductor (MOS) devices with high-k gate dielectric by using electron-beam induced current (EBIC) technique. The correlation between time-dependent dielectric breakdown (TDDB) characteristics and EBIC imaging of breakdown sites are found. A systematic study was performed on pre-existing and electrical stress induced defects. Stress-induced defects are related to the formation of electron trapping defects. The origin of pre-existing defects is also discussed in terms of oxygen vacancy model with comparing different gate electrodes.
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Harimon, M. A., A. Ponniran, A. N. Kasiran, and H. H. Hamzah. "A Study on 3-phase Interleaved DC-DC Boost Converter Structure and Operation for Input Current Stress Reduction." International Journal of Power Electronics and Drive Systems (IJPEDS) 8, no. 4 (2017): 1948. http://dx.doi.org/10.11591/ijpeds.v8.i4.pp1948-1953.
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This paper analyses a 3-phase interleaved DC-DC boost converter for the conversion of low input voltage with high input current to higher DC output voltage. The operation of the 3-phase interleaved DC-DC boost converter with multi-parallel of boost converters is controlled by interleaved of switching signals with 120 degrees phase-shifted. Therefore, with this circuit configuraion, high input current is evenly shared among the parallel units and consequently the current stress is reduced on the circuit and semiconductor devices and contributes reduction of overall losses. The simulation and hardware results show that the current stress and the semiconductor conduction losses were reduced approximately 33% and 32%, respectively in the 3-phase interleaved DC-DC boost converter compared to the conventional DC-DC boost converters. Furthermore, the use of interleaving technique with continuous conduction mode on DC-DC boost converters is reducing input current and output voltage ripples to increase reliability and efficiency of boost converters.
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Kaiser, Daniel, Swapnadip Ghosh, Sang M. Han, and Talid Sinno. "Modeling and simulation of compositional engineering in SiGe films using patterned stress fields." Molecular Systems Design & Engineering 1, no. 1 (2016): 74–85. http://dx.doi.org/10.1039/c6me00017g.
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Semiconductor alloys such as silicon–germanium (SiGe) offer attractive environments for stress-driven compositional engineering of quantum-confined structures that are the basis for a host of current and future optoelectronic devices.
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Meraj, Sheikh Tanzim, Nor Zaihar Yahaya, Molla Shahadat Hossain Lipu, et al. "A Hybrid Active Neutral Point Clamped Inverter Utilizing Si and Ga2O3 Semiconductors: Modelling and Performance Analysis." Micromachines 12, no. 12 (2021): 1466. http://dx.doi.org/10.3390/mi12121466.
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In this paper, the performance of an active neutral point clamped (ANPC) inverter is evaluated, which is developed utilizing both silicon (Si) and gallium trioxide (Ga2O3) devices. The hybridization of semiconductor devices is performed since the production volume and fabrication of ultra-wide bandgap (UWBG) semiconductors are still in the early-stage, and they are highly expensive. In the proposed ANPC topology, the Si devices are operated at a low switching frequency, while the Ga2O3 switches are operated at a higher switching frequency. The proposed ANPC mitigates the fault current in the switching devices which are prevalent in conventional ANPCs. The proposed ANPC is developed by applying a specified modulation technique and an intelligent switching arrangement, which has further improved its performance by optimizing the loss distribution among the Si/Ga2O3 devices and thus effectively increases the overall efficiency of the inverter. It profoundly reduces the common mode current stress on the switches and thus generates a lower common-mode voltage on the output. It can also operate at a broad range of power factors. The paper extensively analyzed the switching performance of UWBG semiconductor (Ga2O3) devices using double pulse testing (DPT) and proper simulation results. The proposed inverter reduced the fault current to 52 A and achieved a maximum efficiency of 99.1%.
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Daus, Alwin, Songyi Han, Stefan Knobelspies, Giuseppe Cantarella, and Gerhard Tröster. "Ge2Sb2Te5 p-Type Thin-Film Transistors on Flexible Plastic Foil." Materials 11, no. 9 (2018): 1672. http://dx.doi.org/10.3390/ma11091672.
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In this work, we show the performance improvement of p-type thin-film transistors (TFTs) with Ge 2 Sb 2 Te 5 (GST) semiconductor layers on flexible polyimide substrates, achieved by downscaling of the GST thickness. Prior works on GST TFTs have typically shown poor current modulation capabilities with ON/OFF ratios ≤20 and non-saturating output characteristics. By reducing the GST thickness to 5 nm, we achieve ON/OFF ratios up to ≈300 and a channel pinch-off leading to drain current saturation. We compare the GST TFTs in their amorphous (as deposited) state and in their crystalline (annealed at 200 °C) state. The highest effective field-effect mobility of 6.7 cm 2 /Vs is achieved for 10-nm-thick crystalline GST TFTs, which have an ON/OFF ratio of ≈16. The highest effective field-effect mobility in amorphous GST TFTs is 0.04 cm 2 /Vs, which is obtained in devices with a GST thickness of 5 nm. The devices remain fully operational upon bending to a radius of 6 mm. Furthermore, we find that the TFTs with amorphous channels are more sensitive to bias stress than the ones with crystallized channels. These results show that GST semiconductors are compatible with flexible electronics technology, where high-performance p-type TFTs are strongly needed for the realization of hybrid complementary metal-oxide-semiconductor (CMOS) technology in conjunction with popular n-type oxide semiconductor materials.
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Yum, J. H., J. Oh, Todd W. Hudnall, C. W. Bielawski, G. Bersuker, and S. K. Banerjee. "Comparative Study ofSiO2,Al2O3, and BeO Ultrathin Interfacial Barrier Layers in Si Metal-Oxide-Semiconductor Devices." Active and Passive Electronic Components 2012 (2012): 1–7. http://dx.doi.org/10.1155/2012/359580.
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In a previous study, we have demonstrated that beryllium oxide (BeO) film grown by atomic layer deposition (ALD) on Si and III-V MOS devices has excellent electrical and physical characteristics. In this paper, we compare the electrical characteristics of inserting an ultrathin interfacial barrier layer such as SiO2, Al2O3, or BeO between the HfO2gate dielectric and Si substrate in metal oxide semiconductor capacitors (MOSCAPs) and n-channel inversion type metal oxide semiconductor field effect transistors (MOSFETs). Si MOSCAPs and MOSFETs with a BeO/HfO2gate stack exhibited high performance and reliability characteristics, including a 34% improvement in drive current, slightly better reduction in subthreshold swing, 42% increase in effective electron mobility at an electric field of 1 MV/cm, slightly low equivalent oxide thickness, less stress-induced flat-band voltage shift, less stress induced leakage current, and less interface charge.
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Marrakh, R., and A. Bouhdada. "Impact of the Stress on the Sub-Micron N-Metal Oxide Semiconductor Field Effect Transistor Characteristics." Active and Passive Electronic Components 24, no. 3 (2001): 187–99. http://dx.doi.org/10.1155/2001/18731.
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In this paper, we present a drain current model for stressed short-channel MOSFET's. Stress conditions are chosen so that the interface states generated by hot-carriers are dominant. The defects generated during stress time are simulated by a spatio-temporal gaussian distribution. The parasitic source and drain resistances are included. We also investigate the impact of the interface charge density, generated during stress, on the transconductance. Simulation results show a significant degradation of the drain current versus stress time.
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Emelyanov, V. A., V. V. Baranov, and V. V. Emelyanov. "Multilayered conductive films of semiconductor devices and integrated circuits." Proceedings of the National Academy of Sciences of Belarus, Physical-Technical Series 65, no. 2 (2020): 170–76. http://dx.doi.org/10.29235/1561-8358-2020-65-2-170-176.
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The stress-migration phenomenon in films of alloy Al–Si which is observed at a current of high density (an order 105 А/mm2) is investigated. By results of researches the technical decision which allows quality raise of obtained film structures is offered. Its essence consists in formation in films the traps for migrating atoms of aluminium at course of a current of high density at the expense of formation the passive layer of TiN on the metal layer surface, for example, Al–1,5 %Si. In the presence of advanced relief of a surface of modern integrated circuits, for example with sub-micron sizes of the topology elements, the thickness and structure of metal current-carrying films on relief steps differs from what are located on planar sites. It leads to occurrence of essential gradients of mechanical pressure which are stress-migration motive power. As it is known, that temperature factor of linear expansion of aluminium is approximately 20 times, than SiO2, that causes active generation of dot defects in a layer of the alloy on the base of aluminium which is much more plastic than SiO2. Under the influence of a gradient of residual pressure, dot defects, existed in films, for example vacancies, come to movement mainly on border of metal - dielectric and in due course under the influence of a current of high density lead to formation of group defects in an alloy film, in particular emptiness, hills etc. Since stress-migration processes on these sites occur most intensively, as a result there is a rupture of films mainly on steps of a topological relief. Results of the research have passed approbation and can be used at manufacturing of silicon semi-conductor devices and integrated microcircuits.
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Ozkan, Cengiz Sinan. "(Invited) Bilayer Molybdenum Disulfide Strain Controlled Field Effect Transistor." ECS Meeting Abstracts MA2024-02, no. 35 (2024): 2431. https://doi.org/10.1149/ma2024-02352431mtgabs.
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Silicon nitride stress capping layers are pivotal in the semiconductor industry for their role in enhancing electron mobility and driving currents in n-channel silicon MOSFETs. This research delves into the effects of silicon nitride-induced strain on the electronic properties of bilayer Molybdenum Disulfide (MoS2), a promising two-dimensional semiconductor. We first examine the modifications in the photoluminescence and Raman spectra of bare bilayer MoS2 under strain. By depositing a silicon nitride stress liner on a bilayer MoS2 field effect transistor (FET), which impacts both the gate and the source-drain regions, we replicate the stress conditions akin to those experienced in silicon MOSFETs. This methodical approach enables us to comprehensively study the evolution from back-gated to top-gated, and ultimately, to strain-gated FET configurations. Our findings indicate that tensile strain crucially modifies the electronic structure of MoS2, primarily reducing the indirect band gap by lowering the conduction band at the K point. Performance evaluations of the FETs demonstrate a marked increase in electron mobility and on-current in the strain-gated configurations compared to top-gated setups, highlighting the positive effects of tensile strain on carrier transport within MoS2. This study not only furthers our understanding of strain effects on MoS2 but also underscores the potential of strain engineering in optimizing semiconductor devices.
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Lim, Jeong-Woo, and Chong-Eun Kim. "Drain-Source Voltage-Controllable Three-Switch Active-Clamp Forward Converter for Wide Input/Output Voltage Applications." Micromachines 14, no. 1 (2022): 35. http://dx.doi.org/10.3390/mi14010035.
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Active-clamp forward converters are applied to various medium-capacity power systems because they have a relatively simple structure and are capable of zero-voltage switching. In particular, there is the advantage that a stable output voltage can be obtained by controlling the duty ratio of the power semiconductor switch even in applications with wide input and output voltage ranges. However, the voltage stress on the power semiconductor switches due to the application of active clamp is higher than the input voltage, especially as the duty ratio increases. A three-switch active-clamp forward converter is proposed, which can overcome such shortcomings and can reduce the voltage stress of the power semiconductor switches, but it causes an increase in the DC bias of the magnetizing current and the additional conduction and switching losses. Therefore, in this paper, a voltage-stress-controllable three-switch active-clamp forward converter that can utilize both advantages of the conventional active-clamp forward converter and three-switch active clamp forward converter is proposed and verified through a prototype for 800 W battery charger.
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Tyan, Shing-Long, Hsiang-Chi Tang, Zhang-Wei Wu, and Ting-Shan Mo. "Diamond-like carbon as gate dielectric for metal–insulator–semiconductor applications." Modern Physics Letters B 33, no. 34 (2019): 1950423. http://dx.doi.org/10.1142/s0217984919504232.
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Diamond-like carbon (DLC) has been studied as a dielectric material for future metal–insulator–semiconductor (MIS) technology. In this paper, ultrathin DLC films were deposited on silicon substrates by using the dc magnetron sputtering technique at various deposition voltages. The current–voltage characteristics indicated that the leakage currents of the MIS devices decreased with an increase in deposition voltages, and that a low leakage current ([Formula: see text] A/cm2) was achieved at −2 V bias voltage. The deposition voltage effects on the structures of films were investigated through Raman spectroscopy, which indicated that the sp3 bonding fraction decreased with an increase in the deposition voltage. The ramp-voltage breakdown test revealed high effective breakdown electric field ([Formula: see text]85 MV/cm) for the MIS device with the DLC film deposited at 1100-V deposition. Stress-induced leakage current measurement indicated that the DLC film exhibited excellent reliability.
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Liu, Bosen, Guohao Yu, Huimin Jia, et al. "Current-collapse suppression and leakage-current decrease in AlGaN/GaN HEMT by sputter-TaN gate-dielectric layer." Journal of Semiconductors 45, no. 7 (2024): 072501. http://dx.doi.org/10.1088/1674-4926/24010025.
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Abstract In this paper, we explore the electrical characteristics of high-electron-mobility transistors (HEMTs) using a TaN/AlGaN/GaN metal insulating semiconductor (MIS) structure. The high-resistance tantalum nitride (TaN) film prepared by magnetron sputtering as the gate dielectric layer of the device achieved an effective reduction of electronic states at the TaN/AlGaN interface, and reducing the gate leakage current of the MIS HEMT, its performance was enhanced. The HEMT exhibited a low gate leakage current of 2.15 × 10−7 mA/mm and a breakdown voltage of 1180 V. Furthermore, the MIS HEMT displayed exceptional operational stability during dynamic tests, with dynamic resistance remaining only 1.39 times even under 400 V stress.
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Tan, Chao, Shibin Yuan, Linshan Yu, Yaohui Chen, and Changjiang He. "A Second-Order Fast Discharge Circuit for Transient Electromagnetic Transmitter." Sensors 25, no. 7 (2025): 2224. https://doi.org/10.3390/s25072224.
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To solve the problem of long turn-off times for transient electromagnetic (TEM) transmitters with inductive loads, a new second-order fast discharge circuit topology added into the original H-bridge structure for TEM transmitters is presented, which includes a capacitor, two Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), and two resistors. Firstly, the four operating stages and principles of the second-order circuit were analyzed. Then, the mathematical models of the turn-off time of the current and the voltage stress of the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) were established using the analytical method. Finally, the parameters of the resistor and capacitor were selected by finding the optimal solution for the fixed transmitter coil. Compared with the simulation results of the other two topologies, the proposed topology demonstrates a current-independent turn-off time and achieves the shortest duration at 50 A, while maintaining lower voltage stress at 9 A. The experimental results of the prototype show that the turn-off time is always about 64 μs when the currents are 1 A, 5 A, and 9 A. Simulation and experimental results show that the second-order circuit reduces the MOSFET’s turn-off time to 58 μs via Resistor–Inductor–Capacitor (RLC) series resonance, with the turn-off duration remaining load-current-independent.
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Meinertzhagen, A., C. Petit, M. Jourdain, and F. Mondon. "Anode hole injection and stress induced leakage current decay in metal-oxide-semiconductor capacitors." Solid-State Electronics 44, no. 4 (2000): 623–30. http://dx.doi.org/10.1016/s0038-1101(99)00309-3.
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Gitau, Michael Njoroge, Lebogang Masike, and Grain P. Adams. "A Unified Analysis of DC–DC Converters’ Current Stress." Energies 16, no. 8 (2023): 3370. http://dx.doi.org/10.3390/en16083370.
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There is always a need to analyze current signals generated by various DC–DC converters. For example, to determine the current stress experienced by semiconductor devices and to evaluate active and reactive power consumption in converters. The study demonstrates that the shape of a current signal dictates the analytical expressions required to determine the average and RMS values of a signal as well as the RMS value of the ripple of that signal. The study also shows that current signals can be treated as composite waveforms comprising various combinations of trapezoidal, rectangular, and triangular pulses. The current literature lacks a unified approach to analyze current stresses in DC–DC converters. This study will propose a unified and generalized analytical technique that is applicable to any type of DC waveform that can be treated as a composite waveform made up of a combination of triangular, rectangular, or trapezoidal sections or sub-intervals. Furthermore, the rectangular and triangular pulses are shown to be a special kind of trapezoidal pulse. This provides the basis for a very broad generalization of current signals’ analysis based on the analysis of a trapezoidal pulse. Additionally, a method for the direct evaluation of signals’ ripple RMS content is developed. This is unlike in the current literature where it is necessary to evaluate the signal’s average and RMS values before ripple content can be evaluated. The technique developed is applicable to continuous and discontinuous conduction modes of operation.
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Wang, Dapeng, Mamoru Furuta, Shigekazu Tomai, and Koki Yano. "Understanding the Role of Temperature and Drain Current Stress in InSnZnO TFTs with Various Active Layer Thicknesses." Nanomaterials 10, no. 4 (2020): 617. http://dx.doi.org/10.3390/nano10040617.
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Thin-film transistor (TFT) devices composed of metal oxide semiconductors have attracted tremendous research attention globally in recent years. Owing to their ability to offer mobility, metal oxide semiconductor materials can enable high-performance TFTs for next-generation integrated display devices. Nevertheless, further breakthroughs of metal oxide TFTs are mainly obstructed by their long-term variability, the reason for which is not yet fully understood. Herein, TFTs based on InSnZnO (ITZO) with various thicknesses (TITZO) were prepared and their long-term stabilities under test temperatures and drain current stress were investigated. The results indicate that ITZO TFTs exhibit outstanding electrical properties regardless of the TITZO, including a high saturated mobility of over 35 cm2V−1s−1 and sharp subthreshold swing. Note that the transfer and output characteristic curves of the device with a thick TITZO of 100 nm express an abnormal current surge when high gate and drain voltages are exerted, which is attributed to the floating body effect, caused when the imposed electric field induces impact ionization near the drain side. More interestingly, these drain current stress results further suggest that the abnormal shift behavior of the electrical properties of the ITZO TFTs with a TITZO of greater than 75 nm is observed to deteriorate gradually with increasing temperature and drain current bias. This study addresses that such a degradation effect should be restrained for the operation of high-mobility devices.
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Min, Kyuhae, Taejun Kang, Tae Yeob Kang, and Jae-Bum Pyo. "Evaluation of Leakage Currents of Semiconductor Packages Due to High-Voltage Stress Under an Immersion Cooling Environment." Applied Sciences 15, no. 9 (2025): 4668. https://doi.org/10.3390/app15094668.
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As data centers expand, immersion cooling systems are gaining attention for thermal management of memory devices. To enable widespread adoption, it is essential to evaluate the impact of coolants on the reliability of memory packages. In this study, high-voltage direct current (DC) stress tests were conducted on commercial dynamic random access memory (DRAM) packages in both single-phase coolant and air environments to analyze heat generation and electrical characteristics. A DC voltage ranging from 2.5 to 3.1 V, which is higher than the regular operating voltage of 1.2 V, was applied. Temperature changes were measured using an infrared camera in the air, and a contact-based thermometer in the coolant. The leakage current was also evaluated through I-V curve analysis. Heat generation and changes in leakage currents were not significant in either environment until the applied voltage stress exceeded approximately twice the standard voltage (2.5–2.8 V). However, the package’s degradation accelerated when the applied voltages exceeded 3.0 V, demonstrating a nonlinear increase in temperature and leakage current.
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Souza, Lucas Carvalho, Luciano de Souza da Costa e. Silva, Falcondes José Mendes de Seixas, and Luis De Oro Arenas. "3SSC-A-Based Step-Down DC–DC Converters: Analysis, Design and Experimental Validation." Energies 15, no. 20 (2022): 7710. http://dx.doi.org/10.3390/en15207710.
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This paper proposes two non-isolated step-down DC–DC converters based on the type-A three-state switching cell (3SSC-A), resulting in an alternative to the buck and buck-boost classical converters, respectively. The proposed topologies are part of a group of unexplored converters that employ the 3SSC-A, which has the advantages of 3SSC-based converters, such as high power density, reduced current stress on the semiconductors and suitable thermal loss distribution. In this regard, a complete static analysis is performed, including a detailed study of all semiconductor voltage and current efforts and developing loss models for each one. Moreover, by using simulation models, AC sweep analyses validate the dynamic frequency response of each converter’s small-signal models, and PI-based output–voltage closed-loop controllers are duly designed. Finally, the topologies are experimentally validated through the implementation of adequately designed prototypes, achieving efficiency values greater than 91% under several output power rates varying from 50% to 100%.
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ILIESCU, Ciprian. "A COMPREHENSIVE REVIEW ON THIN FILM DEPOSITIONS ON PECVD REACTORS." Annals of the Academy of Romanian Scientists Series on Science and Technology of Information 14, no. 1-2 (2021): 12–24. http://dx.doi.org/10.56082/annalsarsciinfo.2021.1-2.12.
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The deposition of thin films by Plasma Enhanced Chemical Vapor Deposition (PECVD) method is a critical process in the fabrication of MEMS or semiconductor devices. The current paper presents an comprehensive overview of PECVD process. After a short description of the PECVD reactors main layers and their application such as silicon oxide, TEOS, silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, diamond like carbon are presented. The influence of the process parameters such as: chamber pressure, substrate temperature, mass flow rate, RF Power and RF Power mode on deposition rate, film thickness uniformity, refractive index uniformity and film stress were analysed. The main challenge of thin films PECVD deposition for Microelectromechanical Systems (MEMS)and semiconductor devices is to optimize the deposition parameters for high deposition rate with low film stress which and if is possible at low deposition temperature.
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Mori, Yuki, Mieko Matsumura, Hirotaka Hamamura, et al. "Direct Observation of Dielectric Breakdown at Step-Bunching on 4H-SiC." Materials Science Forum 821-823 (June 2015): 468–71. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.468.
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The mechanism of dielectric breakdown of oxide on step-bunching of 4H-silicon carbide (SiC) was investigated. Comparing the surface morphology obtained before forming metal-oxide-semiconductor (MOS) capacitor and optical emission on the capacitor under electrical stress, it was cleared that current concentrates on step-bunching and it often caused preferential dielectric breakdown. Based on TEM analysis and the observation of time dependence of emission under the stress, a new model was proposed to explain the dielectric breakdown on step-bunching.
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Lipp, E., A. Kohn, and M. Eizenberg. "Lifetime-limited current in Cu-gate metal-oxide-semiconductor capacitors subjected to bias thermal stress." Journal of Applied Physics 99, no. 3 (2006): 034504. http://dx.doi.org/10.1063/1.2168034.
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Wang, Yanxin, Jiye Li, Fayang Liu, et al. "Fluorination-mitigated high-current degradation of amorphous InGaZnO thin-film transistors." Journal of Semiconductors 44, no. 9 (2023): 092601. http://dx.doi.org/10.1088/1674-4926/44/9/092601.
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Abstract As growing applications demand higher driving currents of oxide semiconductor thin-film transistors (TFTs), severe instabilities and even hard breakdown under high-current stress (HCS) become critical challenges. In this work, the triggering voltage of HCS-induced self-heating (SH) degradation is defined in the output characteristics of amorphous indium-gallium-zinc oxide (a-IGZO) TFTs, and used to quantitatively evaluate the thermal generation process of channel donor defects. The fluorinated a-IGZO (a-IGZO:F) was adopted to effectively retard the triggering of the self-heating (SH) effect, and was supposed to originate from the less population of initial deep-state defects and a slower rate of thermal defect transition in a-IGZO:F. The proposed scheme noticeably enhances the high-current applications of oxide TFTs.
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Huang, Cheng-Yu, Soumen Mazumder, Pu-Chou Lin, Kuan-Wei Lee, and Yeong-Her Wang. "Improved Electrical Characteristics of AlGaN/GaN High-Electron-Mobility Transistor with Al2O3/ZrO2 Stacked Gate Dielectrics." Materials 15, no. 19 (2022): 6895. http://dx.doi.org/10.3390/ma15196895.
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A metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) is proposed based on using a Al2O3/ZrO2 stacked layer on conventional AlGaN/GaN HEMT to suppress the gate leakage current, decrease flicker noise, increase high-frequency performance, improve power performance, and enhance the stability after thermal stress or time stress. The MOS-HEMT has a maximum drain current density of 847 mA/mm and peak transconductance of 181 mS/mm. The corresponding subthreshold swing and on/off ratio are 95 mV/dec and 3.3 × 107. The gate leakage current can be reduced by three orders of magnitude due to the Al2O3/ZrO2 stacked layer, which also contributes to the lower flicker noise. The temperature-dependent degradation of drain current density is 26%, which is smaller than the 47% of reference HEMT. The variation of subthreshold characteristics caused by thermal or time stress is smaller than that of the reference case, showing the proposed Al2O3/ZrO2 stacked gate dielectrics are reliable for device applications.
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Feng, Bin, Junfeng Zhao, Haofei Zhang, Tao Li, and Jianjun Mi. "Design of High-Performance Driving Power Supply for Semiconductor Laser." Electronics 12, no. 23 (2023): 4758. http://dx.doi.org/10.3390/electronics12234758.
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High power semiconductor laser is a kind of photoelectric device with high efficiency and high stability, the performance of its drive system directly affects its output characteristics and service life. In order to solve the problems of stability and robustness of the output power of the semiconductor laser, a semiconductor laser driving power supply with high efficiency, low ripple and strong anti-interference ability was developed. In this paper, the topology of the LCC resonant converter is adopted (LCC refers to the type of resonant converter, because its resonator is composed of an inductor L and two capacitors C, it is called LCC resonant converter). The power supply adopts full-bridge LCC resonant power topology. Firstly, a mathematical model is established to analyze the relationship between LCC resonator parameters and output current gain. Secondly, an LCC resonator parameter design method is proposed to reduce the current stress of components, and the variable frequency phase shift (PFM-PWM) composite control strategy and linear active disturbance rejection control (LADRC) algorithm are proposed, which not only ensures the zero voltage (ZVS) conduction of MOS (Metal-Oxide-Semiconductor) tube, but also reduces the on-off loss of MOS tube. The PFM-PWM composite control strategy and LADRC algorithm not only improve the power efficiency of the drive power supply, suppress the output current ripple, but also ensure that the output current of the drive power supply is stable when the input voltage, load and parasitic parameters of the circuit change. Finally, the simulation and experimental results show that the power supply can be continuously adjustable in the output current range of 0–40 A, the current ripple is less than 0.8%, and the working efficiency is up to 92%. It has the characteristics of high stability, small ripple, high efficiency, low cost and good robustness.
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Chen, Jian, Koustav Jana, Qi Jiang, Shuhan Liu, Kasidit Toprasertpong, and H. S. Philip Wong. "(Invited) Oxide Semiconductor Gain Cell Memory." ECS Meeting Abstracts MA2024-01, no. 30 (2024): 1495. http://dx.doi.org/10.1149/ma2024-01301495mtgabs.
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The energy and delay consumed by the off-chip memory (DRAM) and memory-to-logic chip data movement becomes the bottleneck (known as the memory wall) for the computing systems nowadays, especially for abundant-data computing and neural network accelerators. Larger on-chip memory capacity with high bandwidth can be a solution, yet it is difficult to achieve using SRAM and DRAM. Oxide semiconductor FET (OSFET)-based gain cell memory on the logic platform provides higher density than SRAM due to 3D stacking and is an attractive complement to off-chip DRAM. OSFET with extremely low leakage is used as the write transistor for long retention time, while the read transistor can either adopt OSFET for multiple-layer stacking (OS-OS gain cell) or Si FET for higher read speed (Hybrid gain cell). Designing OSFET gain cell is more than simply choosing materials/device designs that have the lowest off-state leakage current for the longest retention time. Atomic Layer Deposition (ALD) Indium Tin Oxide (ITO) FET is chosen to balance retention time with memory bandwidth. With material, process, and device co-design, the ITO films deposited by ALD with TMIn precursor, 9:1 In:Sn cycle ratio, and 2nm thickness exhibited optimized characteristics for OSFET-based gain cell. The experimentally optimized device exhibits low off-current 2×10-18 A/µm, high on-current 26.8 µA/µm, low SS 70 mV/dec, and high mobility 27 cm2/Vs. It also shows good stability with small VTH shift < 0.2 V under 125 °C, low PBS shift < 0.35 V and low NBS shift < 0.1 V under 1000s bias stress. Oxide semiconductor transistors is an accumulation mode transistor that requires a gate electric field to turn off the transistor. The transistor design calls for nanometer-thin oxide semiconductor channels. Significant device design tradeoffs exists between high on-current, low off-current, short gate length scalability, and the setting of proper threshold voltages. This talk will give an overview of the above experimental achievements today and the device design considerations for future gain cell memories.
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Wang, Xiang-Dong. "Scanning Probe Microscopy Applications in Failure Analysis of Semiconductor Devices." EDFA Technical Articles 22, no. 1 (2020): 20–25. http://dx.doi.org/10.31399/asm.edfa.2020-1.p020.
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Abstract Scanning probe microscopy (SPM) is widely used for fault isolation as well as diagnosing leakage current, detecting open circuits, and characterizing doping related defects. In this article, the author presents two SPM applications that are fairly uncommon but no less important in the scope of failure analysis. The first case involves the discovery of nano-steps on the surface of high-voltage NFETs, a phenomenon associated with stress-induced crystalline shift along the (111) silicon plane. In the second case, the author uses an AFM probe in the conductive mode to correlate tunneling current distribution with hot spots in high-k gate oxide films, which is shown to be a better indicator of oxide quality than rms surface roughness.
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Lee, Hyeonju, Dongwook Kim, Hyunji Shin, Jin-Hyuk Bae, and Jaehoon Park. "Effects of Post-UV/Ozone Treatment on Electrical Characteristics of Solution-Processed Copper Oxide Thin-Film Transistors." Nanomaterials 13, no. 5 (2023): 854. http://dx.doi.org/10.3390/nano13050854.
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To realize oxide semiconductor-based complementary circuits and better transparent display applications, the electrical properties of p-type oxide semiconductors and the performance improvement of p-type oxide thin-film transistors (TFTs) are required. In this study, we report the effects of post-UV/ozone (O3) treatment on the structural and electrical characteristics of copper oxide (CuO) semiconductor films and the TFT performance. The CuO semiconductor films were fabricated using copper (II) acetate hydrate as a precursor material to solution processing and the UV/O3 treatment was performed as a post-treatment after the CuO film was fabricated. During the post-UV/O3 treatment for up to 13 min, the solution-processed CuO films exhibited no meaningful change in the surface morphology. On the other hand, analysis of the Raman and X-ray photoemission spectra of solution-processed CuO films revealed that the post-UV/O3 treatment induced compressive stress in the film and increased the composition concentration of Cu–O lattice bonding. In the post-UV/O3-treated CuO semiconductor layer, the Hall mobility increased significantly to approximately 280 cm2 V−1 s−1, and the conductivity increased to approximately 4.57 × 10−2 Ω−1 cm−1. Post-UV/O3-treated CuO TFTs also showed improved electrical properties compared to those of untreated CuO TFTs. The field-effect mobility of the post-UV/O3-treated CuO TFT increased to approximately 6.61 × 10−3 cm−2 V−1 s−1, and the on-off current ratio increased to approximately 3.51 × 103. These improvements in the electrical characteristics of CuO films and CuO TFTs can be understood through the suppression of weak bonding and structural defects between Cu and O bonds after post-UV/O3 treatment. The result demonstrates that the post-UV/O3 treatment can be a viable method to improve the performance of p-type oxide TFTs.
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Zhou, Shuai, Kaixue Ma, Yugong Wu, et al. "Survey of Reliability Research on 3D Packaged Memory." Electronics 12, no. 12 (2023): 2709. http://dx.doi.org/10.3390/electronics12122709.
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As the core carrier of information storage, a semiconductor memory device is a basic product with a large volume that is widespread in the integrated circuit industry. With the rapid development of semiconductor manufacturing processes and materials, the internal structure of memory has gradually shifted from a 2D planar packaging structure to a 3D packaging structure to meet industry demands for high-frequency, high-speed, and large-capacity devices with low power consumption. However, advanced 3D packaging technology can pose some reliability risks, making devices prone to failure, especially when used in harsh environmental conditions, including temperature changes, high temperature and humidity levels, and mechanical stress. In this paper, the authors introduce the typical structure characteristics of 3D packaged memory; analyze the reasons for device failure caused by stress; summarize current research methods that utilize temperature, mechanical and hygrothermal theories, and failure models; and present future challenges and directions regarding the reliability research of 3D packaged memory.
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Wei, Andrew, Radu Reit, and Walter Voit. "Investigating thiol-epoxy composites for semiconductor die attach adhesives." MRS Proceedings 1718 (2015): 27–31. http://dx.doi.org/10.1557/opl.2015.539.
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ABSTRACTIn this study, thiol-epoxy polymer composites are explored as candidates for high-temperature die attach applications. We present a polymer composite processing technique for die attach adhesives with low cure-stress. Lap shear samples of both a polymer adhesive and current industry adhesives were subjected to tensile testing and die shear strength was compared. At 260 °C, the candidate polymer adhesive exhibited a die shear strength of 0.500 MPa in comparison with 1.35 MPa and 0.258 MPa for two control adhesives. While samples showed less variation in properties in die shear strength between room temperature and 260 °C, the absolute die shear strength values were inferior to commercial adhesives at both room and elevated temperatures. We hypothesize that low cure stress networks, such as the thiol-epoxies presented, provide a compelling choice to engineer new die attach adhesives, but realize that further network refining is needed including the addition of adhesion promoters and other additives, a task better suited to industrial research with a focus in properties optimization.
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Hu, Wang, Yunxiang Xie, Zhiping Wang, and Zhi Zhang. "A Novel Three-Phase Current Source Rectifier Based on an Asymmetrical Structure to Reduce Stress on Semiconductor Devices." Energies 13, no. 13 (2020): 3331. http://dx.doi.org/10.3390/en13133331.
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This paper presents a novel three-phase current source rectifier (CSR) for AC/DC step-down voltage conversion to reduce voltage and current stress. The proposed converter features an asymmetrical connection between upper and lower arms compared with conventional CSRs, but has the same number of devices. With the proposed asymmetrical structure and modified space vector pulse width modulation (SVPWM) scheme, half of transistors only need to withstand half of the line-to-line voltage rather than the full line-to-line voltage, and its DC link current can be shared by multiple switches in freewheeling periods. Therefore, it is able to bring about a significant reduction in voltage and current stress, allowing for an improvement in the converter without additional cost. The topological structure, operation principles, and comparative analysis are specifically presented. Finally, an experimental prototype is built up to verify the performance of the proposed converter.
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Tang, Yi, and Frede Blaabjerg. "A Component-Minimized Single-Phase Active Power Decoupling Circuit With Reduced Current Stress to Semiconductor Switches." IEEE Transactions on Power Electronics 30, no. 6 (2015): 2905–10. http://dx.doi.org/10.1109/tpel.2014.2369959.
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Shifren, L., X. Wang, P. Matagne, et al. "Drive current enhancement in p-type metal–oxide–semiconductor field-effect transistors under shear uniaxial stress." Applied Physics Letters 85, no. 25 (2004): 6188–90. http://dx.doi.org/10.1063/1.1841452.
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Hong, Chao-Chi, Wei-Jian Liao, and Jenn-Gwo Hwu. "Thickness-dependent stress effect in p-type metal–oxide–semiconductor structure investigated by substrate injection current." Applied Physics Letters 82, no. 22 (2003): 3916–18. http://dx.doi.org/10.1063/1.1581004.
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Pogany, D., S. Bychikhin, C. Furbock, et al. "Quantitative internal thermal energy mapping of semiconductor devices under short current stress using backside laser interferometry." IEEE Transactions on Electron Devices 49, no. 11 (2002): 2070–79. http://dx.doi.org/10.1109/ted.2002.804724.
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Suwanasri, Cattareeya, Thanapong Suwanasri, and Phanupong Fuangpian. "Investigation on Partial Discharge of Power Cable Termination Defects using High Frequency Current Transformer." ECTI Transactions on Electrical Engineering, Electronics, and Communications 12, no. 1 (2013): 16–23. http://dx.doi.org/10.37936/ecti-eec.2014121.170810.
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This paper presents partial discharge (PD) investigation of different cable termination defects. The medium voltage power cables as rated of 3.6/6(7.2) kV are applied. Finite Element Method Magnetic (FEMM) program is used as a simulation tool for electric field stress investigation. The partial discharges patterns are detected by using a commercial High Frequency Current Transformer (HFCT). The simple cases for internal, surface and corona discharge are firstly observed in order to investigate the performance of the HFCT. Then eight different case studies of cable termination defects are further investigated, which includes non-terminator, voids between XLPE and stress control, 20 mm. overlaps between semiconductor and stress control, particles on XLPE, non-smooth XLPE, needle tip on insulation screen, impropriate cable bending, and proper termination. The results are then compared with the results from a conventional PD diagnosis tool according to IEC 60270 standard. The results of PD detection show that the commercial product can detect the PD waveform and measure the electric charge when it is highly enough. The test can also identify trends toward breakdown and there severity due to improper cable termination defects.
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Chen, Yung Yu, Chih Ren Hsieh, and Fang Yu Chiu. "Characteristics of the SiN Uniaxial Strained NMOSFET with Channel Fluorine Implantation." Advanced Materials Research 383-390 (November 2011): 3178–82. http://dx.doi.org/10.4028/www.scientific.net/amr.383-390.3178.
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Channel fluorine implantation (CFI) has been successfully integrated with silicon nitride contact etch stop layer (SiN CESL) to further improve the channel hot electron stress (CHES) and constant voltage stress (CVS) reliability of n-channel metal-oxide-semiconductor field-effect-transistor with HfO2/SiON gate stack. Although the improvement of transconductance, drain current and subthreshold swing due to the fluorine passivation is screened out by the effect of uniaxial tensile strain, the result clearly demonstrates that integrating the CFI process in the SiN CESL-strained device can further suppress the CHES- and CVS-induced threshold voltage shift.
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Yang, Yu-Pu, Te-Yun Lu, Hsiao-Han Lo, et al. "Machine Learning Assisted Classification of Aluminum Nitride Thin Film Stress via In-Situ Optical Emission Spectroscopy Data." Materials 14, no. 16 (2021): 4445. http://dx.doi.org/10.3390/ma14164445.
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In this study, we submit a complex set of in-situ data collected by optical emission spectroscopy (OES) during the process of aluminum nitride (AlN) thin film. Changing the sputtering power and nitrogen(N2) flow rate, AlN film was deposited on Si substrate using a superior sputtering with a pulsed direct current (DC) method. The correlation between OES data and deposited film residual stress (tensile vs. compressive) associated with crystalline status by X-ray diffraction spectroscopy (XRD), scanning electron microscope (SEM), and transmission electron microscope (TEM) measurements were investigated and established throughout the machine learning exercise. An important answer to know is whether the stress of the processing film is compressive or tensile. To answer this question, we can access as many optical spectra data as we need, record the data to generate a library, and exploit principal component analysis (PCA) to reduce complexity from complex data. After preprocessing through PCA, we demonstrated that we could apply standard artificial neural networks (ANNs), and we could obtain a machine learning classification method to distinguish the stress types of the AlN thin films obtained by analyzing XRD results and correlating with TEM microstructures. Combining PCA with ANNs, an accurate method for in-situ stress prediction and classification was created to solve the semiconductor process problems related to film property on deposited films more efficiently. Therefore, methods for machine learning-assisted classification can be further extended and applied to other semiconductors or related research of interest in the future.
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Patelka, Maciej, Nicholas Krasco, Sho Ikeda, et al. "Conductive Fusion Technology Advanced Die Attach Materials for High Power Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (2018): 000051–55. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000051.
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Abstract High power semiconductor applications require a die attach material with high thermal conductivity to efficiently release the heat generated from these devices. Current die attach solutions such as eutectic solders and high thermal conductive silver epoxies and sintered silver adhesives have been industry standards, however may fall short in performance for high temperature or high stress applications. This presentation will focus on development of a reinforced, sintered silver die attach solution for high power semiconductor applications with focus on a pressure-less, low temperature sintering technology that offers high reliability for high temperature (250°C) applications. The electronic, optoelectronic, and semiconductor industries have the need for high performance adhesives, in particular, high power devices require low-stress, high thermal conductivity, thermally stable, and moisture resistant adhesives for the manufacture of high reliability devices. This paper introduces a new reinforced sintered silver adhesive based on the “resin-free” Conductive Fusion Technology. The high performance adhesive offers a robust solution for high temperature, high reliability applications. Conductive Fusion Technology consists of a high thermal conductivity silver component blended with a non-conductive, low-modulus powder component. The non-conductive powder component comprises an organically modified inorganic material that exhibits excellent thermal stability at temperatures exceeding 250°C. Properties of the sintered silver adhesive, such as storage modulus, can be modified by varying the content of the non-conductive component.
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Takahashi, Takanori, and Yukiharu Uraoka. "(Invited) High Performance Metal Oxide Thin Film Transistor Using ALD Technology." ECS Meeting Abstracts MA2024-02, no. 34 (2024): 2399. https://doi.org/10.1149/ma2024-02342399mtgabs.
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Field-effect transistors (FETs) based on oxide semiconductors, mainly In2O3 and ZnO, have been commercialized as channel materials for thin-film transistors due to their features such as electron mobility exceeding 10-50 cm2/Vs, extremely low leakage current, and low process temperature. Recently, FETs that can be applied to ferroelectric memory and back end of line have been demonstrated for implementation in ultra-integrated circuits and semiconductor memory. In order to realize various integrated devices using oxide semiconductors, it is necessary to uniformly deposit ultra-thin films of about 5 nm on a three-dimensional structure from the viewpoint of device integration and suppression of short-channel effects. This research group has shown that amorphous In-Ga-O (IGO) is a promising oxide semiconductor material that can be applied to three-dimensional integrated devices. However, it was shown that IGO-FETs have reliability issues because their threshold voltage (Vth) easily fluctuates in response to voltage stress . The purpose of this study was to examine the factors that contribute to Vth instability and to suppress it by evaluating the relationship between FET reliability and IGO composition ratio and annealing temperature, as well as the effect of crystallization. Top-contact/bottom-gate FETs with AlOx protective films were fabricated by depositing 10-11 nm-thick IGO channels on SiO2 (85 nm)/n++-Si substrates using ALD method Triethylindium and Trimethylgallium The composition ratio of In:Ga in the IGO film was controlled by adjusting the ratio of growth cycles of the InOx and GaOx layers. positive bias stress (PBS), in which a positive voltage is applied to the gate electrode. The reliability of amorphous IGO against PBS was found to depend on the composition ratio of In:Ga and annealing temperature. It is known that the formation energy of O-O bonds corresponding to excess oxygen is lower in amorphous oxide semiconductors than in single-crystal and polycrystal structures due to their higher structural degrees of freedom. It was experimentally clarified that electron capture occurs more easily in IGO systems than in other oxide semiconductors (Ex. In-Zn-O), which is consistent with theoretical calculations in previous studies. In addition, we focused on crystalline Ga-doped In2O3 to improve the reliability of the IGO system and developed a deposition process using ALD method. We demonstrated that FETs with polycrystalline IGOs as channels have superior mobility and reliability compared to amorphous IGOs. The present study clarified that excess oxygen must be reduced during deposition of oxide semiconductors using the ALD method, and that polycrystalline oxide semiconductors are effective in improving reliability.
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Mao, Hua, Binbing Wu, Xinsheng Lan, Yalong Xia, Junjie Chen, and Lei Tang. "Research on Improving the Avalanche Current Limit of Parallel SiC MOSFETs." Electronics 14, no. 13 (2025): 2502. https://doi.org/10.3390/electronics14132502.
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The transient overvoltage caused by coupling of loop inductance during rapid turn off of a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) can easily induce avalanche breakdown. Meanwhile, the instantaneous high-density heat flux generated by energy dissipation can create significant electrothermal coupling stress, potentially leading to device failure under severe conditions. To address the issue that the multi-chip parallel structure of power modules cannot linearly enhance avalanche withstand capability, an innovative device screening method based on parameter matching is proposed in this paper. The effectiveness of the proposed solution is verified through experiments, with the total current limit of dual-tube parallel devices and three-tube parallel devices achieving 1.9 times and 2.4 times that of single-tube devices, respectively. This research is of great significance for improving safe and reliable operation of the system.
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Schuegraf, Klaus F., and Chenming Hu. "Metal‐oxide‐semiconductor field‐effect‐transistor substrate current during Fowler–Nordheim tunneling stress and silicon dioxide reliability." Journal of Applied Physics 76, no. 6 (1994): 3695–700. http://dx.doi.org/10.1063/1.357438.
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Saeed, Abdulkafi M., Kh Lotfy, and Alaa A. El-Bary. "Hall Current Effect of Magnetic-Optical-Elastic-Thermal-Diffusive Semiconductor Model during Electrons-Holes Excitation Processes." Journal of Mathematics 2022 (November 15, 2022): 1–17. http://dx.doi.org/10.1155/2022/6597924.
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In this study, a novel model is introduced when the Hall effect associated with a strong magnetic field is taken into account when the electrons and holes interact in the processes of semiconductor material. The plasma-elastic-thermal waves are investigated in the context of diffusive processes during optical-generated transport processes. The variable of thermal conductivity is obtained during graduated temperature due to the thermal impact of fallen light. The governing equations of the novel model are investigated in a unidimensional (1D) way when the electronics and elastic deformations have occurred. The Laplace transforms are used to convert the main dimensionless physical fields according to the initial conditions into the Laplace domain. When certain thermal, mechanical, holes, and electronic conditions are used, the analytical solutions of the fundamental fields can be produced to the outer surface of the semiconductor medium. Mathematically, the Laplacian computational inversion algorithm with a numerical approximation is used to achieve the fundamental physical quantities numerically in the time domain. The influences of several parameters (thermal relaxation times, Hall impact, and thermal conductivity parameters) on thermal conditions, mechanical stress, holes charge carrier field, and carrier density are prescribed with the help of graphical diagrams that are discussed theoretically.
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Flicker, Jack, David Hughart, Robert Kaplar, Stanley Atcitty, and Matthew Marinella. "Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs and JFETs at High Temperatures." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (2014): 000228–34. http://dx.doi.org/10.4071/hitec-wp16.
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1200 V Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs) have been characterized at high operational temperatures. For packaged JFETs obtained from a collaborating manufacturer, the threshold shift (ΔVT) was measured under both static and dynamic voltage stress and, in all cases, was less than 2 mV, which is within the measurement margin of error. Temperatures up to 250°C and stress times as long as 200 hours were evaluated. As a comparison, commercially available SiC MOSFETs demonstrated shifts of up to 300 mV after 30 minutes of static gate stress at 175°C. In addition, results from unpackaged JFET die at temperatures up to 525°C show ΔVT values of less than 10 mV for all stress conditions. Although VT remained unchanged for the duration of the test for both static and dynamic stress conditions, under dynamic stress conditions the JFET packaged parts demonstrated a linear increase in sub-threshold leakage current of around 15.6 nA per hour; in contrast, the MOSFET devices showed an exponential increase in sub-threshold leakage under dynamic stress. The increase in sub-threshold leakage current could be recovered temporarily, but long-term behavior was consistent with cumulative damage.
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Yastrubchak, O., T. Wosiński, J. Z. Domagała, and E. Łusakowska. "Anisotropy of Strain Relaxation in III-V Semiconductor Heterostructures." Defect and Diffusion Forum 230-232 (November 2004): 93–100. http://dx.doi.org/10.4028/www.scientific.net/ddf.230-232.93.
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Partially relaxed III–V heterostructures: GaAs/InGaAs and InP/InAlAs/InGaAs, with a small lattice mismatch, grown using molecular beam epitaxy under compressive or tensile misfit stress at the (001) interface, have been investigated by means of high-resolution X-ray diffractometry, atomic force microscopy and generalized ellipsometry. Additionally, transmission electron microscopy and electron-beam induced current in a scanning electron microscope have been employed to reveal misfit dislocations at the heterostructure interface. Chemical etching was used to determine polarity of the crystals and threading dislocation densities in the epitaxial layers. Our findings are interpreted in terms of the dependent on growth conditions, material’s composition and doping glide velocities of two types of misfit dislocations: α and β, differing in their core structure and lying along two orthogonal 〈110〉 crystallographic directions at the (001) interface.
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Chen, Chii-Wen, Mu-Chun Wang, Cheng-Hsun-Tony Chang, Wei-Lun Chu, Shun-Ping Sung, and Wen-How Lan. "Hot Carrier Stress Sensing Bulk Current for 28 nm Stacked High-k nMOSFETs." Electronics 9, no. 12 (2020): 2095. http://dx.doi.org/10.3390/electronics9122095.
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This work primarily focuses on the degradation degree of bulk current (IB) for 28 nm stacked high-k (HK) n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs), sensed and stressed with the channel-hot-carrier test and the drain-avalanche-hot-carrier test, and uses a lifetime model to extract the lifetime of the tested devices. The results show that when IB reaches its maximum, the ratio of VGS/VDS values at this point, in the meanwhile, gradually increases in the tested devices from the long-channel to the short ones, not just located at one-third to one half. The possible ratiocination is due to the ON-current (IDS), in which the short-channel devices provide larger IDS impacting the drain junction and generating more hole carriers at the surface channel near the drain site. In addition, the decrease in IB after hot-carrier stress is not only the increment in threshold voltage VT inducing the decrease in IDS, but also the increment in the recombination rate due to the mechanism of diffusion current. Ultimately, the device lifetime uses Berkley’s model to extract the slope parameter m of the lifetime model. Previous studies have reported m-values ranging from 2.9 to 3.3, but in this case, approximately 1.1. This possibly means that the critical energy of the generated interface state becomes smaller, as is the barrier height of the HK dielectric to the conventional silicon dioxide as the gate oxide.
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Meera, Akshaya. "High Gain Modified Based on Switched Inductor." International Journal for Research in Applied Science and Engineering Technology 11, no. 6 (2023): 1346–52. http://dx.doi.org/10.22214/ijraset.2023.53868.
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Abstract: The proposed work represents the Modified boost converter is able to regulate the output voltage and the choice of second inductor can give its current as positive and whereas for boost increases in the voltage will not able to regulate the output voltage. It has low semiconductor device voltage stress and switch usage factor is high. A power with 125 W is developed with a 20V input voltage and yields 222 V output voltage and the outcomes are approved through recreation utilizing
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He, Hongyi, Minjie Zhang, Wenjun Wang, Xudong Li, Miaomiao Li, and Luke Zhao. "Two-Dimensional Linear Elasticity Equations of Thermo-Piezoelectric Semiconductor Thin-Film Devices and Their Application in Static Characteristic Analysis." Applied Sciences 14, no. 15 (2024): 6509. http://dx.doi.org/10.3390/app14156509.
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Based on the three-dimensional (3D) linear elasticity theory of piezoelectric semiconductor (PS) structures, inspired by the variational principle and the Mindlin plate theory, a two-dimensional (2D) higher-order theory and equations for thin-film devices are established for a rectangular coordinate system, in which Newton’s law (i.e., stress equation of motion), Gauss’s law (i.e., charge equation of electrostatics), Continuity equations (i.e., conservation of charge for holes and electrons), drift–diffusion theory for currents in semiconductors, and unavoidable thermo-deformation-polarization-carrier coupling response in external stimulus field environment are all considered. As a typical application of these equations, the static characteristic analysis of electromechanical fields for the extensional deformation of a PS thin-film device with thermal field excitations is carried out by utilizing established zeroth-order equations and the double trigonometric series solution method. It is revealed that the extensional deformations, electric potential, electron and hole concentration perturbations, and their current densities can be controlled actively via artificially tuning thermal fields of external stimuli. Especially, a higher temperature rise can induce a deeper potential well and a higher potential barrier, which can play a vital role in driving effectively motions and redistributions of electrons and holes. Overall, the derived 2D equations as well as the quantitative results provide us some useful guidelines for investigating the thermal regulation behavior of PS thin-film devices.