Academic literature on the topic 'Semiconductor-on-Chip Architecture'
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Journal articles on the topic "Semiconductor-on-Chip Architecture"
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Luo, Jifeng, Wenqi Wu, Qianjian Xing, Meiting Xue, Feng Yu, and Zhenguo Ma. "A Low-Latency Fair-Arbiter Architecture for Network-on-Chip Switches." Applied Sciences 12, no. 23 (2022): 12458. http://dx.doi.org/10.3390/app122312458.
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As semiconductor technology evolves, computing platforms attempt to integrate hundreds of processing cores and associated interconnects into a single chip. Network-on-chip (NoC) technology has been widely used for data exchange centers in recent years. As the core element of the NoC, the round-robin arbiter provides fair and fast arbitration, which is essential to ensure the high performance of each module on the chip. In this paper, we propose a low-latency fair switch arbiter (FSA) architecture based on the tree structure search algorithm. The FSA uses a feedback-based parallel priority update mechanism to complete the arbitration within the leaf nodes and a lock-based round-robin search algorithm to guarantee global fairness. To reduce latency, the FSA keeps the lock structure only at the leaf node so that the complexity of the critical path does not increase. Meanwhile, the FSA achieves a critical path with only O(log4N) delay by using four input nodes in parallel. The latency of the proposed circuit is on average 22.2% better than the existing fair structures and 8.1% better than the fastest arbiter, according to the synthesis results. The proposed architecture is well suited for high-speed network-on-chip switches and has better scalability for switches with large numbers of ports.
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Nowak, Matt, and Brian Henderson. "Can High Density 3D Through Silicon Stacking Replace Lithography-Driven CMOS Scaling as the Engine for the Semiconductor Industry?" Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (2011): 000458–75. http://dx.doi.org/10.4071/2011dpc-ta12.
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High density 3D Through Silicon Stacking (TSS) offers opportunities for form factor miniaturization, cost reduction, and performance and energy improvement for advanced semiconductor systems. We will explore the value propositions for TSS compared to CMOS scaling to consider if TSS could replace lithography-driven CMOS scaling as the engine for the semiconductor industry. TSS can provide major reduction in volume form factor compared to 2D CMOS scaling. As the industry moves to advanced lithography and complex device structures at 16nm and below, the cost improvement resulting from CMOS scaling is expected to diminish. The cost reduction opportunities of TSS compared to traditional System on Chip (SOC) solutions enabled by lithography-driven CMOS scaling will be explored. The realized technology value propositions are strongly dependent on the specific system architecture and application. Architectural and software innovation enabled by HD 3D TSS and Architectural Pathfinding could provide an additional vector for continuing the improvements from semiconductor miniaturization.
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Malinowski, Marcin, Ricardo Bustos-Ramirez, Jean-Etienne Tremblay, et al. "Towards On-Chip Self-Referenced Frequency-Comb Sources Based on Semiconductor Mode-Locked Lasers." Micromachines 10, no. 6 (2019): 391. http://dx.doi.org/10.3390/mi10060391.
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Miniaturization of frequency-comb sources could open a host of potential applications in spectroscopy, biomedical monitoring, astronomy, microwave signal generation, and distribution of precise time or frequency across networks. This review article places emphasis on an architecture with a semiconductor mode-locked laser at the heart of the system and subsequent supercontinuum generation and carrier-envelope offset detection and stabilization in nonlinear integrated optics.
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Doraisamy, Radha, Minal Moharir, and Rajakumar Arul. "Congestion aware and game based odd even adaptive routing in network on chip many-core architecture." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (2022): 962. http://dx.doi.org/10.11591/ijeecs.v28.i2.pp962-972.
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The era of single processors had almost reached a saturation state, and the industry had moved to multi-core processors for the newer generation of many-core architecture. Interconnections between multiple cores with network on chip (NoC) surpass traditional bus architecture for its quality of service (QoS) and other additional services. Seamless communication among the cores is more significant for better performance and the proper utilization of the cores. The rise in the cores count in a semiconductor chip adds the complexity of the communication among cores. Cache misses request and packet transmission’s traffic possibly will reduce the performance of the architecture. A theoretical game-based methodology is proposed to improvise the performance and communication by routing the request packets in the NoC of the many core architectures and the throughput is maximized with reduced latency by using the stag-hunt game (SHG) model. The proposed communication algorithm routes the packets in an adaptive way by detecting the congestion in routers. The SHG based odd-even routing algorithm is adaptive and can divert the packets towards less congested routers using the information gathered about congestion in the system, so that the overall performance of the system in terms of latency and throughput is improved.
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Aziza, Hassen, Christian Dufaza, Annie Perez, and Said Hamdioui. "Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs." Journal of Circuits, Systems and Computers 28, no. 13 (2019): 1950216. http://dx.doi.org/10.1142/s0218126619502165.
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This paper introduces memristor-based operational amplifiers (OpAmps) in which semiconductor resistors are suppressed and replaced by memristors. The ability of the memristive elements to hold several resistance states is exploited to design programmable closed-loop OpAmps. An inverting OpAmp, an integrator and a differentiator are studied. Such designs are developed based on a calibrated memristor model, and offer dynamic configurability to realize different gains and corner frequencies at reduced chip area.
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DOERING, ROBERT R. "System-on-Chip Integration." International Journal of High Speed Electronics and Systems 12, no. 02 (2002): 325–32. http://dx.doi.org/10.1142/s0129156402001289.
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Numerous "signal-processing products" are now driving the semiconductor market for SOC solutions enabling real-time performance, low-cost, low-power, portability, etc. A primary limit on the types of electronic (or other) functions that will be integrated into future SOCs is cost of integration, which tends to grow non-linearly with process complexity and chip area. A near-continuum of System-on/in-X solutions is emerging between traditional System-on-Chip and System-on-Board. These approaches span the tradeoff between bandwidth and cost. For the foreseeable future, digital CMOS will continue to serve as a "host platform" for integrating a wide range of mechanical, optical, biological, and, perhaps, even "quantum" technologies.
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Zhang, Liang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, and Paul D. Franzon. "A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 9 (2009): 1267–74. http://dx.doi.org/10.1109/tvlsi.2008.2002682.
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This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.
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WANG, FANG. "INFLUENCE OF TRAFFIC CORRELATION ON THE PERFORMANCE OF NETWORK-ON-CHIP DESIGNS." Journal of Circuits, Systems and Computers 19, no. 03 (2010): 655–69. http://dx.doi.org/10.1142/s0218126610006347.
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Advance in semiconductor technologies enables seamless integration of hundreds of cores on a single silicon die, which requires high communication performance. To deal with the increasing communication complexity of System-on-Chip (SoC), Network-on-Chip (NoC) has been recently proposed as an alternative to the conventional point-to-point links and bus based communication fabrics. In practice, to facilitate NoC design evaluation and optimization, Poisson traffic or Bernoulli traffic models are generally assumed. However, actual measurements showed that real high speed network traffic always has strong correlations. The objective of this paper is to investigate the impact of traffic correlations on the performance of NoC design. Experimental results show that traffic correlation degrades the performance of NoC design and unrealistic traffic assumptions may yield unacceptable designs.
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Shi, Weiwei, Jinyong Zhang, Zhiguo Zhang, Lizhi Hu, and Yongqian Su. "An introduction and review on innovative silicon implementations of implantable/scalp EEG chips for data acquisition, seizure/behavior detection, and brain stimulation." Brain Science Advances 6, no. 3 (2020): 242–54. http://dx.doi.org/10.26599/bsa.2020.9050024.
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Technological advances in the semiconductor industry and the increasing demand and development of wearable medical systems have enabled the development of dedicated chips for complex electroencephalogram (EEG) signal processing with smart functions and artificial intelligence‐based detections/classifications. Around 10 million transistors are integrated into a 1 mm2 silicon wafer surface in the dedicated chip, making wearable EEG systems a powerful dedicated processor instead of a wireless raw data transceiver. The reduction of amplifiers and analog‐digital converters on the silicon surface makes it possible to place the analog front‐end circuits within a tiny packaged chip; therefore, enabling high‐count EEG acquisition channels. This article introduces and reviews the state‐of‐the‐art dedicated chip designs for EEG processing, particularly for wearable systems. Furthermore, the analog circuits and digital platforms are included, and the technical details of circuit topology and logic architecture are presented in detail.
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Wahida Binti Zulkefli, Farah, P. Ehkan, M. N. M. Warip, and Ng Yen Phing. "A efficacy of different buffer size on latency of network on chip (NoC)." Bulletin of Electrical Engineering and Informatics 8, no. 2 (2019): 438–42. http://dx.doi.org/10.11591/eei.v8i2.1422.
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Moore's prediction has been used to set targets for research and development in semiconductor industry for years now. A burgeoning number of processing cores on a chip demand competent and scalable communication architecture such as network-on-chip (NoC). NoC technology applies networking theory and methods to on-chip communication and brings noteworthy improvements over conventional bus and crossbar interconnections. Calculated performances such as latency, throughput, and bandwidth are characterized at design time to assured the performance of NoC. However, if communication pattern or parameters set like buffer size need to be altered, there might result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication while routers with small buffers reduce power consumption but result in high latency. This paper intention is to validate that size of buffer exert influence to NoC performance in several different network topologies. It is concluded that the way in which routers are interrelated or arranged affect NoC’s performance (latency) where different buffer sizes were adapted. That is why buffering requirements for different routers may vary based on their location in the network and the tasks assigned to them.
Dissertations / Theses on the topic "Semiconductor-on-Chip Architecture"
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Skopal, Miroslav. "Univerzální hardwarová platforma podporující operační systém Linux." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218709.
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This thesis deals with the development problems and creating of the multi- purpose hardware platform, which supports operating system Linux. It is focused on the microprocessors using ARM architecture with architecture ARM7, ARM9 and ARM11. The scope of the first part of this thesis was searching the sales of available 32 bit ARM microprocessors. The second part is attended to a particular Mini2440 development kit, its animation and the subsequent development of the kernel drivers for OS Linux platform. One of this thesis details was also the development of my own expansive hardware module and a capacity keypad for a usage with Mini2440 developmental kit.
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Satrawala, Amar Nath. "RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture." Thesis, 2009. https://etd.iisc.ac.in/handle/2005/1017.
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REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in the applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). Computer architectures based on the dynamic dataflow model of computation have to be an infinite resource implementation to be able to exploit all available parallelism in all applications. It is not feasible for any real architectural implementation. When limited resource implementations are considered, there is a possibility of loss of performance (inability to efficiently exploit available parallelism). In this thesis, we study the throttling of execution in the REDEFINE architecture to maximize the architecture efficiency. We have formulated it as a design space exploration problem at two levels i.e. architectural configurations and throttling schemes.
Reduced feature/high level simulation or feature specific analytical approaches are very useful for the selective study/exploration of early in design phase architectures/systems. Our approach is similar to that of SEASAME Framework which is used for the study of MPSoC (Multiprocessor SoC) architectures. We have used abstraction (feature reduction) at the levels of architecture and model of computation to make the problem approachable and practically feasible. A feature specific fast hybrid (mixed level) simulation framework for the early in design phase study is developed and implemented for the huge design space exploration (1284 throttling schemes, 128 architectural configurations and 10 applications i.e. 1.6 million executions).
We have done performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigation of the effectiveness of the design space exploration using statistical hypothesis testing. We found some interesting obvious/intuitive and some non-obvious/counterintuitive results. The two performance criteria namely Exec.T and Avg.TU were found sufficient to represent the performance and the resource usage characteristics of the architecture independent of the throttling schemes, the architectural configurations and the applications. The ranking of the throttling schemes based on the selected performance criteria is found to be statistically very significant. The intuitive throttling schemes span the range of performance from the best to the worst. We found absence of trade-off amongst all of the performance criteria. The best throttling schemes give appreciable overall performance (25%) and resource usage (37%) gains in the throttling unit simultaneously. The design space exploration of the throttling schemes is found to be fine and uniform.
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Satrawala, Amar Nath. "RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture." Thesis, 2009. http://hdl.handle.net/2005/1017.
Full textAbstract:
REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in the applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). Computer architectures based on the dynamic dataflow model of computation have to be an infinite resource implementation to be able to exploit all available parallelism in all applications. It is not feasible for any real architectural implementation. When limited resource implementations are considered, there is a possibility of loss of performance (inability to efficiently exploit available parallelism). In this thesis, we study the throttling of execution in the REDEFINE architecture to maximize the architecture efficiency. We have formulated it as a design space exploration problem at two levels i.e. architectural configurations and throttling schemes.
Reduced feature/high level simulation or feature specific analytical approaches are very useful for the selective study/exploration of early in design phase architectures/systems. Our approach is similar to that of SEASAME Framework which is used for the study of MPSoC (Multiprocessor SoC) architectures. We have used abstraction (feature reduction) at the levels of architecture and model of computation to make the problem approachable and practically feasible. A feature specific fast hybrid (mixed level) simulation framework for the early in design phase study is developed and implemented for the huge design space exploration (1284 throttling schemes, 128 architectural configurations and 10 applications i.e. 1.6 million executions).
We have done performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigation of the effectiveness of the design space exploration using statistical hypothesis testing. We found some interesting obvious/intuitive and some non-obvious/counterintuitive results. The two performance criteria namely Exec.T and Avg.TU were found sufficient to represent the performance and the resource usage characteristics of the architecture independent of the throttling schemes, the architectural configurations and the applications. The ranking of the throttling schemes based on the selected performance criteria is found to be statistically very significant. The intuitive throttling schemes span the range of performance from the best to the worst. We found absence of trade-off amongst all of the performance criteria. The best throttling schemes give appreciable overall performance (25%) and resource usage (37%) gains in the throttling unit simultaneously. The design space exploration of the throttling schemes is found to be fine and uniform.
Book chapters on the topic "Semiconductor-on-Chip Architecture"
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Herkersdorf, Andreas, Michael Engel, Michael Glaß, et al. "RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_1.
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AbstractThe Resilience Articulation Point (RAP) model aims to provision a probabilistic fault abstraction and error propagation concept for various forms of variability related faults in deep sub-micron CMOS technologies at the semiconductor material or device levels. RAP assumes that each of such physical faults will eventually manifest as a single- or multi-bit binary signal inversion or out-of-specification delay in a signal transition between bit values. When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, finite state machine (FSM) states, IP macro-interfaces, or software variables. Thus, design concerns can be investigated at higher abstraction layers without the necessity to further consider the full details of lower levels of design. This chapter introduces the ideas of RAP based on examples of particle strike, noise and voltage drop induced bit errors in SRAM cells. Furthermore, we show by different examples how probabilistic bit flips are systematically abstracted and propagated towards instruction and data vulnerability at MPSoC architecture level, and how RAP can be applied for dynamic testing and application-level optimizations in an autonomous robot scenario.
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Mele, Filippo. "Application Specific Integrated Circuits for High Resolution X and Gamma Ray Semiconductor Detectors." In Special Topics in Information Technology. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-85918-3_3.
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AbstractThe increasing demand for performance improvements in radiation detectors, driven by cutting-edge research in nuclear physics, astrophysics and medical imaging, is causing not only a proliferation in the variety of the radiation sensors, but also a growing necessity of tailored solutions for the front-end readout electronics. Within this work, novel solutions for application specific integrated circuits (ASICs) adopted in high-resolution X and $$\upgamma $$ γ ray spectroscopy applications are studied. In the first part of this work, an ultra-low noise charge sensitive amplifier (CSA) is presented, with specific focus on sub-microsecond filtering, addressing the growing interest in high-luminosity experiments. The CSA demonstrated excellent results with Silicon Drift Detectors (SDDs), and with room temperature Cadmium-Telluride (CdTe) detectors, recording a state-of-the-art noise performance. The integration of the CSA within two full-custom radiation detection instruments realized for the ELETTRA (Trieste, Italy) and SESAME (Allan, Jordan) synchrotrons is also presented. In the second part of this work, an ASIC constellation designed for X-Gamma imaging spectrometer (XGIS) onboard of the THESEUS space mission is described. The presented readout ASIC has a highly customized distributed architecture, and integrates a complete on-chip signal filtering, acquisition and digitization with an ultra-low power consumption.
Conference papers on the topic "Semiconductor-on-Chip Architecture"
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Parameswaran, Suresh, Gamal Refai-Ahmed, Suresh Ramalingam, and Boon Ang. "Next Gen Test-Vehicle to Simulate Thermal Load for IoT FPGA Applications." In ASME 2018 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2018. http://dx.doi.org/10.1115/ipack2018-8300.
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As semiconductor device feature size scales and circuit performance increases, power dissipation and thermal management are becoming very important. Attention to thermal considerations is required throughout the chip development cycle from preliminary architecture planning to deployment on customer board and beyond. This paper describes a versatile thermal test vehicle that can be used to address these requirements. We discuss the architecture and implementation of a specially designed test-vehicle chip, followed by its operation. The programmability and flexibility of this vehicle will be highlighted. In addition, we cover other usage of this vehicle which includes modelling of chip-level thermal behavior with different floorplan, simulating thermal loads in IoT FPGA applications, cross-calibrating thermal numerical simulators with measured silicon data and evaluating the thermal impact of different package form-factor / material (such as thermal interface material) and cooling solutions. The abovementioned chip was fabricated using 0.18um technology and assembled in a flip-chip package. The reminder of this evaluation system is a simple, inexpensive tester from which a software is run to program the chip and to measure the spatial & temporal temperature values. Measured thermal data from different use cases are presented in this paper.
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Nair, Arya Sukumaran, Peter Hoffrogge, Peter Czurratis, et al. "1D-ResNet Framework for Ultrasound Signal Classification." In ISTFA 2022. ASM International, 2022. http://dx.doi.org/10.31399/asm.cp.istfa2022p0021.
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Abstract Minor flaws are becoming extremely relevant as the complexity of the semiconductor package evolves. Scanning acoustic microscopy is one analytical tool for detecting flaws in such a complex package. Minor changes in the reflected signal that could indicate a fault can be lost during image reconstruction, despite the high sensitivity. Because of recent AI (Artificial Intelligence) advancements, more emphasis is being placed on developing AI-based algorithms for high precision-automated signal interpretation for failure detection. This paper presents a new deep learning model for classifying ultrasound signals based on the ResNet architecture with 1D convolution layers. The developed model was validated on two test case scenarios. One use case was the detection of voids in the die attach, the other the detection of cracks below bumps in Flip-chip samples. The model was trained to classify signals into different classes. Even with a small dataset, experiment results confirmed that the model predicts with a 98 percent accuracy. This type of signal-based model could be extremely useful in situations where obtaining large amounts of labeled image data is difficult. Through this work we propose an intelligent signal classification methodology to automate high volume failure analysis in semiconductor devices.
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Demarest, J., K. Brew, H. Jagannathan, et al. "Elemental TEM Tomography of Phase Change Memory Artificial Intelligence Hardware Case Study." In ISTFA 2020. ASM International, 2020. http://dx.doi.org/10.31399/asm.cp.istfa2020p0198.
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Abstract Power consumption of conventional CMOS semiconductor architectures has grown to the point where novel structures need to be introduced to mitigate the power load within the chip. The introduction of the specialized artificial intelligence devices goes hand in hand with the inception of novel materials and processes into conventional semiconductor fabrication, which drives the need for expanding the host of failure analysis techniques and diagnostic capabilities. This paper describes a case study of elemental transmission electron microscopy tomography on an exploratory phase change memory test structure and comments upon some technique observations: advantages and disadvantages.
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Zhou, J., A. M. Kriman, and D. K. Ferry. "Transient Simulation of Ultra-Small GaAs MESFET Using Quantum Moment Equations." In Picosecond Electronics and Optoelectronics. Optica Publishing Group, 1991. http://dx.doi.org/10.1364/peo.1991.we1.
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Since the advent of the integrated circuits in the late 1950’s, the number of devices contained on a single chip has approximately doubled every three years and this process has caused semiconductor devices to be made smaller and smaller. However, little is understood about the physical limitations that will determine whether or not these devices are practical. These questions have opened a new field for semiconductor research and technology in which a great opportunity is provided to study many new physical phenomena, some of which have been described in [1-4], and exploring a new generation of device structures and system architectures for the potential application of Ultra Large Scale Integrated (ULSI) system in the near future.
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Lagorio, E. "System on chip architecture for AugerPrime surface detector electronics upgrade of the pierre auger observatory." In 2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD). IEEE, 2016. http://dx.doi.org/10.1109/nssmic.2016.8069731.
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Lall, Pradeep, Shantanu Deshpande, and Luu Nguyen. "Copper, Silver, and PCC Wirebonds Reliability in Automotive Underhood Environments." In ASME 2018 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2018. http://dx.doi.org/10.1115/ipack2018-8358.
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Wire bonding is popular first-level interconnect method used in the semiconductor device packaging. Gold (Ag) wire is often used in high-reliability applications. Typical wire diameters vary between 0.8mil to 2mil. Recent increases in the gold-price have motivated the industry to search for alternate materials candidates for use in wirebonding. Three of the leading candidates are Silver (Ag), Copper (Cu), and Palladium Coated Copper (PCC). The new material candidates are inexpensive in comparison with gold and may have better electrical, and thermal properties, which is advantageous for fine pitch-high density electronics. The transition, however, comes along with few trade-offs such as narrow process window, higher wire-hardness, increased propensity for chip-cratering, lack of reliability knowledge base of when deployed in harsh environment applications. Relationship between mechanical degradation of the wirebond and the change in electric response needs to be established for better understanding of the failure modes and their respective mechanisms. Understanding the physics of damage progression may provide insights into the process parameters for manufacture of more robust interconnects. In this paper, a detailed study of the electrical and mechanical degradation of wirebonds under high temperature exposure is presented. Four wirebond candidates (Au, Ag, Cu and PCC) bonded onto Aluminum (Al) pad were subjected to high temperature storage life until failure to study the degradation of the bond-wire interface. Same package architecture and electronic molding compound (EMC) were used for all four candidates. Detailed analysis of intermetallic (IMC) phase evolution is presented along with quantification of the phases and their evolution over time. Ball shear strength was measured after decapsulation. Measurements of shear strength, shear failure modes, and IMC composition have been correlated with the change in the electrical response. Change in shear strength and different shear failure modes for different wirebond systems are discussed in the paper.