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Dissertations / Theses on the topic 'Semiconductor storage devices'

Author: Grafiati
Published: 4 June 2021
Last updated: 30 July 2024

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1

Sudirgo, Stephen. "Quantum and spin-based tunneling devices for memory systems /." Link to online version, 2006. https://ritdml.rit.edu/dspace/handle/1850/2066.

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2

Chan, Wan Tim. "CMOS-compatible zero-mask one time programmable (OTP) memory design /." View abstract or full-text, 2008. http://library.ust.hk/cgi/db/thesis.pl?ECED%202008%20CHANW.

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3

Barclay, Martin Jared. "Electrical switching properties of ternary and layered chalcogenide phase-change memory devices." [Boise, Idaho] : Boise State University, 2009. http://scholarworks.boisestate.edu/td/67/.

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4

Garud, Niharika Triplett Gregory Edward. "Shallow trench isolation process in microfabrication for flash (NAND) memory." Diss., Columbia, Mo. : University of Missouri-Columbia, 2008. http://hdl.handle.net/10355/5622.

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Thesis (M.S.)--University of Missouri-Columbia, 2008.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on September 2, 2008) Includes bibliographical references.
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5

Ketrick, Robert Paul. "Design, fabrication and implementation of a hash table processor /." Online version of thesis, 1987. http://hdl.handle.net/1850/10497.

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6

Fullem, Travis Z. "Radiation detection using single event upsets in memory chips." Diss., Online access via UMI:, 2006.

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7

Fang, Jun. "Design of an ATM switch and implementation of output scheduler /." Title page, contents and abstract only, 1999. http://web4.library.adelaide.edu.au/theses/09ENS/09ensf211.pdf.

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8

Lee, Yung-Huei. "Dual-carrier charge transport and damage formation of LPCVD nitride for nonvolatile memory devices /." The Ohio State University, 1986. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487322984316841.

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9

Barsatan, Randy. "CMOS-compatible nonvolatile memories for radio frequency identification (RFID) applications /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20BARSAT.

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10

Xiang, Jing. "Electrofunctional ferrocene-containing metallopolymers for organic lithium-ion battery and organic resistive memory applications." HKBU Institutional Repository, 2016. https://repository.hkbu.edu.hk/etd_oa/286.

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This thesis is dedicated to developing three different types of ferrocene-containing polymers for organic lithium-ion battery and resistive memory applications. Chapter 1 gives an overview of organic cathode-active materials, polymeric resistive memories and ferrocene-containing polymers. Furthermore, the previously reported applications of ferrocene-containing polymeric systems in electrochemical energy storage and electronical memory devices were also comprehensively summarized. In chapter 2, conjugated ferrocene-containing side-chain metallopolymers PFcFE1, PFcFE2, PFcFE3 and PFcFE4 were designed and synthesized via Sonogashira cross-coupling polycondensation. The charging-discharging processes of triphenyamine-based PFcFE1 and thiophene-modified PFcFE4 have been successfully studied as cathode materials. PFcFE1 composite electrode showed a capacity of 90 mAh g-1 and the cathode composed of PFcFE4 retained over 90% of the initial capacity after 100 charging-discharging cycles at 10 C. These results demonstrate the great potentials of these ferrocene-containing side-chain polymers as active cathode materials for organic lithium-ion battery applicaitons. Besides, all prepared ferrocene-containing metallopolymers PFcFE1, PFcFE2, PFcFE3 and PFcFE4 also exhibited nonvolatile resistive switching behaviors with the flash memory effect of PFcFE1, PFcFE2 and PFcFE3 as well as the WORM memory feature of PFcFE4, indicating the easily tuned memory properties by changing the chemical structures of the active polymeric backbones. It is also worth noting that the ITO/PFcFE1/Al memory device showed a high ON/OFF current ratio of 103 to 104, a low switch-on voltage of -1.0 V, a long retention time of 1000 s and a large read cycle number up to 105, which is superior to other reported ferrocene-containing memory examples. Chapter 3 focuses on the development of non-conjugated ferrocene-containing copolymers PVFVM1, PVFVM1-1, PVFVM2, PVFVM3, PVFVM4, PVFVM5 and PVFVM6 based on different heteroaromatic moieties which were prepared by AIBN initiated chain addition polymerization. The as-prepared copolymers PVFVM1 and PVFVM1-1 exhibited electrochemical characteristics of both ferrocene and triphenylamine pendants with reversible multiple redox waves at the half potentials of E1/2 = --0.06, 0.30, and 0.42 V (vs. Fc/Fc+). Notably, the composite electrode based on PVFVM1 afforded a discharge capacity of 102 mAh g--1 at 10 C, corresponding to 98% of its theoretical capacity. The cycle endurances of the active polymer electrodes composed of PVFVM1 or PVFVM1-1 were both evaluated for over 50 numbers and no significant capacity reduction over cycles were observed. On the other hand, initial I-V results of memory devices based on PVFVM1, PVFVM1-1, PVFVM2, PVFVM3, PVFVM4 and PVFVM6 also revealed their huge potentials in electronic information storage. The stability and reproducibility of the corresponding memory devices based on these materials will be futher evaluated in the near future. We used 1,1'-ferrocenediboronic acid bis(pinacol) ester to develop conjugated ferrocene-containing main-chain metallopolymers in chapter 4. All these rational designed metallopolymers FcMMP1, FcMMP2, FcMMP3 and FcMMP4 with one or two ferrocene moieties were produced via Suzuki cross-coupling polycondensation. Their structural information, molecular masses, photophysical features and thermal properties have been well studied. Electrochemical performances of the formed polymers were also examined to clarify their potential as cathode-active materials. Other charge-storage characteristics and switching behaviors of these prepared ferrocene-containing main-chain metallopolymers for organic battery and memory applications are under further investigation.
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11

Yuen, Kam Hung. "A nano-scale double-gate flash memory /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20YUEN.

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12

Balasubramanian, Mahesh. "Phase change memory : array development and sensing circuits using delta-sigma modulation /." [Boise, Idaho] : Boise State University, 2009. http://scholarworks.boisestate.edu/td/44/.

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13

McGeever, Michael K. "Design of a very high speed dynamic RAM in gallium arsenide for an ATM switch /." Title page, contents and abstact only, 1995. http://web4.library.adelaide.edu.au/theses/09PH/09phm1449.pdf.

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14

Akeyo, Oluwaseun M. "ANALYSIS AND SIMULATION OF PHOTOVOLTAIC SYSTEMS INCORPORATING BATTERY ENERGY STORAGE." UKnowledge, 2017. http://uknowledge.uky.edu/ece_etds/107.

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Solar energy is an abundant renewable source, which is expected to play an increasing role in the grid's future infrastructure for distributed generation. The research described in the thesis focuses on the analysis of integrating multi-megawatt photovoltaics (PV) systems with battery energy storage into the existing grid and on the theory supporting the electrical operation of components and systems. The PV system is divided into several sections, each having its own DC-DC converter for maximum power point tracking and a two-level grid connected inverter with different control strategies. The functions of the battery are explored by connecting it to the system in order to prevent possible voltage fluctuations and as a buffer storage in order to eliminate the power mismatch between PV array generation and load demand. Computer models of the system are developed and implemented using the PSCADTM/EMTDCTM software.
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15

Lashway, Christopher R. "Resilient and Real-time Control for the Optimum Management of Hybrid Energy Storage Systems with Distributed Dynamic Demands." FIU Digital Commons, 2017. https://digitalcommons.fiu.edu/etd/3515.

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A continuous increase in demands from the utility grid and traction applications have steered public attention toward the integration of energy storage (ES) and hybrid ES (HESS) solutions. Modern technologies are no longer limited to batteries, but can include supercapacitors (SC) and flywheel electromechanical ES well. However, insufficient control and algorithms to monitor these devices can result in a wide range of operational issues. A modern day control platform must have a deep understanding of the source. In this dissertation, specialized modular Energy Storage Management Controllers (ESMC) were developed to interface with a variety of ES devices. The EMSC provides the capability to individually monitor and control a wide range of different ES, enabling the extraction of an ES module within a series array to charge or conduct maintenance, while remaining storage can still function to serve a demand. Enhancements and testing of the ESMC are explored in not only interfacing of multiple ES and HESS, but also as a platform to improve management algorithms. There is an imperative need to provide a bridge between the depth of the electrochemical physics of the battery and the power engineering sector, a feat which was accomplished over the course of this work. First, the ESMC was tested on a lead acid battery array to verify its capabilities. Next, physics-based models of lead acid and lithium ion batteries lead to the improvement of both online battery management and established multiple metrics to assess their lifetime, or state of health. Three unique HESS were then tested and evaluated for different applications and purposes. First, a hybrid battery and SC HESS was designed and tested for shipboard power systems. Next, a lithium ion battery and SC HESS was utilized for an electric vehicle application, with the goal to reduce cycling on the battery. Finally, a lead acid battery and flywheel ES HESS was analyzed for how the inclusion of a battery can provide a dramatic improvement in the power quality versus flywheel ES alone.
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16

Wu, Weimin. "Materials for organic memory devices." HKBU Institutional Repository, 2009. http://repository.hkbu.edu.hk/etd_ra/1084.

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17

Chen, Danti. "Local electron transport of organic semiconducting monolayers /." Connect to online version, 2009. http://ada.mtholyoke.edu/setr/websrc/pdfs/www/2009/363.pdf.

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18

Jun, Zhang, Zhang Qishan, Zhang Zhihui, and Huang Jian. "A New Approach to Telemetry Data Decomposition and Analysis Based on Large-Capacity Semiconductor RAM." International Foundation for Telemetering, 1993. http://hdl.handle.net/10150/611858.

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International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada
With the development of microelectronics and computer technology, telemetry computer systems are demanded to provide larger storage capacity and higher storage data rate than ever before. This paper fully considers various factors of a high-speed PCM fiber-optic telemetry system such as data format, data rate, data storage, the width of data storage, storage data rate. All these considerations lead to a new scheme with a semiconductor RAM and a dedicated program as its basic idea. This scheme chooses 1Mbits or 4Mbits static-RAM chips to implement the telemetry data storage device with a total capacity of 4Mbytes, 16Mbytes, or 64Mbytes. The software running on COMPAQ 386/25M or its compatibles is written in Turbo C 2. 0 to fetch, decompose, display and process data stored in the large-capacity RAM. The main task of the system processing software is to identify the flag words of frame sync-code -pattern and then demultiplex the data into separate channel data to be stored in the disk. Besides the ability to recognize specific data format, the software can also rectify data confusion to some extent. The scheme has already been proved to be efficient to receive large capacity of data with features of high data rate, high data storage in a short time.
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19

Gray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.

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Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation. An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT. Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA.
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20

Horikawa, Tsuyoshi. "A study of advanced integrated semiconductor device and process technologies for data storage and transmission." 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/215222.

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21

Kovaltchouk, Thibaut. "Contributions à la co-optimisation contrôle-dimensionnement sur cycle de vie sous contrainte réseau des houlogénérateurs directs." Thesis, Cachan, Ecole normale supérieure, 2015. http://www.theses.fr/2015DENS0033/document.

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Les Energies Marines Renouvelables (EMR) se développent aujourd’hui très vite tant au niveau de la recherche amont que de la R&D, et même des premiers démonstrateurs à la mer. Parmi ces EMR, l'énergie des vagues présente un potentiel particulièrement intéressant. Avec une ressource annuelle brute moyenne estimée à 40 kW/m au large de la côte atlantique, le littoral français est plutôt bien exposé. Mais l’exploitation à grande échelle de cette énergie renouvelable ne sera réalisable et pertinente qu'à condition d'une bonne intégration au réseau électrique (qualité) ainsi que d'une gestion et d'un dimensionnement optimisé au sens du coût sur cycle de vie. Une première solution de génération tout électrique pour un houlogénérateur a d’abord été évaluée dans le cadre de la thèse de Marie RUELLAN menée sur le site de Bretagne du laboratoire SATIE (ENS de Cachan). Ces travaux ont mis en évidence le potentiel de viabilité économique de cette chaîne de conversion et ont permis de poser la question du dimensionnement de l’ensemble convertisseur-machine et de soulever les problèmes associés à la qualité de l’énergie produite. Puis une seconde thèse a été menée par Judicaël AUBRY dans la même équipe de recherche. Elle a consisté, entre autres, en l’étude d’une première solution de traitement des fluctuations de la puissance basée sur un système de stockage par supercondensateurs. Une méthodologie de dimensionnement de l’ensemble convertisseur-machine et de gestion de l’énergie stockée fut également élaborée, mais en découplant le dimensionnement et la gestion de la production d’énergie et de ceux de son système de stockage. Le doctorant devra donc : 1. S’approprier les travaux antérieurs réalisés dans le domaine de la récupération de l’énergie des vagues ainsi que les modèles hydrodynamiques et mécaniques réalisés par notre partenaire : le LHEEA de l’Ecole Centrale de Nantes - 2. Résoudre le problème du couplage entre dimensionnement/gestion de la chaîne de conversion et dimensionnement/gestion du système de stockage. 3. Participer à la réalisation d’un banc test à échelle réduite de la chaine électrique et valider expérimentalement les modèles énergétiques du stockage et des convertisseurs statiques associés - 4. Proposer une méthodologie de dimensionnement de la chaine électrique intégrant le stockage et les lois de contrôle préalablement élaborées 5. Déterminer les gains en termes de capacités de stockage obtenus grâce à la mutualisation de la production (parc de machines) et évaluer l’intérêt d’un stockage centralisé - 6. Analyser l’impact sur le réseau d’une production houlogénérée selon divers scenarii, modèles et outils développés par tous les partenaires dans le cadre du projet QUALIPHE. L’exemple traité sera celui de l’Ile d’Yeu (en collaboration avec le SyDEV
The work of this PhD thesis deals with the minimization of the per-kWh cost of direct-drive wave energy converter, crucial to the economic feasibility of this technology. Despite the simplicity of such a chain (that should provide a better reliability compared to indirect chain), the conversion principle uses an oscillating system (a heaving buoy for example) that induces significant power fluctuations on the production. Without precautions, such fluctuations can lead to: a low global efficiency, an accelerated aging of the fragile electrical components and a failure to respect power quality constraints. To solve these issues, we firstly study the optimization of the direct drive wave energy converter control in order to increase the global energy efficiency (from wave to grid), considering conversion losses and the limit s from the sizing of an electrical chain (maximum force and power). The results point out the effect of the prediction horizon or the mechanical energy into the objective function. Production profiles allow the study of the flicker constraint (due to grid voltage fluctuations) linked notably to the grid characteristics at the connection point. Other models have also been developed to quantify the aging of the most fragile and highly stressed components, namely the energy storage system used for power smoothing (with super capacitors or electrochemical batteries Li-ion) and power semiconductors.Finally, these aging models are used to optimize key design parameters using life-cycle analysis. Moreover, the sizing of the storage system is co-optimized with the smoothing management
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Yang, Yang. "The retention reliability of scaled SONOS devices /." Diss., 1999. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:9935187.

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23

Wang, Yu. "Uniform and localized charge-trapping in SONOS nonvolatile memory devices /." Diss., 2005. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3167086.

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24

Wrazien, Stephen J. "Characterization of SONOS nonvolatile semiconductor memory (NVSM) devices for space and military applications /." Diss., 2005. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3167087.

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25

Bu, Jiankang. "Polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memory devices design, fabrication and characterization /." Diss., 2001. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3010398.

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26

Lee, Jong Jin Kwong Dim-Lee. "A study on the nanocrystal floating-gate nonvolatile memory." 2005. http://repositories.lib.utexas.edu/bitstream/handle/2152/1975/leej77040.pdf.

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Lee, Jong Jin. "A study on the nanocrystal floating-gate nonvolatile memory." Thesis, 2005. http://hdl.handle.net/2152/1975.

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Liu, Yueran 1975. "Novel flash memory with nanocrystal floating gate." Thesis, 2006. http://hdl.handle.net/2152/2819.

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Han, Jeong Hee. "Electrical characterization of doped strontium titanate thin films for semiconductor memories." Thesis, 2002. http://wwwlib.umi.com/cr/utexas/fullcit?p3099459.

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30

Khan, Faraz I. "Endurance characterization and improvement of floating gate semiconductor memory devices." 2009. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000051734.

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31

Sarkar, Joy 1977. "Non-volatile memory devices beyond process-scaled planar Flash technology." Thesis, 2007. http://hdl.handle.net/2152/3666.

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Mainstream non-volatile memory technology dominated by the planar Flash transistor with continuous floating-gate has been historically improved in density and performance primarily by means of process scaling, but is currently faced with significant hindrances to its future scaling due to fundamental constraints of electrostatics and reliability. This dissertation is based on exploring two pathways for circumventing scaling limitations of the state-of-the-art Flash memory technology. The first part of the dissertation is based on demonstrating a vertical Flash memory transistor with nanocrystal floating-gate, while the second part is based on developing fundamental understanding of the operation of Phase Change Memory. A vertical Flash transistor can allow the theoretical minimum cell area and a nanocrystal floating-gate on the sidewalls is shown to allow a thinner gate-stack further conducive to scaling while still providing good reliability. Subsequently, the application of a technique of protein-mediated assembly of preformed nanocrystals to the sidewalls of the vertical Flash transistor is also demonstrated and characterized. This technique of ordering pre-formed nanocrystals is beneficial towards achieving reproducible nanocrystal size uniformity and ordering especially in a highly scaled vertical Flash cell, rendering it more amenable to scaling and manufacturability. In both forms, the vertical Flash memory cell is shown to have good electrical characteristics and reliability for the viability of this cell design and implementation. In the remaining part of this dissertation, studies are undertaken towards developing fundamental understanding of the operational characteristics of Phase Change Memory (PCM) technology that is expected to replace floating-gate Flash technology based on its potential for scaling. First, a phenomenon of improving figures of merit of the PCM cell with operational cycles is electrically characterized. Based on the electrical characterization and published material characterization data, a physical model of an evolving "active region" of the cell is proposed to explain the improvement of the cell parameters with operational cycles. Then, basic understanding is developed on early and erratic retention failure in a statistically significant number of cells in a large array and, electrical characterization and physical modeling is used to explain the mechanism behind the early retention failure.
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Tang, Shan 1975. "Protein-mediated nanocrystal assembly for floating gate flash memory fabrication." 2008. http://hdl.handle.net/2152/18156.

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As semiconductor device scaling is reaching the 45 nm node, the need for novel device concept, architecture and new materials has never been so pressing as today. Flash memories, the driving force of semiconductor memory market in recent years, also face the same or maybe more severe challenges to meet the demands for high-density, low-cost, low-power, high-speed, better endurance and longer retention time. As traditional continuous floating gate flash struggles to balance the trade-off between high speed and retention requirement, nanocrystal (NC) floating gate flash has attracted more and more interest recently due to its advantages over traditional flash memories in many areas such as better device scaling, lower power consumption and improved charge retention. However, there are still two major challenges remaining for embedded NC synthesis: the deposition method and the size and distribution control. Nowadays using bio-nano techniques such as DNA, virus or protein for NC synthesis and assembly has become a hot topic and feasible for actual electronic device fabrication. In this dissertation a new method for NC deposition wherein a colloidal suspension of commercially-available NCs was organized using a self-assembled chaperonin array. The chaperonin array was applied as a scaffold to mediate NCs into an assembly with uniform spatial distribution on Si wafers. By using this method, we demonstrated that colloidal PbSe and Co NCs in suspension can self-assemble into ordered arrays with a high density of up to 10¹²cm⁻². MOSCAP and MOSFET memory devices were successfully fabricated with the chaperonin protein mediated NCs, showing promising memory functions such as a large charge storage capacity, long retention time and good endurance. The charge storage capacity with respect to material work function, NC size and density was explored. In addition to NC engineering, the tunnel barrier was engineered by replacing traditional SiO₂ by high-k material HfO₂, giving a higher write/erase speed with a reduced effective oxide thickness (EOT). Suggestions for future research in this direction are presented in the last part of this work.
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33

McGeever, Michael K. "Design of a very high speed dynamic RAM in gallium arsenide for an ATM switch / Michael K. McGeever." Thesis, 1995. http://hdl.handle.net/2440/19075.

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Bibliography: leaves 156-165.
xvi, 174 leaves : ill. ; 30 cm.
This thesis analyses the design of a Dynamic RAM in gallium arsenide for use as a buffer in an ATM switch. The causes of leakage are investigated and methods to overcome or compensate the leakage are devised, resulting in a memory cell with a large storage time, high speed and low power dissipation. A 14 kbit RAM array is designed and laid out in gallium arsenide. The RAM array is designed to operate over a -25oC to +125oC temperature range using process parameters which vary by up to 2 [sigma] from typical.
Thesis (M.Eng.Sc.)--University of Adelaide, Dept. of Electrical & Electronic Engineering, 1996?
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Heng, C. L., Wee Kiong Choi, Wai Kin Chim, L. W. Teo, Vincent Ho, W. W. Tjiu, and Dimitri A. Antoniadis. "Charge Storage Effect in a Trilayer Structure Comprising Germanium Nanocrystals." 2002. http://hdl.handle.net/1721.1/3969.

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A metal-insulator-semiconductor (MIS) device with a trilayer insulator structure consisting of sputtered SiO₂ (~50nm)/evaporated pure germanium (Ge) layer (2.4nm)/rapid thermal oxide (~5nm) was fabricated on a p-type Si substrate. The MIS device was rapid thermal annealed at 1000°C. Capacitance-voltage (C-V) measurements showed that, after rapid thermal annealing at 1000°C for 300s in Ar, the trilayer device exhibited charge storage property. The charge storage effect was not observed in a device with a bilayer structure without the Ge middle layer. With increasing rapid thermal annealing time from 0 to 400s, the width of the C-V hysteresis of the trilayer device increased significantly from 1.5V to ~11V, indicating that the charge storage capability was enhanced with increasing annealing time. High-resolution transmission electron microscopy results confirmed that with increasing annealing time, the 2.4nm amorphous middle Ge layer crystallized gradually. More Ge nanocrystals were formed and the crystallinity of the Ge layer improved as the annealing time was increased. When the measurement temperature was increased from –50°C to 150°C, the width of the hysteresis of the MIS device reduced from ~10V to ~6V. This means that the charge storage capability of the trilayer structure decreases with increasing measurement temperature. This is due to the fact that the leakage current in the trilayer structure increases with increasing measurement temperature.
Singapore-MIT Alliance (SMA)
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35

Teo, L. W., Van Tai Ho, M. S. Tay, Y. Lei, Wee Kiong Choi, Wai Kin Chim, Dimitri A. Antoniadis, and Eugene A. Fitzgerald. "Charge Storage Mechanism and Size Control of Germanium Nanocrystals in a Tri-layer Insulator Structure of a MIS Memory Device." 2003. http://hdl.handle.net/1721.1/3712.

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A method of synthesizing and controlling the size of germanium nanocrystals is developed. A tri-layer metal-insulator-semiconductor (MIS) memory device structure comprising of a thin (~5nm) silicon dioxide (SiO₂) layer grown using rapid thermal oxidation (RTO), followed by a layer of Ge+SiO₂ of varying thickness (3 - 6 nm) deposited using a radio frequency (rf) co-sputtering technique, and a capping SiO₂ layer (50nm) deposited using rf sputtering is investigated. It was verified that the size of germanium (Ge) nanocrystals in the vertical z-direction in the trilayer memory device was controlled by varying the thickness of the middle (cosputtered Ge+SiO₂) layer. From analyses using transmission electron microscopy and capacitance-voltage measurements, we deduced that both electrons and holes are most likely stored within the nanocrystals in the middle layer of the trilayer structure rather than at the interfaces of the nanocrystals with the oxide matrix.
Singapore-MIT Alliance (SMA)
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