Journal articles: 'Semiconductor wafers. Silicon Silicon Electrodiffusion'

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Jennings, Michael R., Amador Pérez-Tomás, Owen J. Guy, Michal Lodzinski, Peter M. Gammon, Susan E. Burrows, James A. Covington, and Philip A. Mawby. "Silicon-on-SiC, a Novel Semiconductor Structure for Power Devices." Materials Science Forum 645-648 (April 2010): 1243–46. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1243.

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A physical and electrical analysis of Si/SiC heterojunctions formed by layer transfer based on the smartcut® process is presented in this paper. AFM and SEM have revealed a high bonding quality when Si wafers are transferred to SiC on-axis wafers. XRD points to the fact that the layers are monocrystalline in nature. A surface AFM analysis of the bonded wafers demonstrated a smooth surface (rms = 5.8 nm) suitable for semiconductor device fabrication. Capacitors have been fabricated from the Si/SiC heterojunctions, which have been totally oxidised. Oxidised Si/SiC structures yielded a lower density of interface states than conventional thermal oxidation techniques.

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Oliver, James D., Russ Kremer, Arnd Dietrich Weber, Kevin Nguyen, and James Amano. "SEMI Standards for SiC Wafers." Materials Science Forum 924 (June 2018): 5–10. http://dx.doi.org/10.4028/www.scientific.net/msf.924.5.

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SEMI Standards charter is to develop standards that benefit the semiconductor industry. The SEMI organization has evolved over the last 40 years into an international organization with covering all aspects of semiconductor and flat panel materials and devices. SEMI Standards provides the framework for the development of consensus based standards documents. At present there are two published standards specific to silicon carbide, the first dealing with dimensions, properties and ordering information for SiC wafers, and the second defining a nomenclature for defects found on SiC: SEMI M55-0817 Specification for Polished Monocrystalline Silicon Carbide Wafers SEMI M81-0611 Guide to Defects Found on Monocrystalline Silicon Carbide Substrates Additional standards applicable to various semiconductor wafers also are available and new SiC related standards are being developed based on industry needs and volunteer participation.

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FUKUDA, Tetsuo, Atsunobu UNE, Akira FUKUDA, and Yasuhide NAKAI. "1601 Mechanical Issues of Silicon Wafers for Semiconductor Devices." Proceedings of The Computational Mechanics Conference 2009.22 (2009): 534–35. http://dx.doi.org/10.1299/jsmecmd.2009.22.534.

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Sianko, S. F., and V. A. Zelenin. "ESTIMATION OF TOPOGRAPHIC DEFECTS DIMENSIONS OF SEMICONDUCTOR SILICON STRUCTURES." Devices and Methods of Measurements 9, no. 1 (March 20, 2018): 74–84. http://dx.doi.org/10.21122/2220-9506-2018-9-1-74-84.

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The effect of non-flatness of semiconductor wafers on characteristics of manufactured devices is shown through defocusing of an image of a topological layout of a structure being formed and through reduction of resolution at photolithographic processing. For quality control of non-flatness the Makyoh method is widely used. However, it does not allow obtaining quantitative characteristics of observed defects, which essentially restricts its application. The objective of this work has been developing of a calculation method for dimensions of topographic defects of wafers having semiconductor structures formed on them, which has allowed determining acceptability criteria for wafers, depending on defects dimensions and conducting their timely penalization.A calculation method under development is based on deduction of relationships linking distortion of image elements to curvature of local sections of a semiconductor wafer that has formed structures. These structures have been considered to be image finite elements and within this range the curvature radius has been assumed to be constant. Sequential calculation of deviation of element ends from ideal plane based on determining their curvature radius has allowed obtaining geometry of a target surface in a set range of elements. Conditions of image formation and requirements to structures have been determined.Analytical expressions relating a deviation value of elements of a light-to-dark image with surface geometry have been obtained. This allows conducting effective quantitative control of observed topographic defects both under production and research conditions. Examples of calculation of topographic defects of semiconductor silicon wafers have been provided. Comparison of the obtained results with the data obtained by conventional methods has shown their complete conformity.

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Solodukha, V. A., G. G. Chigir, V. A. Pilipenko, V. A. Filipenya, and V. A. Gorushko. "Reliability Express Control of the Gate Dielectric of Semiconductor Devices." Devices and Methods of Measurements 9, no. 4 (December 17, 2018): 308–13. http://dx.doi.org/10.21122/2220-9506-2018-9-4-308-313.

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The key element determining stability of the semiconductor devices is a gate dielectric. As its thickness reduces in the process of scaling the combined volume of factors determining its electrophysical properties increases. The purpose of this paper is development of the control express method of the error-free running time of the gate dielectric and study the influence of the rapid thermal treatment of the initial silicon wafers and gate dielectric on its reliability.The paper proposes a model for evaluation of the reliability indicators of the gate dielectrics as per the trial results of the test MDS-structures by means of applying of the ramp-increasing voltage on the gate up to the moment of the structure breakdown at various velocities of the voltage sweep with measurement of the IV-parameters. The proposed model makes it possible to realize the express method of the reliability evaluation of the thin dielectrics right in the production process of the integrated circuits.On the basis of this method study of the influence of the rapid thermal treatment of the initial silicon wafers of the KEF 4.5, KDB 12 wafers and formed on them by means of the pyrogenic oxidation of the gate dielectric for the error-free running time were performed. It is shown, that rapid thermal treatment of the initial silicon wafers with their subsequent oxidation results in increase of the error-free running time of the gate dielectric on average from 12.9 to 15.9 years (1.23 times greater). Thermal treatment of the initial silicon wafers and gate dielectric makes it possible to expand the error-free running time up to 25.2 years, i.e.1.89 times more, than in the standard process of the pyrogenic oxidation and 1.5 times more, than under application of the rapid thermal treatment of the initial silicon wafers only.

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Couey, Jeremiah A., Eric R. Marsh, Byron R. Knapp, and R. Ryan Vallance. "In-process force monitoring for precision grinding semiconductor silicon wafers." International Journal of Manufacturing Technology and Management 7, no. 5/6 (2005): 430. http://dx.doi.org/10.1504/ijmtm.2005.007695.

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Sreejith, P. S., G. Udupa, Y. B. M. Noor, and B. K. A. Ngoi. "Recent Advances in Machining of Silicon Wafers for Semiconductor Applications." International Journal of Advanced Manufacturing Technology 17, no. 3 (January 1, 2001): 157–62. http://dx.doi.org/10.1007/s001700170185.

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Kurita, Kazunari, Takeshi Kadono, Satoshi Shigematsu, Ryo Hirose, Ryosuke Okuyama, Ayumi Onaka-Masada, Hidehiko Okuda, and Yoshihiro Koga. "Proximity Gettering Design of Hydrocarbon–Molecular–Ion–Implanted Silicon Wafers Using Dark Current Spectroscopy for CMOS Image Sensors." Sensors 19, no. 9 (May 4, 2019): 2073. http://dx.doi.org/10.3390/s19092073.

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We developed silicon epitaxial wafers with high gettering capability by using hydrocarbon–molecular–ion implantation. These wafers also have the effect of hydrogen passivation on process-induced defects and a barrier to out-diffusion of oxygen of the Czochralski silicon (CZ) substrate bulk during Complementary metal-oxide-semiconductor (CMOS) device fabrication processes. We evaluated the electrical device performance of CMOS image sensor fabricated on this type of wafer by using dark current spectroscopy. We found fewer white spot defects compared with those of intrinsic gettering (IG) silicon wafers. We believe that these hydrocarbon–molecular–ion–implanted silicon epitaxial wafers will improve the device performance of CMOS image sensors.

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Кукушкин, С. А., И. П. Калинкин, and А. В. Осипов. "Влияние химической подготовки поверхности кремния на качество и структуру эпитаксиальных пленок карбида кремния, синтезированных методом замещения атомов." Физика и техника полупроводников 52, no. 6 (2018): 656. http://dx.doi.org/10.21883/ftp.2018.06.45932.8758.

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AbstractThe fundamentals of a new technique for the cleaning and passivation of (111), (110), and (100) silicon wafer surfaces by hydride groups, which ensure a high surface purity and smoothness at the nanoscale upon long-term storage of the wafers at room temperature in air, are discussed. A new composition of the passivation solution for the long-term antioxidation protection of silicon surfaces is developed. The proposed solution is suitable for the long-term storage and repeated passivation of silicon wafers. The composition of the passivation solution and the conditions of passivation of the silicon wafers in it are described. Silicon wafers treated using the proposed technique can be used for growing epitaxial semiconductor films and different nanostructures. It is shown that only silicon surfaces prepared in this way allow SiC epitaxial films on silicon to be grown by atom substitution. The experimental dependences of the SiC and GaN film structures grown on silicon on the silicon-surface etching conditions are presented. The developed technique for silicon cleaning and passivation can both be used under laboratory conditions and easily adapted for the industrial production of silicon wafers with an oxidation-resistant surface coating.

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Haring, Fred, Syed Sajid Ahmad, Nathan Schneck, Kaycie Gerstner, Nicole Dallman, Chris Hoffarth, and Aaron Reinholz. "Spin Coating of Dielectrics on Thin Silicon To Enhance Strength Characteristics." International Symposium on Microelectronics 2010, no. 1 (January 1, 2010): 000339–43. http://dx.doi.org/10.4071/isom-2010-tp5-paper3.

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Use of very thin wafers in the semiconductor industry poses handling challenges during manufacturing. The goal of this study was to determine whether applying thin coatings could create stronger, easy to handle wafers. Standard three-point bend testing of coated and uncoated thin wafer samples was used to determine whether the coating strengthened the wafers to improve their handling properties. Data indicated that only the thinnest coating on the thinner silicon increased the peak break strength in three-point bend testing.

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Pilipenko, V. А., V. A. Saladukha, V. A. Filipenya, R. I. Vorobey, O. K. Gusev, A. L. Zharin, K. V. Pantsialeyeu, A. I. Svistun, A. K. Tyavlovsky, and K. L. Tyavlovsky. "CHARACTERIZATION OF THE ELECTROPHYSICAL PROPERTIES OF SILICON-SILICON DIOXIDE INTERFACE USING PROBE ELECTROMETRY METHODS." Devices and Methods of Measurements 8, no. 4 (December 15, 2017): 344–56. http://dx.doi.org/10.21122/2220-9506-2017-8-4-24-31.

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Introduction of submicron design standards into microelectronic industry and a decrease of the gate dielectric thickness raise the importance of the analysis of microinhomogeneities in the silicon-silicon dioxide system. However, there is very little to no information on practical implementation of probe electrometry methods, and particularly scanning Kelvin probe method, in the interoperational control of real semiconductor manufacturing process. The purpose of the study was the development of methods for nondestructive testing of semiconductor wafers based on the determination of electrophysical properties of the silicon-silicon dioxide interface and their spatial distribution over wafer’s surface using non-contact probe electrometry methods.Traditional C-V curve analysis and scanning Kelvin probe method were used to characterize silicon- silicon dioxide interface. The samples under testing were silicon wafers of KEF 4.5 and KDB 12 type (orientation <100>, diameter 100 mm).Probe electrometry results revealed uniform spatial distribution of wafer’s surface potential after its preliminary rapid thermal treatment. Silicon-silicon dioxide electric potential values were also higher after treatment than before it. This potential growth correlates with the drop in interface charge density. At the same time local changes in surface potential indicate changes in surface layer structure.Probe electrometry results qualitatively reflect changes of interface charge density in silicon-silicon dioxide structure during its technological treatment. Inhomogeneities of surface potential distribution reflect inhomogeneity of damaged layer thickness and can be used as a means for localization of interface treatment defects.

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Hockett, R. S. "Txrf Semiconductor Applications." Advances in X-ray Analysis 37 (1993): 565–75. http://dx.doi.org/10.1154/s0376030800016116.

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This is a review of Total reflection X-Ray Fluorescence (TXRF) applications for semiconductors. This review is limited to surface analysis of contamination for semiconductors and does not include chemical analysis in semiconductor processing. TXRF for surface analysis is a relatively new technology. One of the first publications occurred in 1986 using synchrotron radiation. Publications using commercially available TXRF instruments for semiconductor applications began in 1988. Today there are on the order of 100 TXRF instruments worldwide in the semiconductor industry. Since 1988 there have been about 100 publications in this field, but this number does not include numerous abstracts and publications in Japan where the majority of the commercial instruments are found today. The commercial instruments were developed for the primary application of characterizing the cleaning of planar silicon wafers, however, numerous unforeseen applications were developed by users and many of those applications are reported here. In essence TXRF has much broader application today in the semiconductor industry than supporting the cleaning of silicon wafers.

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Tang, Qing-Ju, Shuai-Shuai Gao, Yong-Jie Liu, Yun-Ze Wang, and Jing-Min Dai. "Theoretical study on infrared thermal wave imaging detection of semiconductor silicon wafers with micro-crack defects." Thermal Science 24, no. 6 Part B (2020): 4011–17. http://dx.doi.org/10.2298/tsci2006011t.

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The semiconductor silicon wafer with micro-crack defects was detected using infrared thermal wave imaging technique. The 3-D thermal conduction model in semiconductor silicon wafer excited by linear frequency modulated continuous laser was established, and it was solved by finite element method. The results show the effectiveness of the proposed method for detecting micro-crack defects in semi?conductor silicon wafers.

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Niitsu, Keiichiro, Yu Tayama, Hidenobu Maehara, Takatoshi Kato, and Ji Wang Yan. "Laser Recovery of Subsurface Damages in Chemomechanically Polished Silicon Wafers." Key Engineering Materials 701 (July 2016): 97–100. http://dx.doi.org/10.4028/www.scientific.net/kem.701.97.

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Silicon wafers are the most widely used semiconductor substrates. It has been considered that silicon wafers after chemomechanical polishing (CMP) have no subsurface defects. However, in fact, defects such as dislocation and latent microcracks will remain in the wafers if CMP is performed under unsuitable conditions. In this study, we confirmed the existence of subsurface damages at a depth of submicron level in a silicon wafer after CMP, then used a nanosecond pulsed Nd:YAG laser to repair the subsurface damages. It was found that subsurface defects were recovered to a single crystalline structure by laser irradiation without changing the surface topography. The phase transformation of silicon before and after laser irradiation was confirmed by laser Raman spectroscopy and chemical etching using saturated aqueous solution of Ca(OH)2. The findings from this study contributes to improve the quality of silicon wafers for high-performance semiconductors.

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Yurchenko, V., T. S. Navruz, M. Ciydem, and A. Altintas. "Microwave Whispering-Gallery-Mode Photoconductivity Measurement of Recombination Lifetime in Silicon." Advanced Electromagnetics 8, no. 2 (May 22, 2019): 101–7. http://dx.doi.org/10.7716/aem.v8i2.1127.

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We present a whispering-gallery-mode resonance-enhanced microwave-detected photoconductivity-decay method for contactless measurement of recombination lifetime in highresistivity semiconductor layers. We applied the method to undoped Silicon wafers of high resistivity at 5 and 30 kOhm*cm and measured the conductivity relaxation times of 10 and 14 microseconds, respectively. In wafers being considered, they are supposed to be defined by the electron-hole diffusion from the bulk to the wafer surfaces.

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Widodo, S. "Study Of Solid Planar Source For Phosphorus Diffution Process On Semiconductor Devices Fabrication." REAKTOR 6, no. 1 (June 13, 2017): 35. http://dx.doi.org/10.14710/reaktor.6.1.35-39.

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The sourcing lifetimes, microstructural staility, and diffution performance of a new solid planar phosphorus source for silicon doping were investigated in the temperature range 900-1000 0C. The source wafers were highly porous ceramic wafers containing 25 weight percentage (w/o) SiP2O7 as the “active” component in an inert refractory binder matrix. The microstructural stability and thermografimetric analysis (TGA) result indicated the structural integrity and sourcing ability of this materials at temperatures of at least 1050 0C. Theoretical lifetimesof 260 and 3400 hr at 1000 and 900 0C, respectively, have been predicted from the TGA results. Experimental data relating sheet resistance, junction depth, and diffution coefficient for silicon wafers doped using these source wafers are presented. Special material handling procedure are also described. Keywords : diffution process, solid phosphorus source, SiP2O5, semiconductor devices

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Xin, X. J., Z. J. Pei, and Wenjie Liu. "Finite Element Analysis on Soft-Pad Grinding of Wire-Sawn Silicon Wafers." Journal of Electronic Packaging 126, no. 2 (June 1, 2004): 177–85. http://dx.doi.org/10.1115/1.1649243.

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Silicon is the primary semiconductor material used to fabricate microchips. The quality of microchips depends directly on the quality of starting silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Surface grinding is one of the processes used to flatten the wire-sawn wafers. A major issue in grinding of wire-sawn wafers is the reduction and elimination of wire-sawing induced waviness. Several approaches (namely, combination of grinding and lapping, reduced chuck vacuum, soft-pad, and wax mounting) have been proposed to address this issue. Finite element analysis modeling of these approaches was conducted and the results were published earlier. It was shown that soft-pad grinding was a very promising approach since it was very effective in reducing the waviness and very easily adopted to conventional grinding environment. This paper presents a study of finite element analysis on soft-pad grinding of wire-sawn silicon wafers, covering the mechanisms of waviness reduction and the effects of pad material properties.

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Pramanik, Alokesh, Mei Liu, and Liang Chi Zhang. "Production, Characterization and Application of Silicon-on-Sapphire Wafers." Key Engineering Materials 443 (June 2010): 567–72. http://dx.doi.org/10.4028/www.scientific.net/kem.443.567.

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Silicon-on-sapphire (SOS) thin film systems have had specific electronic applications because they can reduce noise and current leakage in metal oxide semiconductor transistors. However, there are some issues in producing defect-free SOS wafers. Dislocations, misfit, micro twins and residual stresses can emerge during the SOS processing and they will reduce the performance of an SOS product. For some reasons, research publications on SOS in the literature are not extensive, and as a result, the information available in the public domain is fragmentary. This paper aims to review the subject matter in an as complete as possible manner based on the published information about the production, characterization and application of SOS wafers.

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Awang, Zaiki, Deepak Kumar Ghodgaonkar, and Noor Hasimah Baba. "Free Space Microwave Characterization of Silicon Wafers for Microelectronic Applications." Scientific Research Journal 2, no. 2 (December 31, 2005): 35. http://dx.doi.org/10.24191/srj.v2i2.9331.

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A contactless and non-destructive microwave method has been developed to characterize silicon semiconductor wafers from reflection and transmission measurements made at normal incidence using MNDT. The measurement system consists of a pair of spot-focusing horn lens antenna, mode transitions, coaxial cables and a vector network analyzer (VNA). In this method, the free-space reflection and transmission coefficients, S11 and S21 are measured for silicon wafers sandwiched between two Teflon plates of 5mm thickness which act as a quarter-wave transformer at mid-band. The actual reflection and transmission coefficients, S11 and S21 of the silicon wafers are then calculated from the measured S11 and S21 using ABCD matrix transformation in which the complex permittivity and thickness of the Teflon plates are known. From the complex permittivity, the resistivity and conductivity can be obtained. Results for p-type and n-type doped silicon wafers are reported in the frequency range of 11 – 12.5 GHz. The dielectric constant of silicon wafer obtained by this method agrees well with that measured in the same frequency range by other conventional methods.

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Kang, Ren Ke, Yan Fen Zeng, Shang Gao, Zhi Gang Dong, and Dong Ming Guo. "Surface Layer Damage of Silicon Wafers Sliced by Wire Saw Process." Advanced Materials Research 797 (September 2013): 685–90. http://dx.doi.org/10.4028/www.scientific.net/amr.797.685.

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Wire saw process is widely used in the machining of hard and brittle materials with low surface damage and high efficiency. Cutting of silicon wafers in integrated circuit (IC), semiconductor and photovoltaic solar industries is also generally using wire saw process. However, the surface layer damage induced by wire saw process will seriously decrease the wafer quality and increase the process time and production costs of the post grinding and polishing. The surface layer qualities of the silicon wafers sawed by the different wire saw processes was investigated in this paper. The characteristics of surface roughness, surface topography and subsurface damage of silicon wafers sliced by the fixed abrasive and the loose abrasive wire sawing respectively were compared and the corresponding reasons were analyzed.

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Hidai, Hirofumi, Taro Sugita, and Hitoshi Tokura. "Blasting of Affected Layer of Silicon Surface Sliced by Wire EDM." Advanced Materials Research 76-78 (June 2009): 440–44. http://dx.doi.org/10.4028/www.scientific.net/amr.76-78.440.

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Polycrystalline ingot slicing by wire electric discharge machining (W-EDM) has been investigated to reduce kerf loss and wafer thickness. In order to use the sliced wafers for semiconductor devices, the modified surface layer induced by W-EDM must be removed. In this paper, we have demonstrated the elimination of the layer by abrasive blasting. Three types of abrasives were blasted at a speed of 100 m/s. The surfaces blasted with WA #1000 and GC #1000 were smoother than that sliced with a wire saw. The modified layer induced by W-EDM slicing could be removed by blasting with WA #1000 while scanning the surface three times. Solar cells were fabricated using wafers with the blasted surface with an efficiency of 15.2%, which was almost the same as that of cells fabricated from the wire-sliced wafers.

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P.Y., Leonov, Kotelyanets O.S., and Ivanov N.V. "Import Substitution Production of Semiconductor Silicon in Russia as a Tool to Reduce the risk of Money Laundering." KnE Social Sciences 3, no. 2 (February 15, 2018): 221. http://dx.doi.org/10.18502/kss.v3i2.1546.

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The work is devoted to studying the need of creation a domestic production of polycrystalline, monocrystalline silicon and silicon wafers for the purposes of electronics and solar energy in the Russian Federation, as a part of the solution of a number of strategic objectives. In addition, the work discusses the question of import substitution as a means of combating money-laundering. Keywords: semiconductor silicon, polycrystalline silicon, monocrystalline silicon, import substitution, money laundering

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Gaman, V. I., G. F. Karlova, and E. G. Shumskaya. "Helical instability of a semiconductor plasma in silicon wafers at 77 K." Soviet Physics Journal 34, no. 8 (August 1991): 693–98. http://dx.doi.org/10.1007/bf01103497.

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Saedon, Juri B., Siti Musalmah Md Ibrahim, Amir Radzi Abd Ghani, and Muhammad Hafizi Bin Abd Razak. "Dicing Characterization on Optical Silicon Wafer Waveguide." Applied Mechanics and Materials 899 (June 2020): 163–68. http://dx.doi.org/10.4028/www.scientific.net/amm.899.163.

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Silicon wafers are a key component in integrated circuits which comprised of various electronic components that are arranged to perform a specific function. Wafer dicing is a mechanical process of removing material from a wafer by synthetic diamonds as abrasive particles. Chipping along the cut line crucial to the wafer dicing operation has been identified by semiconductor manufacturers as a relevant area for improvement. The purposed of this study is to characterize the effect of dicing operation on the optical silicon wafer coating material. The effect of the blade wear and silicon wafer kerf width will be analyzed in this work

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Hooper, Andy, and Daragh Finn. "Analysis of Silicon Micromachining by UV Lasers, and Implications for Full Cut Laser Dicing of Ultra-Thin Semiconductor Device Wafers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 001743–59. http://dx.doi.org/10.4071/2010dpc-wp16.

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3D packaging technologies such as FLASH rely on die-to-die stacking of ultra-thin silicon devices with individual die thicknesses below 100 um. Because ultra-thin silicon wafers are very fragile, mechanical saw dicing of sub 100 um thick wafers tends to be more challenging, requiring slower processing and reduced throughput and/or yields. These challenges make full cut laser dicing an attractive solution. This presentation provides an investigation for machining of 50 um thick silicon wafers using a Gaussian-shaped, nanosecond pulsewidth, 355 nm UV laser. A range of machining speeds and laser fluences are compared, from single laser pulses to highly overlapped slow-velocity machining. 3D Laser Scanning Microscope and FIB/TEM cross sections are employed to characterize the state and depth of heating damage into the Si material. Implications for laser machining rates and die break strength are investigated for full cut laser dicing.

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Strandjord, Andrew, Thorsten Teutsch, Axel Scheffler, Bernd Otto, Anna Paat, Oscar Alinabon, and Jing Li. "Wafer Level Packaging of Compound Semiconductors." Journal of Microelectronics and Electronic Packaging 7, no. 3 (July 1, 2010): 152–59. http://dx.doi.org/10.4071/imaps.263.

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The microelectronics industry has implemented a number of different wafer level packaging (WLP) technologies for high volume manufacturing, including: UBM deposition, solder bumping, wafer thinning, and dicing. These technologies were successfully developed and implemented at a number of contract manufacturing companies, and then licensed to many of the semiconductor manufacturers and foundries. The largest production volumes for these technologies are for silicon-based semiconductors. Continuous improvements and modifications to these WLP processes have made them compatible with the changes observed over the years in silicon semiconductor technologies. These industry changes include: the move from aluminum to copper interconnect metallurgy, increases in wafer size, decreases in pad pitch, and the use of Low-K dielectrics. In contrast, the direct transfer of these WLP technologies to compound semiconductor devices, like GaAs, SiC, InP, GaN, and sapphire; has been limited due to a number of technical compatibility issues, several perceived compatibility issues, and some business concerns From a technical standpoint, many compound semiconductor devices contain fragile air bridges, gold bond pads, topographical cavities and trenches, and have a number of unique bulk material properties which are sensitive to the mechanical and chemical processes associated with the standard WLP operations used for silicon wafers. In addition, most of the newer contract manufacturing companies and foundries have implemented mostly 200 and 300 mm wafer capabilities into their facilities. This limits the number of places that one can outsource the processing of 100 and 150 mm compound semiconductor wafers. Companies that are processing large numbers of silicon based semiconductor wafers at their facilities are reluctant to process many of these compound semiconductors because there is a perceived risk of cross contamination between the different wafer materials. Companies are not willing to risk their current business of processing silicon wafers by introducing these new materials into existing process flows. From a business perspective, many companies are reluctant to take the liability risks associated with some of the very high-value compound semiconductors. In addition, the volumes for many of the compound semiconductor devices are very small compared with silicon based devices, thus making it hard to justify interruption in the silicon wafer flows to accommodate these lower volume products. In spite of these issues and perceptions, the markets for compound semiconductors are expanding. Several high profile examples include the increasing number of frequency and power management devices going into cell phones, light emitting diodes, and solar cells The strategy for the work described in this paper is to protect all structures and surfaces with either a spin-on resist or a laminated film during each step in the process flow. These layers will protect the wafer from mechanical and chemical damage, and at the same time protect the fab from contamination by the compound semiconductor.

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Choi, Seong Jae, Dong Kee Yi, Jae-Young Choi, Jong-Bong Park, In-Yong Song, Eunjoo Jang, Joo In Lee, et al. "Spatial Control of Quantum Sized Nanocrystal Arrays onto Silicon Wafers." Journal of Nanoscience and Nanotechnology 7, no. 12 (December 1, 2007): 4285–93. http://dx.doi.org/10.1166/jnn.2007.884.

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Monolayer arrays of monodispersed nanocrystals (<10 nm) onto three dimensional (3D) substrates have considerable potential for various engineering applications such as highly integrated memory devices, solar cells, biosensors and photo and electro luminescent displays because of their highly integrated features with nanocrystal homogeneity. However, most reports on nanocrystal arrays have focused on two dimensional (2D) flat substrates, and the production of wafer-scale monolayer arrays is still challenging. Here we address the feasibility of arraying nanocrystal monolayers in wafer-scale onto 3D substrates. We present both metal (Pd) and semiconductor (CdSe) nanocrystals arrayed in monolayer onto trenched silicon wafers (4 inch diameter) using a facile electrostatic adsorption scheme. In particular, CdSe nanocrystal arrays in the trench well showed superior luminescent efficiency compared to those onto the protruded trench flat, due to the densely arrayed CdSe nanocrystals in the vertical direction. Furthermore, the surface coverage controllability was investigated using a 2D silicon substrate. Our approach can be applied to generate highly efficient displays, memory chips and integrated sensing devices.

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González-Fernández, Alfredo A., Mariano Aceves-Mijares, Oscar Pérez-Díaz, Joaquin Hernández-Betanzos, and Carlos Domínguez. "Embedded Silicon Nanoparticles as Enabler of a Novel CMOS-Compatible Fully Integrated Silicon Photonics Platform." Crystals 11, no. 6 (May 31, 2021): 630. http://dx.doi.org/10.3390/cryst11060630.

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The historical bottleneck for truly high scale integrated photonics is the light emitter. The lack of monolithically integrable light sources increases costs and reduces scalability. Quantum phenomena found in embedded Si particles in the nanometer scale is a way of overcoming the limitations for bulk Si to emit light. Integrable light sources based in Si nanoparticles can be obtained by different CMOS (Complementary Metal Oxide Semiconductor) -compatible materials and techniques. Such materials in combination with Si3N4 photonic elements allow for integrated Si photonics, in which photodetectors can also be included directly in standard Si wafers, taking advantage of the emission in the visible range by the embedded Si nanocrystals/nanoparticles. We present the advances and perspectives on seamless monolithic integration of CMOS-compatible visible light emitters, photonic elements, and photodetectors, which are shown to be viable and promising well within the technological limits imposed by standard fabrication methods.

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Kusuyama, Jumpei, Shintaro Iwahashi, Takayuki Kitajima, Nagahisa Ogasawara, Akinori Yui, Hirotsugu Saito, and Alexander H. Slocum. "Loop Stiffness of Grinding Machine Developed for 450 mm Silicon Wafers." Advanced Materials Research 1136 (January 2016): 655–60. http://dx.doi.org/10.4028/www.scientific.net/amr.1136.655.

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Increasing the wafer diameter from φ300 mm to φ450 mm is required to enhance semiconductor devices productivity. A high-stiffness rotary grinding machine equipped with water hydrostatic bearings was developed for a φ450 mm silicon wafer. The grinding machine has an upper structure consisting of a wheel spindle system and a lower structure consisting of a rotary worktable system. The spindle shaft creates both rotary and axial feeding motion. The upper and lower structures are clamped together rigidly by three kinematic couplings. A higher loop stiffness is required for the grinding machine because grinding the larger wafer requires a higher grinding force. This paper investigates the loop stiffness of the developed wafer grinding machine.

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Bai, Jin Rui, and Rui Xiang Hou. "The Study of Surface Morphology and Roughness of Silicon Wafers Treated by Plasma." Materials Science Forum 980 (March 2020): 88–96. http://dx.doi.org/10.4028/www.scientific.net/msf.980.88.

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Plasma is generally used for the doping of semiconductors. During plasma doping process, plasma interacts with the surface of semiconductor. As a result, defects are induced in the surface region. In this work, the surface morphology and roughness of silicon wafer caused by plasma treatment is studied by use of atom force microscope (AFM). It is found that, during the plasma process, each of the processing time of plasma, location of silicon wafer in plasma and the way of placement of silicon wafer has an influence on the surface morphology and roughness and the reason is discussed. The interaction between plasma and the surface of silicon wafer is qualitatively discussed.

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31

Robson, Mark, Kristin A. Fletcher, Ping Jiang, Michael B. Korzenski, A. Upham, T. Haigh Jr., and Thomas J. C. Hsieh. "Advances in Test Wafer Reclaim Technology – Wet Stripping Porous Low-k Films with No Substrate Damage." Solid State Phenomena 145-146 (January 2009): 339–42. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.339.

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In semiconductor processing, test wafers are used as particle monitors, film thickness monitors for deposition and oxide growth measurements, dry/wet etch rate monitors, CMP monitors, as well as characterizing new and existing equipment and processes. Depending on fab size and capacity, monthly test wafer usage can be tens of thousands or more. Due to the ever increasing demand for silicon between the IC and solar markets and the high cost of 300mm wafers, chip manufacturers are increasing their efforts to reduce overall spending on silicon - currently by far the largest non equipment related cost [1]. One approach taken by many chip makers is the concept of extending the usable life of test wafers by re-using them as many times as possible through a reclaim process.

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32

Kohno, H., T. Arai, Y. Araki, and R. Wilson. "High Accuracy Analysis of BPSG Thin Films on Silicon Wafers by X-Ray Wafer Analyzer." Advances in X-ray Analysis 37 (1993): 229–34. http://dx.doi.org/10.1154/s0376030800015731.

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The wafer analyzer has been used to fulfil many applications needs in the semiconductor industry. The prominent features of the XRF method for the semiconductor industry are:analysis of many types of films, e.g., oxides, silicides and metallic alloys, and simultaneous analysis of film thickness and compositions.In the past, the analysis results of BPSG (Boron-doped Phospho-Silicate Glass) films, with thicknesses greater than 4000 Å, were reported. With the recent increased demand for larger scale and higher quality semiconductor devices (larger than 64 Mbit), more accurate analysis with high precision has been required.

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Sun, Yalong, Di Wu, Kai Liu, and Fengang Zheng. "Colossal Permittivity and Low Dielectric Loss of Thermal Oxidation Single-Crystalline Si Wafers." Materials 12, no. 7 (April 3, 2019): 1102. http://dx.doi.org/10.3390/ma12071102.

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In this work, thin SiO2 insulating layers were generated on the top and bottom surfaces of single-crystalline silicon plates (n type) by thermal oxidation to obtain an insulator/semiconductor/insulator (ISI) multilayer structure. X-ray diffraction (XRD) pattern and scanning electron microscope (SEM) pictures implied that all of the synthesized SiO2 layers were amorphous. By controlling the thermal oxidation times, we obtained SiO2 layers with various thicknesses. The dielectric properties of silicon plates with different thicknesses of SiO2 layers (different thermal oxidation times) were measured. The dielectric properties of all of the single-crystalline silicon plates improved greatly after thermal oxidation. The dielectric constant of the silicon plates with SiO2 layers was approximately 104, which was approximately three orders more than that of the intrinsic single-crystalline silicon plate (11.9). Furthermore, both high permittivity and low dielectric loss (0.02) were simultaneously achieved in the single-crystalline silicon plates after thermal oxidation (ISI structure).

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Sun, Yu Li, Dun Wen Zuo, W. Z. Lu, Y. W. Zhu, and J. Li. "Temperature Distribution of IFA Polishing Single Silicon Wafer." Advanced Materials Research 135 (October 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amr.135.73.

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The ice fixed abrasives (IFA) polishing is a potential polishing process in the semiconductor industry to realize superior surface finish and planarity for semiconductor wafers. The key question in IFA polishing is how to keep suitable ambient temperature and melting rate in production process in order to avoid premature failure of the IFA pad. In this paper, effects of ambient temperature (T), pressure in cylinder (Pc), rotary speed of IFA pad (v) and eccentricity of pressure head (e) on temperature distribution and melting rate of the IFA pad are researched. The results show that T should be kept at about 10 °C in order to control the melting rate of the IFA pad effectively and keep longer polishing time. And suitable Pc, e can be kept at 0.075 MPa or 0.1 MPa and 20 mm or 30 mm, respectively. In order to increase IFA polishing efficiency, the rotary speed of IFA pad can be increased appropriately. All the results provide the basis for choosing suitable processing parameters in IFA polishing.

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Deng, Qian Fa, Tao Kong, Gan Li, and Ju Long Yuan. "Study on Polishing Technology of GaAs Wafer." Advanced Materials Research 497 (April 2012): 200–204. http://dx.doi.org/10.4028/www.scientific.net/amr.497.200.

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GaAs are one of the most important semiconductor followed silicon, GaAs wafers are the mostly used substrates for fabricating integrated circuits (ICs). So the quality of ICs depends directly on the quality of GaAs wafers. A series of processes are required to manufacture high quality GaAs wafers. This paper reviews the literature on polishing technology of GaAs wafers, covering the history, summarizes the effects of slurry’s chemical and physical characters such as pH, oxidants, abrasive grit, velocity, and temperature in the polishing process. It also discusses some possible topics for future research.

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Nomura, Sigeaki, Kazuo Nishihagi, and Kazuo Tauiguchi. "Impurity Analysis of Silicon Wafers by Total Reflection X-ray Fluorescence Analysis." Advances in X-ray Analysis 32 (1988): 205–10. http://dx.doi.org/10.1154/s0376030800020486.

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High purity of silicon wafers is demanded by the high performance and highly integrated IC and LSI semiconductors. Impurities on, or in, the silicon wafer have a big influence on the characteristics of the semiconductor as a final product. Usually, these impurities are introduced by water during washing, by bad handling, or by reagents and processes.Typical influences of these impurities are shown in Table 1. These elements are present at too small concentration to he detected by ordinary analytical methods (except for oxygen). Usually, XPS , AES, NAA, SIMS, ICPAES, ICP-MS and AAS are used for trace analysis.

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Obayashi, Yuma, Urara Satake, and Toshiyuki Enomoto. "New Evaluation Method of Polishing Pad Property for Estimating Edge Roll-Off of Silicon Wafer." Materials Science Forum 874 (October 2016): 34–39. http://dx.doi.org/10.4028/www.scientific.net/msf.874.34.

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With the ever-growing demand for further increase in the integration density of semiconductor devices, silicon wafers as the substrates for most devices are required to be extremely flat. In particular, it is strongly required to suppress edge roll-off, which seriously deteriorates the surface flatness near the wafer edge during polishing process in the final stage of the wafer manufacturing. In this study, we investigate the properties of polishing pads required for decreasing edge roll-off and propose the evaluation method of the properties. Polishing experiments with silicon wafers and evaluation tests for polishing pads reveal that the proposed method can estimate the obtained edge surface flatness.

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Godignon, Phillippe, Iñigo Martin, Gemma Gabriel, Rodrigo Gomez, Marcel Placidi, and Rosa Villa. "New Generation of SiC Based Biodevices Implemented on 4” Wafers." Materials Science Forum 645-648 (April 2010): 1097–100. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1097.

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Silicon Carbide is mainly used for power semiconductor devices fabrication. However, SiC material also offers attractive properties for other types of applications, such as high temperature sensors and biomedical devices. Micro-electrodes arrays are one of the leading biosensor applications. Semi-insulating SiC can be used to implement these devices, offering higher performances than Silicon. In addition, it can be combined with Carbon Nanotubes growth technology to improve the devices sensing performances. Other biosensors were SiC could be used are microfluidic based devices. However, improvement of SiCOI starting material is necessary to fulfill the typical requirements of such applications.

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Peterson, G. P., A. B. Duncan, and M. H. Weichold. "Experimental Investigation of Micro Heat Pipes Fabricated in Silicon Wafers." Journal of Heat Transfer 115, no. 3 (August 1, 1993): 751–56. http://dx.doi.org/10.1115/1.2910747.

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An experimental investigation was conducted to determine the thermal behavior of arrays of micro heat pipes fabricated in silicon wafers. Two types of micro heat pipe arrays were evaluated, one that utilized machined rectangular channels 45 μm wide and 80 μm deep and the other that used an anisotropic etching process to produce triangular channels 120 μm wide and 80 μm deep. Once fabricated, a clear pyrex cover plate was bonded to the top surface of each wafer using an ultraviolet bonding technique to form the micro heat pipe array. These micro heat pipe arrays were then evacuated and charged with a predetermined amount of methanol. Using an infrared thermal imaging unit, the temperature gradients and maximum localized temperatures were measured and an effective thermal conductivity was computed. The experimental results were compared with those obtained for a plain silicon wafer and indicated that incorporating an array of micro heat pipes as an integral part of semiconductor devices could significantly increase the effective thermal conductivity; decrease the temperature gradients occurring across the wafer; decrease the maximum wafer temperatures; and reduce the number and intensity of localized hot spots. At an input power of 4 W, reductions in the maximum chip temperature of 14.1°C and 24.9°C and increases in the effective thermal conductivity of 31 and 81 percent were measured for the machined rectangular and etched triangular heat pipe arrays, respectively. In addition to reducing the maximum wafer temperature and increasing the effective thermal conductivity, the incorporation of the micro heat pipe arrays was found to improve the transient thermal response of the silicon test wafers significantly.

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40

Steinegger, Thomas, M. Naumann, and F. G. Kirscht. "Laser Scattering Tomography on Magnetic CZ-Si for Semiconductor Process Optimization." Solid State Phenomena 108-109 (December 2005): 597–602. http://dx.doi.org/10.4028/www.scientific.net/ssp.108-109.597.

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Laser scattering tomography (LST) and band-to-band photoluminescence (PL) are applied for supporting a MEMS process optimization. Process wafers are based on magnetic CZ grown silicon material. LST allows the characterization of number-size distributions of oxygen precipitates in various stages of the process flow. Precipitation is shown to be affected by the design of high-temperature anneal post initial oxidation. PL gives useful information on relative concentration level and radial distribution of recombination centers within process wafers. The initial oxidation leads to significant reduction of recombination centers. The combined LST/PL information enables valuable conclusions towards process optimization.

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41

Lu, Yongqiang, Sian Collins, Laura B. Mauer, John Taddei, and John Clark. "Highly Selective Wet Silicon Etch Chemistry and Process for Advanced Semiconductor Packaging." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000463–68. http://dx.doi.org/10.4071/isom-2016-tha41.

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Abstract A wet silicon etch chemistry and a process using the chemistry as a simple and cost-effective alternative to the polish/plasma etch silicon thinning process are presented in this paper. The new etch chemistry improves the Si etch rate over traditional etchants such as tetramethylammonium hydroxide (TMAH). The chemistry has very high silicon etch selectivity (ratio of Si etch rate to another film etch rate) over SiO2 and over copper films, with etch selectivity greater than 8000:1 and 2500:1 respectively. Chemical compatibility with typical packaging materials such as polybenzoxazole (PBO) and polyimide (PI) are also discussed. Additionally, real production TSV wafers have been successfully processed on an advanced single wafer etch tool using the chemistry. High uniformity and smooth surface finishing have been achieved.

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42

Darchuk, S. D., and F. F. Sizov. "Semiconductor IR laser spectroscopy in application to oxygen concentration distribution determination in silicon wafers." Infrared Physics & Technology 39, no. 2 (March 1998): 77–81. http://dx.doi.org/10.1016/s1350-4495(97)00042-x.

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Park, Jin-Goo, and Srini Raghavan. "Dynamic wetting behavior of silicon wafers in alkaline solutions of interest to semiconductor processing." Journal of Adhesion Science and Technology 7, no. 3 (January 1993): 179–93. http://dx.doi.org/10.1163/156856193x00646.

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44

Williams, Stephen, Sorin Cristoloveanu, and George Campisi. "Point contact pseudo-metal/oxide/semiconductor transistor in as-grown silicon on insulator wafers." Materials Science and Engineering: B 12, no. 1-2 (January 1992): 191–94. http://dx.doi.org/10.1016/0921-5107(92)90284-g.

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45

Sih, Vincent, Berthold Reimer, Anthony S. Ratkovich, Jeffrey M. Lauerhaas, and Jeffery W. Butterbaugh. "Selective Nitride Etching with Phosphoric and Sulfuric Acid Mixtures Using a Single-Wafer Wet Processor." Solid State Phenomena 219 (September 2014): 93–96. http://dx.doi.org/10.4028/www.scientific.net/ssp.219.93.

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Selective nitride etching in semiconductor manufacturing is currently performed in wet benches using hot orthophosphoric acid at 160-180C. This process requires silica seasoning to achieve the desired selectivity to silicon oxide. Silica seasoning in wet benches is achieved by etching blanket silicon nitride wafers prior to running productions runs. While, this method of selective silicon nitride etching has been successful in the past, particle requirements at advanced nodes [1] are driving the need for a new solution. Single wafer wet processing is proposed as a way to meet these challenging new particle specifications.

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46

Barcz, Adam. "Silicon Dioxide as a Boundary for Oxygen Outdiffusion from CZ-Si." Defect and Diffusion Forum 297-301 (April 2010): 688–93. http://dx.doi.org/10.4028/www.scientific.net/ddf.297-301.688.

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Oxygen out-diffusion from CZ-Si or in-diffusion into FZ Si was studied with Secondary Ion Mass Spectrometry. For anneals up to 1200oC , the value of 16O concentration Csurf that develops at the semiconductor surface in bare wafers with ~2 nm thick natural oxide was found to be comparable to that in thermally oxidized wafers with 260 nm thick SiO2. Beyond this temperature, at 1280oC, Csurf in non-oxidised sample appears 5 times lower that in the oxidised one. This means that the spontaneous oxide becomes permeable to the oxygen species and no longer constitutes a barrier preventing the oxygen atoms from direct out-diffusion into the ambient. The effect becomes more pronounced when the specimens were heated to 1150oC in a chamber evacuated to ~ 10-7 Torr. The resultant bare Cz-Si and, to even greater extent, FZ Si with previously in-diffused oxygen exhibited deep oxygen depletion, 10x below the respective values for annealing under atmospheric pressure. Undoubtedly, it is the removal of residual oxides by sublimation that enables oxygen atoms to freely out-diffuse into vacuum.

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TIMOSHENKO, VICTOR YU, KYRILL A. GONCHAR, NATALIA E. MASLOVA, YERZHAN T. TAURBAYEV, and TOKHTAR I. TAURBAYEV. "ELECTROCHEMICAL NANOSTRUCTURING OF SEMICONDUCTOR WAFERS BY CAPILLARY-FORCE-ASSISTED METHOD." International Journal of Nanoscience 09, no. 03 (June 2010): 139–43. http://dx.doi.org/10.1142/s0219581x10006697.

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Wafers of crystalline silicon (c-Si) and compound semiconductors (GaP, GaAs) were nanostructured by using the electrochemical etching in specially designed cells with two or more electrodes spaced at 100–500 μm distances, which allowed keeping the electrolyte due to capillary forces. Investigations by means of atomic force microscopy and optical spectroscopy revealed nanoporous and nanocrystalline structure of the prepared samples. The employed capillary-force-assisted method is promising for preparation of thin layers of nanostructured semiconductors with desired optical properties having advantages of cost saving, quickness and flexibility in the electrical contact arrangements versus conventional electrochemical etching methods.

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48

Morris, J. C., and D. L. Callahan. "Origins of microplasticity in low-load scratching of silicon." Journal of Materials Research 9, no. 11 (November 1994): 2907–13. http://dx.doi.org/10.1557/jmr.1994.2907.

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Microstructural characterization of silicon wafers subjected to controlled low-load scratching with a sharp indenter reveals that considerable plastic deformation occurs prior to the onset of fracture. In particular, a completely ductile response to scratching is observed at or below a Vickers load of 1 g, corresponding to penetration depths of 200 nm or less. This anomalous plasticity arises primarily as a result of a pressure-induced semiconductor-to-metal phase transition (Mott transition). Various levels of subsurface dislocation activity and cracking also contribute to the deformation. The relationships among the phase transformation, dislocation activity, and the onset of fracture are discussed. These findings can be applied to other areas of contact damage demonstrating anomalous plasticity, such as hardness testing and ductile-regime turning.

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Nonaka, Tatsuo, Kikuo Takeda, Reiko Iikawa, Toshikazu Taira, Taketoshi Fujimoto, and Taketoshi Nakahara. "Evaluation of Chemical Filters Using Wafer Exposure Method and Experimental FFU." Journal of the IEST 46, no. 1 (September 14, 2003): 55–58. http://dx.doi.org/10.17764/jiet.46.1.y2510660g86310j3.

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Airborne molecular contaminants (AMCs) have become a serious problem with recent advances in semiconductor manufacturing technology. The use of chemical filters to remove AMCs in cleanrooms is critical for improving the yield of semiconductor devices. The experimental FFU is designed for the evaluation of chemical filters. Silicon wafers exposed in the downstream air of chemical filters in the experimental FFU were investigated by Wafer Thermal Desorption—Gas Chromatography-Mass Spectrometry (WTD-GC-MS). Organic contaminants caused by outgassing from the chemical filter were detected on the surface of the silicon wafer and compared among various chemical filters. Results showed that the volatile organic compounds (VOCs) emitted from chemical filters adsorbed on the surface of silicon wafers located downstream of the filters. It was also found that the organic contamination on the surface was related to the amount of outgassing from the chemical filters. In addition, the rates of decrease of organic contamination emitted from various ULPA filters were compared using the experimental FFU. The rate of decrease of organic contamination emitted from the low-outgassing ULPA filter was also superior to that of the normal ULPA filter.

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Shankar, N. G., Z. W. Zhong, and N. Ravi. "Classification of Defects on Semiconductor Wafers Using Priority Rules." Defect and Diffusion Forum 230-232 (November 2004): 135–48. http://dx.doi.org/10.4028/www.scientific.net/ddf.230-232.135.

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This paper presents a template-based vision system to detect and classify the nonuniformaties that appear on the semiconductor wafer surfaces. Design goals include detection of flaws and correlation of defect features based on semiconductor industry expert’s knowledge. The die pattern is generated and kept as the reference beforehand from the experts in the semiconductor industry. The system is capable of identifying the defects on the wafers after die sawing. Each unique defect structure is defined as an object. Objects are grouped into user-defined categories such as chipping, metallization peel off, silicon dust contamination, etc., after die sawing and micro-crack, scratch, ink dot being washed off, bridging, etc., from the wafer. This paper also describes the vision system in terms of its hardware modules, as well as the image processing algorithms utilized to perform the functions.

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Journal articles on the topic 'Semiconductor wafers. Silicon Silicon Electrodiffusion'

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