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Journal articles on the topic 'Semiconductors; IC manufacture'

Author: Grafiati

Published: 4 June 2021

Last updated: 3 February 2022

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1

Zhang, Yuqian. "The Application of Third Generation Semiconductor in Power Industry." E3S Web of Conferences 198 (2020): 04011. http://dx.doi.org/10.1051/e3sconf/202019804011.

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With the rapid development of technologies, the third generation semiconductor is being studied, as it is leading to the significant change in industry like the manufacture of PC, mobile devices, lighting etc. Till now, due to its irreplaceable physical characteristics, third generation semiconductor is applied to lots of fields. This paper analyzes the application of third generation semiconductor, namely, GaN and SiC. Their characteristics including advantages as well as disadvantages will be discussed through reviewing the result of relevant researches. Meanwhile, comparison between the thi

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Roberts, Bob. "Technology Transfer for MEMS and Advanced Packaging: Precision Surface Preparation Innovatively Applied to Emerging Technologies." International Symposium on Microelectronics 2017, no. 1 (2017): 000231–41. http://dx.doi.org/10.4071/isom-2017-wa33_004.

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Abstract The purpose of this presentation is to examine how certain mainline silicon substrate and semiconductor wafer manufacturing processes, can be and are being applied to applications in the manufacture of some of the most advanced digital devices including advanced packaging applications. Periodically, the manufacturing steps and procedures of advanced semiconductor devices have changed dramatically enough that they are termed “paradigm shifts.” Two of the more dramatic manufacturing paradigm shifts in our professional lifetimes have been Precision Ultra-Thinning, and Chemical Mechanical

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Iwase, N., and J. Ewanich. "AIN LGAs for High Performance Packaging Applications." Microelectronics International 14, no. 3 (1997): 5–7. http://dx.doi.org/10.1108/13565369720195261.

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Because they offer many properties favourable for IC package construction, ceramics have been in widespread use as an electronic package material since the early 1960s. In recent years, with trends towards higher speed semiconductors generating up to 30‐40 watts power, packaging materials must possess excellent thermal, electrical and mechanical properties. Aluminium nitride, with a thermal conductivity of 170 W/m.K., high fracture strength and a thermal coefficient of expansion match with silicon, has been used to manufacture multilayer LGA (land grid array) packages for high performance appl

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Krylov, V. P., and A. M. Bogachev. "Deep Trapping Centers Relaxation in Transistors and Integrated Circuits." Proceedings of Universities. ELECTRONICS 25, no. 6 (2020): 568–72. http://dx.doi.org/10.24151/1561-5405-2020-25-6-568-572.

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For ensuring the efficiency of the semiconductor electronic component base for apparatus, responsible for application, an optimal combination of statistical (group) and physical-technological (individual) reliability assessments is required. In the paper a thermodynamic approach, based on the deep-level transient spectroscopy in semiconductors promising means of individual rejection of potentially unreliable electronic component base has been proposed. For transistors and integrated circuits, the dependences of the amplitude of capacitance transient, caused by the bulk and surface defects of v

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Kibarian, J. K., and A. Strojwas. "Using spatial information to analyze correlations between test structure data (semiconductor IC manufacture)." IEEE Transactions on Semiconductor Manufacturing 4, no. 3 (1991): 219–25. http://dx.doi.org/10.1109/66.85943.

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van Borkulo, Jeroen, Richard van der Stam, and Guido Knippels. "Multi Beam Full Cut Dicing of Thin Si IC Wafers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (2015): 001446–74. http://dx.doi.org/10.4071/2015dpc-wp21.

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The ongoing trend to thinner wafers which are needed for continuous miniaturization, 3D packaging and IC performance, inevitably means that sole blade dicing evolution is coming to an end. Over the last years several technologies to handle the separation process of thin Si wafer dicing have been evaluated (DBG, Stealth, Plasma, etc). Although they are capable for certain applications to meet the process specifications, they achieve this at expense of flexibility, productivity and process costs. ALSI, the inventor of multi beam dicing for semiconductor materials, has developed a technology usin

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Irmansyah, Muhammad. "PENGIMPLEMENTASIAN TEKNOLOGI PROGRAMMABLE LOGIC DEVICE (PLD) SEBAGAI BINER CODE DECIMAL (BCD) UNTUK SCANNING KEYPAD." Elektron : Jurnal Ilmiah 5, no. 1 (2018): 9–18. http://dx.doi.org/10.30630/eji.5.1.38.

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Industrial of electronics developed in many fields in the middle of 1990s. Base on this situation, the manufacturer produce the product by increased the function, display, low cost, low power consumption and small size. This kind of product must be supported by complex system, small number of integrated circuit and tiny printed circuit board (PCB). Many integrated technologies such as submicron semiconductor, PCB technology, and the using of PCB surface maximal. The market situation push the producer used modern technology in design and testing for example Programmable Logic Device (PLD). It i

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Richards, J. F., and R. J. Kline. "Applications of Scanned Probe Microscopy in the Integrated Circuit Fabrication Industry." Microscopy and Microanalysis 5, S2 (1999): 956–57. http://dx.doi.org/10.1017/s1431927600018109.

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Scanning Probe Microscopy (SPM), in particular Atomic Force Microscopy (AFM), has become well establish member of the IC metrology tool arsenal which few IC manufacturers are without. Although Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) remain the “workhorse” metrology techniques, SPM (standard AFM, as well as Scanning Capacitance Microscopy (SCM), Scanning Spreading Resistance Microscopy (SSRM), Scanning Kelvin probe, Nanoindentaion and others) are being increasingly called upon to help solve IC production problems and to aid in research and development for n

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Han, Kwonsang, Hyungseup Kim, Jaesung Kim, et al. "A 24.88 nV/√Hz Wheatstone Bridge Readout Integrated Circuit with Chopper-Stabilized Multipath Operational Amplifier." Applied Sciences 10, no. 1 (2020): 399. http://dx.doi.org/10.3390/app10010399.

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This paper proposes a low noise readout integrated circuit (IC) with a chopper-stabilized multipath operational amplifier suitable for a Wheatstone bridge sensor. The input voltage of the readout IC changes due to a change in input resistance, and is efficiently amplified using a three-operational amplifier instrumentation amplifier (IA) structure with high input impedance and adjustable gain. Furthermore, a chopper-stabilized multipath structure is applied to the operational amplifier, and a ripple reduction loop (RRL) in the low frequency path (LFP) is employed to attenuate the ripple genera

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De Souza, Rafael Navarenho, Marcilei A. Guazzelli, and Salvador P. Gimenez. "Mitigating MOSFET Radiation Effects by Using the Wave Layout in Analog ICs Applications." Journal of Integrated Circuits and Systems 10, no. 1 (2015): 30–37. http://dx.doi.org/10.29292/jics.v10i1.402.

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This paper presents an experimental comparative study of the Total Ionizing Dose (TID) effects between the Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET) manufactured with the Wave (S gate geometry) and the standard layout (CnM). Because of the special geometric characteristic of the gate, drain and source regions of the Wave MOSFET (WnM), this innovative layout proposal for transistors is able to mitigate the TID effects in order to implement in analog integrated circuits (IC) for space and medical applications without causing any additional cost to the Complementary MOS (C

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Chen, Ruei Chang, and Shih Fong Lee. "Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems." Applied Mechanics and Materials 203 (October 2012): 469–73. http://dx.doi.org/10.4028/www.scientific.net/amm.203.469.

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This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 10

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Nadaraja, Shri Kumaran, and Boon Kar Yap. "In depth study of lead frame tape residuein quad flat non-leaded package." Microelectronics International 36, no. 4 (2019): 129–36. http://dx.doi.org/10.1108/mi-12-2018-0077.

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Purpose Lead frame tape is a crucial support for lead frames in the IC assembly process. The tape residue on the quad flat non-leaded (QFN) could result in low reliability and failure in electrical conductivity tests. The tape residue would affect overall performance of the chips and contribute to low pass yield. The purpose of this paper is to present an in-depth study of tape residue and factors that may affect it. Design/methodology/approach An experiment using lead frame and tapes from three manufacturers with two types of die bond adhesives, namely, die attach film (DAF) and wafer back co

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Teng, Shiang-Yu, and Sheng-Jye Hwang. "Simulations of Process-Induced Warpage During IC Encapsulation Process." Journal of Electronic Packaging 129, no. 3 (2006): 307–15. http://dx.doi.org/10.1115/1.2753936.

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Warpage during integrated circuit encapsulation process is a serious problem. Previous researchers had focused on warpage analysis with thermal-induced shrinkage and the cure-induced shrinkage was neglected. A new approach considering both cure- and thermal-induced shrinkage during encapsulation process was presented to predict the amount of warpage. The cure-induced shrinkage was described by the pressure-volume-temperature-cure (P-V-T-C) equation of epoxy. The thermal-induced shrinkage was described by the coefficients of thermal expansion of the component materials. The thin small outline p

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Spory, Erick M. "Increased High-Temperature IC Packaging Reliability Using Die Extraction and Additive Manufacturing Assembly." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000018–22. http://dx.doi.org/10.4071/2016-hitec-18.

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Abstract Semiconductor parts are most often specified for use in the “commercial” 0 to 70°C and, to a lesser extent, in the “industrial” −40 to 85°C operating temperature range. These operating temperature ratings generally satisfy the demands of the dominant semiconductor customers in the computer, telecommunications, and consumer electronic industries. There is also a demand for parts rated beyond the “industrial” temperature range, primarily from the aerospace, military, oil and gas exploration, and automotive industries (−55 to +125C, and even higher). However, the demand has not been larg

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van Borkulo, Jeroen, Rene Hendriks, and Peter Dijkstra. "Comparison between Single & Multi Beam Laser Grooving of Low-K layers." International Symposium on Microelectronics 2012, no. 1 (2012): 000433–39. http://dx.doi.org/10.4071/isom-2012-tp53.

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The traditional blade dicing technology has gone through an impressive evolution keeping up with quality, cost and miniaturization requirements that the semiconductor technology roadmaps introduced and specified. However, since wafer technologies have dropped below 90nm node and low k materials were introduced it became clear that blade dicing evolution came to an end and expensive hybrid solutions such as combined laser grooving processes and blade dicing technologies were required to achieve the desired product reliability. Similar situations have been seen with the ongoing trend to thinner

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Sotner, Roman, Jan Jerabek, Ladislav Polak, Roman Prokop, and Vilem Kledrowetz. "Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example." Electronics 8, no. 5 (2019): 568. http://dx.doi.org/10.3390/electronics8050568.

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This paper introduces new integrated analog cells fabricated in a C035 I3T25 0.35-μm ON Semiconductor process suitable for a modular design of advanced active elements with multiple terminals and controllable features. We developed and realized five analog cells on a single integrated circuit (IC), namely a voltage differencing differential buffer, a voltage multiplier with current output in full complementary metal–oxide–semiconductor (CMOS) form, a voltage multiplier with current output with a bipolar core, a current-controlled current conveyor of the second generation with four current outp

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Fjelstad, Joseph, Thomas DiStefano, and Anthony Faraci. "Wafer level packaging of compliant, chip size ICs." Microelectronics International 17, no. 2 (2000): 23–27. http://dx.doi.org/10.1108/13565360010332426.

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The concept of packaging integrated circuits while they are still in wafer form has captured the imagination of semiconductor manufacturers and packagers around the globe. One such concept, referred to as wide area vertical expansion (WAVETM) technology promises to provide a relatively easy method for cost effectively interconnecting ICs while still on the wafer. Moreover the fundamental technology is amenable to the production of “virtual wafers” where individual IC chips can be assembled en masse. The virtual wafer variation also allows for die shrink to occur, while the IC package footprint

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Robson, Mark, Kristin A. Fletcher, Ping Jiang, et al. "Advances in Test Wafer Reclaim Technology – Wet Stripping Porous Low-k Films with No Substrate Damage." Solid State Phenomena 145-146 (January 2009): 339–42. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.339.

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In semiconductor processing, test wafers are used as particle monitors, film thickness monitors for deposition and oxide growth measurements, dry/wet etch rate monitors, CMP monitors, as well as characterizing new and existing equipment and processes. Depending on fab size and capacity, monthly test wafer usage can be tens of thousands or more. Due to the ever increasing demand for silicon between the IC and solar markets and the high cost of 300mm wafers, chip manufacturers are increasing their efforts to reduce overall spending on silicon - currently by far the largest non equipment related

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Mevellec, Vincent, Dominique Suhr, Thomas Dequivre, and Frédérique Raynal. "Electrografted insulator layer as copper diffusion barrier for TSV interposers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (2013): 001051–84. http://dx.doi.org/10.4071/2013dpc-wa14.

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Introduction After many years as a hypothetical possibility, 3D Integrated Circuits (3D IC) stacking has emerged as a potential key enabler for maintaining semiconductor performance trends. Through Silicon Vias (TSVs) sit at the foundation of the 3D-IC revolution and are a key enabler for extending semiconductor integration trends into a new phase. Integrated Device Manufacturers and fabless design houses need small, high-density, fine-pitch vias for improved signal integrity and Si real-estate savings. They need them now, and cannot wait for very thin wafer processing and handling technologie

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Gaudestad, Jan, and Antonio Orozco. "Magnetic Current Imaging of a TSV short in a 3D IC." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (2015): 001408–28. http://dx.doi.org/10.4071/2015dpc-wp14.

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In this paper we show Magnetic Field Imaging (MFI) is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a Dual Beam-Plasma FIB (DB-PFIB) system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. Magnetic Current Imaging (MCI) is a sub technique of MFI which has been used by the semiconductor industry for more than a decade t

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Amirul, Abdullah Rashid, Saad Nor Hayati, and Bulan Abdullah. "Assessment on Copper C194 Mechanical Properties Variations in Typical Semiconductor Assembly Production Line." Advanced Materials Research 576 (October 2012): 523–26. http://dx.doi.org/10.4028/www.scientific.net/amr.576.523.

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Process variation is inevitable for any production line regardless of the industry. The trend for smaller, lighter yet multifunctional devices has created high expectation for the semiconductor manufacturer to produce more robust and highly reliable devices. One way to achieve this is by assessing the variance performance of the assembly production. In this study, the mechanical properties of copper alloy C194 used as the lead frame for particular IC device have been investigated. Samples from control and defect groups been subjected to hardness (Rockwell test) and tensile (Instron test) while

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Zhang, Zhi Sheng, and Fan He. "Design of a Control System for a Turret Based Test Handler." Applied Mechanics and Materials 201-202 (October 2012): 131–34. http://dx.doi.org/10.4028/www.scientific.net/amm.201-202.131.

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Final testing procedures are performed to assure the quality of manufactured parts before their shipping to customers. Turret based test handler is a general kind of IC Test Handler for final testing. This paper discusses how to develop a general control system for a test handler of turret style in which every workstation moves up and down separately based on an industrial control computer. The combination of object-oriented programming and the cycling scanning working mode is the key of the whole system. To achieve ideal performance, special control flags are designed as an efficient way for

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Beebout, Charlie, and Erick M. Spory. "Environmentally Hardening IC Die Previously Assembled in Plastic Packages through Die Removal, Bond Pad Replating and Reassembly into Hermetic Packages." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (2018): 000039–44. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000039.

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ABSTRACT Many integrated circuits (ICs) will operate well above their maximum rated temperature of +70°C or +125°C, but are often not packaged appropriately to reliably endure temperatures above +150C. Specifically, the original gold or copper bonds on the aluminum die bond pads are prone to Kirkendall or Horsting voiding, particularly at temperatures greater than +150°C. Also the mold compounds used in plastic packaging for IC assembly can degrade at these elevated temperatures. In some cases, commercial demand for higher temperature reliability can justify a separate offering of ICs assemble

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Shin, Soowon, Yoonhee Ha, Gwangjin Choi, et al. "Manufacturable 32-Channel Cochlear Electrode Array and Preliminary Assessment of Its Feasibility for Clinical Use." Micromachines 12, no. 7 (2021): 778. http://dx.doi.org/10.3390/mi12070778.

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(1) Background: In this study, we introduce a manufacturable 32-channel cochlear electrode array. In contrast to conventional cochlear electrode arrays manufactured by manual processes that consist of electrode-wire welding, the placement of each electrode, and silicone molding over wired structures, the proposed cochlear electrode array is manufactured by semi-automated laser micro-structuring and a mass-produced layer-by-layer silicone deposition scheme similar to the semiconductor fabrication process. (2) Methods: The proposed 32-channel electrode array has 32 electrode contacts with a leng

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Lee, Minwoong, Seongik Cho, Namho Lee, and Jongyeol Kim. "New Radiation-Hardened Design of a CMOS Instrumentation Amplifier and its Tolerant Characteristic Analysis." Electronics 9, no. 3 (2020): 388. http://dx.doi.org/10.3390/electronics9030388.

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A radiation-hardened instrumentation amplifier (IA) that allows precise measurement in radiation environments, including nuclear power plants, space environments, and radiation therapy rooms, was designed and manufactured, and its characteristics were verified. Most electronic systems are currently designed using silicon-based complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) to achieve a highly integrated low-power design. However, fixed charges induced in silicon by ionization radiation cause various negative effects, resulting in, for example, the generation of leakag

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Zhu, Xiwen, Qiang Fu, Ruimo Yang, and Yufeng Zhang. "A High Power-Conversion-Efficiency Voltage Boost Converter with MPPT for Wireless Sensor Nodes." Sensors 21, no. 16 (2021): 5447. http://dx.doi.org/10.3390/s21165447.

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A high power-conversion-efficiency voltage boost converter with MPPT for wireless sensor nodes (WSNs) is proposed in this paper. Since tiny wireless sensor nodes are all over complex environments, an efficient power management system (PMS) must be equipped to achieve long-term self-power supply and maintain regular operation. It is common to use Photovoltaic cells (PV) to harvest sunlight in the environment. However, most existing interface boost integrated circuits for the PV cell have low efficiency. This paper presents a voltage boost converter (VBC) with high power conversion efficiency (P

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Wu, Hou Ya, Tie Niu Yang, and Xiao Jun Wang. "Researches of Pressure Measurement Method in Vacuum Environment." Applied Mechanics and Materials 347-350 (August 2013): 19–23. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.19.

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wafer processing is one process of the IC industry which is a booming area nowadays, the quality of the production of this course depends on the performance of the film which is formed by deposition. And one of the most important factors influencing the performance is working pressure. Variable structure chamber for flowing experiment and testing which is a multifunction testing platform with changeable structure and sufficient measurement points all-covered the chamber, a device has been designed and manufactured to measure and research vacuum flow filed. By using this equipment, the pressure

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Oosterhuis, Gerrit, Ben van der Zon, Hessel Maalderink, and Par Dunias. "Fully Additive Chip Packaging: Science or Fiction?" International Symposium on Microelectronics 2011, no. 1 (2011): 000476–83. http://dx.doi.org/10.4071/isom-2011-wa1-paper5.

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The current trend in IC packaging towards an ever increasing degree of integration, combined with a high level of production flexibility calls for novel approaches in manufacturing. To address these challenges in a flexible manufacturing setting, TNO investigated to what extend mask-less additive manufacturing (3D printing) can be applied to packaging of semiconductor components and systems. The micro-stereolithography (μSLA) process has been applied to two different cases to assess its feasibility in creating integrated chip packages and interconnects. First, 2D interconnects based on conduct

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Kiryanova, M. N., O. L. Markova, and E. V. Ivanova. "Features of formation of working conditions of workers of the main professions in the production of integrated circuits." Russian Journal of Occupational Health and Industrial Ecology, no. 8 (September 25, 2019): 508–12. http://dx.doi.org/10.31089/1026-9428-2019-59-8-508-512.

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Introduction. The modern stage of development of electronics is characterized by the widespread use of integrated circuits (IC). Assessment of working conditions in a promising, developing production of electronic components with hygienic positions is an urgent task.The aim of the study is to conduct a hygienic assessment of working conditions of workers in the main professions in the production of IC.Materials and methods. Hygienic research conducted at three modern enterprises for the production of chips and semiconductor devices, included the study of the conditions and nature of work of wo

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Takeuchi, Yoshimi. "Message from Editor-in-Chief." International Journal of Automation Technology 1, no. 1 (2007): 3. http://dx.doi.org/10.20965/ijat.2007.p0003.

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On behalf of the editorial committee of International Journal of Automation Technology, I would like to sincerely ask all of you a favour of me to activate this journal since I am convinced that the automation technology is indispensable to the convenience and prosperity of human being. The automation technology began with the development and introduction of numerical control (NC) machine tools in the latter of 1950s. In 1960s, the technology was applied to assemble electric goods and automobiles together with the development of a wide variety of automationrelated methods such as industrial ro

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Macaitis, Vytautas, and Romualdas Navickas. "Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems." Electronics 8, no. 1 (2019): 72. http://dx.doi.org/10.3390/electronics8010072.

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This paper presents the design, simulation, and measurements of a low power, low phase noise 10.25–11.78 GHz LC digitally controlled oscillator (LC DCO) with extended true single phase clock (E-TSPC) frequency divider in 130 nm complementary metal–oxide–semiconductor (CMOS) technology for 5G intelligent transport systems. The main goal of this work was to design the LC DCO using a mature and low-cost 130 nm CMOS technology. The designed integrated circuit (IC) consisted of two parts: the LC DCO frequency generation and division circuit and an independent frequency divider testing circuit. The

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Paul, Shubhra Deb, and Swarup Bhunia. "SILVerIn: Systematic Integrity Verification of Printed Circuit Board Using JTAG Infrastructure." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (2021): 1–28. http://dx.doi.org/10.1145/3460232.

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A printed circuit board (PCB) provides necessary mechanical support to an electronic system and acts as a platform for connecting electronic components. Counterfeiting and in-field tampering of PCBs have become significant security concerns in the semiconductor industry as a result of increasing untrusted entities in the supply chain. These counterfeit components may result in performance degradation, profit reduction, and reputation risk for the manufacturers. While Integrated Circuit (IC) level authentication using physical unclonable functions (PUFs) has been widely investigated, countermea

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Azémar, Jérôme. "Fan-Out Wafer-Level-Packaging: Market and Technology Trends." International Symposium on Microelectronics 2016, no. 1 (2016): 000176–79. http://dx.doi.org/10.4071/isom-2016-wa31.

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Abstract The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns

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Siegle, William T. "Interconnection Technology for Modern Logic Devices; an Exercise in System Engineering to Assure Manufacturability." MRS Proceedings 337 (1994). http://dx.doi.org/10.1557/proc-337-3.

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The history of the semiconductor IC has often been dominated by the issues associated with transistor engineering. In recent years however, it has become clear that successful mastery of advanced logic devices depends not only on transistor engineering, but also on the ability to engineer and manufacture multiple level metallization systems to form the interconnect structure of modern and dense logic ICs.

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