Journal articles: 'Sentaurus Modeling'

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Kuznetsov, Maksim, Sergey Kalinin, Alexey Cherkaev, and Dmitriy Ostertak. "Investigating physical model interface in the TCAD Sentaurus environment." Transaction of Scientific Papers of the Novosibirsk State Technical University, no. 3 (November 18, 2020): 39–48. http://dx.doi.org/10.17212/2307-6879-2020-3-39-48.

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Currently, the application SDevice software package TCAD Sentaurus is a reliable tool for electrophysical simulation of silicon CMOS transistors operating in the temperature range of -60 °C – +125 °C. To adapt the modeling process to specific physical conditions of the devices, application SDevice has an extensive library of models of electrophysical parameters, in particular models of mobility or band gap energy. However, when the device operates under extreme cryogenic conditions, there is a need to rework these models using a special Physical Model Interface (PMI). The paper presents methodological features of work with PMI and results of implementation of custom parameter models for silicon devices.

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Gulomov, Jasurbek, Rayimjon Aliev, Murad Nasirov, and Jakhongir Ziyoitdinov. "MODELING METAL NANOPARTICLES INFLUENCE TO PROPERTIES OF SILICON SOLAR CELLS." International Journal of Advanced Research 8, no. 11 (November 30, 2020): 336–45. http://dx.doi.org/10.21474/ijar01/12015.

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Nanotechnologies are entering every field. Nanoparticles have been widely used in medicine and technology. We decided to study the behavior of nanoparticles under the influence of light and its effects on solar cells, based on a number of properties. How gold and silver nanoparticles are introduced into the optical layer of the solar cell has been studied enough to affect the properties of the solar cell. However, the effect of silicon-based solar cell metal nanoparticles in the n domain on the solar cell has not been sufficiently studied. In addition, in this study, the properties of solar cells, which included nanoparticles of various shapes, were modeled. Since the end of the last century, new methods of modeling have been introduced into scientific research. A lot of modeling software has been developed. They are based on a numerical method. Synopsys program of Sentaurus TCAD software package was used in the modeling to ensure the accuracy and reliability of the research. Using Sentaurus TCAD, a model of a silicon-based solar cell with simple and various shapes of platinum nanoparticles embedded in the n field was developed. The focus is on determining the effect of the shape of a nanoparticle introduced on solar cells on its properties. The effect of nanoparticles on the optical and I-V characteristics of a solar cell is also analyzed in depth.

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Jia, Yunfang, and Cheng Ju. "Sentaurus® based modeling and simulation for GFET's characteristic for ssDNA immobilization and hybridization." Journal of Semiconductors 37, no. 1 (January 2016): 014005. http://dx.doi.org/10.1088/1674-4926/37/1/014005.

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Passeri, D., F. Moscatelli, A. Morozzi, and G. M. Bilei. "Modeling of radiation damage effects in silicon detectors at high fluences HL-LHC with Sentaurus TCAD." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 824 (July 2016): 443–45. http://dx.doi.org/10.1016/j.nima.2015.08.039.

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Jasurbek Gulomov, Rayimjon Aliev, Murodjon Abduvoxidov, Avazbek Mirzaalimov, and Navruzbek Mirzaalimov. "Exploring optical properties of solar cells by programming and modeling." Global Journal of Engineering and Technology Advances 5, no. 1 (October 30, 2020): 032–38. http://dx.doi.org/10.30574/gjeta.2020.5.1.0080.

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One of the main factors influencing the efficiency of solar cells is their optical properties. So, most light is reflecting back and transmit through solar cell. This leads to a decrease in the efficiency. We know that the refractive index of silicon is 3-4 depending on the wavelength of light, and the refractive index of air is about 1. This causes to reflect 34 percentages of the incident light. To reduce the amount of reflected light, the surface of the solar cell should be covered with an anti-reflection layer. It is important to determine the conditions of the types and thicknesses of the material covering the surface of the solar cell. Semiconductor devices modeling has become very popular. Because the results obtained through modeling are very close to the experimental results. In this study, we also modeled the solar cell with and without an anti-reflective layer using the Sentaurus TCAD software package and presented the results obtained. A new program was developed using the C # programming language, and a library was developed to help new researchers study the optical properties of solar cells directly for that program, and a number of results were obtained.

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Armand, Jimmy, Cyril Oliver, F. Martinez, B. Semmache, M. Gauthier, Alain Foucaran, and Yvan Cuminal. "Modeling of the Boron Emitter Formation Process from BCl₃ Diffusion for N-Type Silicon Solar Cells Processing." Advanced Materials Research 324 (August 2011): 261–64. http://dx.doi.org/10.4028/www.scientific.net/amr.324.261.

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This work is devoted to the study of boron doping diffusion process for n-type silicon solar cells applications. Deposition temperature is an important parameter in the diffusion process. In this paper we investigate its influence using an industrial scale furnace [1] (LYDOPTM Boron), which is developed by Semco Engineering. We especially used a numerical model (Sentaurus) in order to further understand the boron diffusion mechanism mainly with respect of the diffusion temperature. The model calibration is based on boron concentration profiles obtained by SIMS (Secondary Ion Mass Spectrometry) analysis. We observed that the boron profiles could be correctly simulated by a single fitting parameter. This parameter, noted kBoron which is connected to the chemical reaction kinetics developed at the interface between the boron silicon glass (BSG) and the silicon substrate

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Martinez-Limia, Alberto, Peter Pichler, Christian Steen, Silke Paul, and Wilfried Lerch. "Modeling of the Diffusion and Activation of Arsenic in Silicon Including Clustering and Precipitation." Solid State Phenomena 131-133 (October 2007): 277–82. http://dx.doi.org/10.4028/www.scientific.net/ssp.131-133.277.

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We have developed a diffusion and activation model for implanted arsenic in silicon. The model includes the dynamic formation of arsenic-vacancy complexes (As4V) as well as the precipitation of a SiAs phase. The latter is mandatory to correctly describe concentrations above solid solubility while the former are needed to describe the reduced electrical activity as well as the generation of self-interstitials during deactivation. In addition, the activation state after solid-phase epitaxy and the segregation at the interface to SiO2 are taken into account. After implementation using the Alagator language in the latest version of the Sentaurus Process Simulator of Synopsys, the parameters of the model were optimized using reported series of diffusion coefficients for temperatures between 700 °C and 1200 °C, and using several SIMS profiles covering annealing processes from spike to very long times with temperatures between 700 °C and 1050 °C and a wide distribution of implantation energies and doses. The model was validated using data from flash-assisted RTP and spike annealing of ultra-low energy arsenic implants.

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Sahoo, Sasmita, Sidhartha Dash, and Guru P. Mishra. "An Accurate Drain Current Model for Symmetric Dual Gate Tunnel FET Using Effective Tunneling Length." Nanoscience &Nanotechnology-Asia 9, no. 1 (December 26, 2018): 85–91. http://dx.doi.org/10.2174/2210681207666170612081017.

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Introduction: Here we propose an accurate drain current model for a Symmetric Dual Gate Tunnel FET (SDG-TFET) using effective tunneling length and generation rate of carrier over tunneling junction area. Analytical Modeling: The surface potential of the model is obtained by solving 2-dimensional Poisson’s equation and further extends to determine the magnitude of initial tunneling length and final tunneling length. The different DC performance indicators like drain current (ID), threshold voltage (Vth), transconductance (gm) and Subthreshold Slope (SS) for the present model are extensively investigated and the results are compared with that of Single Gate Tunnel FET (SGTFET). Conclusion: The practical importance of this model relies on its accuracy and improved electrostatic performance over SG-TFET. The analytical model results are validated using TCAD Sentaurus (Synopsys) device simulator.

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Boufouss, E., J. Alvarado, and D. Flandre. "Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000077–82. http://dx.doi.org/10.4071/hitec-eboufouss-ta25.

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A temperature dependence analysis of the single event transient current induced by heavy ions irradiation is performed in the range of 300K to 500K on a 1μm SOI CMOS MOSFET standard 6T-SRAM cell. The Sentaurus TCAD mixed-mode numerical simulation showed a significant impact of the temperature on the current induced by the radiation and as a result, an increase of the 6T-SRAM sensitivity upon radiation. A SOI MOSFET compact model introduced in SPICE as a Verilog-A module reproducing the single event effects was developed. This model shows a very good agreement with the TCAD simulations results but with a drastic reduction of the simulation time. Furthermore this model could be extended to other circuits simulations. This result is of importance to allow for extensive circuit design studies which cannot be carried out with TCAD physical simulations.

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Mishra, Sikha, Urmila Bhanja, and Guru Prasad Mishra. "An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET." Nanoscience & Nanotechnology-Asia 9, no. 4 (November 25, 2019): 504–11. http://dx.doi.org/10.2174/2210681208666180820151121.

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Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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Othman, Nurul Aida Farhana, Sharidya Rahman, Sharifah Fatmadiana Wan Muhamad Hatta, Norhayati Soin, Brahim Benbakhti, and Steven Duffy. "Design optimization of the graded AlGaN/GaN HEMT device performance based on material and physical dimensions." Microelectronics International 36, no. 2 (April 1, 2019): 73–82. http://dx.doi.org/10.1108/mi-09-2018-0057.

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Purpose To design and optimize the traditional aluminum gallium nitride/gallium nitride high electron mobility transistor (HEMT) device in achieving improved performance and current handling capability using the Synopsys’ Sentaurus TCAD tool. Design/methodology/approach Varying material and physical considerations, specifically investigating the effects of graded barriers, spacer interlayer, material selection for the channel, as well as study of the effects in the physical dimensions of the HEMT, have been extensively carried out. Findings Critical figure-of-merits, specifically the DC characteristics, 2DEG concentrations and mobility of the heterostructure device, have been evaluated. Significant observations include enhancement of maximum current density by 63 per cent, whereas the electron concentration was found to propagate by 1,020 cm−3 in the channel. Practical implications This work aims to provide tactical optimization to traditional heterostructure field effect transistors, rendering its application as power amplifiers, Monolithic Microwave Integrated Circuit (MMICs) and Radar, which requires low noise performance and very high radio frequency design operations. Originality/value Analysis in covering the breadth and complexity of heterostructure devices has been carefully executed through extensive TCAD modeling, and the end structure obtained has been optimized to provide best performance.

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Danilenko, Alexander A., Anton V. Strygin, Nikolay I. Mikhailov, Vadim V. Perepelovsky, Yaroslav N. Panichev, Vladislav V. Marochkin, and Vladimir L. Ivanov. "PROGRAMMING 2-BIT PIN DIODE IN SYNOPSYS TCAD." Journal of the Russian Universities. Radioelectronics, no. 5 (December 6, 2018): 51–59. http://dx.doi.org/10.32603/1993-8985-2018-21-5-51-59.

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The article is devoted to the modeling of a two-bit pin-diode. The possibility of programming opening time of the device based on the pin-diode is shown. The design consisting of a pin diode and two floating gates on the surface of i-region is considered. The addition of electrodes to the surface of the i-region makes it possible to regulate the concentration of electrons and holes within the larger limits in compare with the single-gate structure creating enriched and depleted are-as in the structure. Programming is carried out by applying the appropriate voltage to the control electrodes of the floating gates. It is shown that the charge generated on the floating gate changes characteristics of the i-region of the pin diode.The key elements of complex simulation of the two-gate pin diode are simulation of charge accumulation mechanism on the floating gate, simulation of pin-diode opening time and calibration of numerical model. Simulation is performed in Synopsys Sentaurus TCAD. Physical models describing traps and their parameters, particle tunneling, transport phenomena in dielectrics and amorphous films are used in simulation. As a result of modeling, the opening time dependences on size, floating gate location and floating gate charge magnitude are obtained.It is shown that the pin-diode 2-gate structures allow to change the opening time in a wider range than the single-gate ones. To program a large range of pin-diode opening times, it is 2 gate structure that is advisable to use. The obtained results indicate that it is possible to implement a two-bit programming pin-diode and expand its functionality.

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Pu, Aobo, Fajun Ma, Chang Yan, Jialiang Huang, Kaiwen Sun, Martin Green, and Xiaojing Hao. "Sentaurus modelling of 6.9% Cu2ZnSnS4 device based on comprehensive electrical & optical characterization." Solar Energy Materials and Solar Cells 160 (February 2017): 372–81. http://dx.doi.org/10.1016/j.solmat.2016.10.053.

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Rodríguez, R., B. González, J. García, A. Lázaro, B. Iñiguez, and A. Hernández. "Large-Signal DG-MOSFET Modelling for RFID Rectification." Advances in Condensed Matter Physics 2016 (2016): 1–6. http://dx.doi.org/10.1155/2016/8017139.

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This paper analyses the undoped DG-MOSFETs capability for the operation of rectifiers for RFIDs and Wireless Power Transmission (WPT) at microwave frequencies. For this purpose, a large-signal compact model has been developed and implemented in Verilog-A. The model has been numerically validated with a device simulator (Sentaurus). It is found that the number of stages to achieve the optimal rectifier performance is inferior to that required with conventional MOSFETs. In addition, the DC output voltage could be incremented with the use of appropriate mid-gap metals for the gate, as TiN. Minor impact of short channel effects (SCEs) on rectification is also pointed out.

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Palomo, F. R., P. Fernández-Martínez, J. M. Mogollón, S. Hidalgo, M. A. Aguirre, D. Flores, I. López-Calle, and J. A. de Agapito. "Simulation of femtosecond pulsed laser effects on MOS electronics using TCAD Sentaurus customized models." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 23, no. 4-5 (January 19, 2010): 379–99. http://dx.doi.org/10.1002/jnm.736.

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Li, Joel B., and Bruce M. Clemens. "Modeling the Performance of Biaxially-Textured Silicon Solar Cells." MRS Proceedings 1670 (2014). http://dx.doi.org/10.1557/opl.2014.590.

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ABSTRACTGrain boundaries (GBs) in polycrystalline silicon (poly-Si) thin film solar cells are frequently found to be detrimental for device performance. Biaxiallytextured silicon with grains that are well-aligned in-plane and out-of-plane can possess fewer GB defects. In this work, we use TCAD Sentaurus device simulator and known experimental work to investigate and quantify the potential performance gains of biaxially-textured silicon. Simulation shows there can be performance gain from well-aligned grains when GB defects dominate carrier recombination or when grains are small. On the other hand, when intra-grain defects dominate recombination and grains are large, well-aligned grains do not lead to much performance gain. Another important result from our simulation is when intra-grain and GB defects are few, Jsc is almost independent of grain size while Voc drops with decreasing grain size.

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"Simulation photoelectric parameters of vertical junction solar cells." International Journal of Advanced Trends in Computer Science and Engineering 10, no. 2 (April 5, 2021): 543–48. http://dx.doi.org/10.30534/ijatcse/2021/131022021.

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Many properties of the solar cells are being studied extensively. In this study, the basic photoelectric parameters of vertical junction solar cell were modeled. Attempts were made to approach the scientific work both physically and programmatically. In terms of programming, a perfect algorithm has been developed for modeling vertical junction solar cell in the Sentaurus TCAD software package. Using this algorithm, a vertical junction solar cell was modeled. The main focus was on the comparison of the photoelectric parameters of a vertical junction solar cell consisting of 3 elements with the photoelectric parameters of a vertical solar cell consisting of single element. The results obtained were physically based.

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Zechner, Christoph, Dmitri Matveev, Nikolas Zographos, Victor Moroz, and Bartek Pawlak. "Modeling Ultra Shallow Junctions Formed by Phosphorus-Carbon and Boron-Carbon Co-implantation." MRS Proceedings 994 (2007). http://dx.doi.org/10.1557/proc-0994-f11-17.

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AbstractA new carbon-interstitial clustering model has been developed. The model has been implemented into the process simulator Sentaurus Process. Model parameters have been calibrated using fundamental marker layer experiments. B diffusion retardation in the C doped layer as well as Sb diffusion enhancement in the region close to a layer with high C concentration are successfully simulated. The calibrated model has been applied to simulations of ultra-shallow junction formation by high dose P-C and B-C co-implantation. It is assumed that, in regions which are amorphized by ion implantation and recrystallized by solid phase epitaxy, C is in the substitutional state right after the recrystallization. In contrast, in non-amorphized regions, C is assumed to be in clusters at the beginning of thermal annealing. A good agreement between simulation and experimental results has been achieved. The dependence of dopant diffusion on implanted C dose and spike annealing temperature has been reproduced.

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Morozzi, Arianna, Francesco Moscatelli, Tommaso Croci, and Daniele Passeri. "TCAD Modeling of Surface Radiation Damage Effects: A State-Of-The-Art Review." Frontiers in Physics 9 (February 2, 2021). http://dx.doi.org/10.3389/fphy.2021.617322.

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A comprehensive numerical model which accounts for surface damage effects induced by radiation on silicon particle detectors is presented with reference to the state-of-the-art Synopsys Sentaurus Technology CAD (TCAD) tool. The overall aim of this work is to present the “Perugia 2019 Surface” damage modeling scheme, fully implemented within the TCAD environment, which effectively describes the surface damage effects induced by radiation in silicon sensors relying on a limited number of parameters relevant for physics. To this end, extensive measurement campaigns have been recently performed on gated-diodes and MOS capacitors at Fondazione Bruno Kessler (FBK) in Italy, Hamamatsu Photonics (HPK) in Japan and Infineon Technologies (IFX) in Austria on both n-type and p-type substrates (with and without p-spray isolation implants), in order to extrapolate the relevant parameters which rule the surface damage effects. The integrated interface trap density and the oxide charge density, have been determined before and after X-ray irradiation with doses ranging from 0.05 to 100 Mrad(SiO2), for each specific foundry and technology flavor. The main guidelines of this study are the versatility and generality of the simulation approach.

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Tang, Zhenyu, Xiaoyan Tang, Shi Pu, Yimeng Zhang, Hang Zhang, Yuming Zhang, and Song Bo. "Study on high temperature model based on the n-Channel planar 4H-SiC MOSFET." Circuit World ahead-of-print, ahead-of-print (June 10, 2021). http://dx.doi.org/10.1108/cw-12-2020-0351.

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Purpose To use the 4H-SiC material in integrated circuits for high temperature application, an accurate and simple circuit model of n-channel planar 4H-SiC MOSFET is required. Design/methodology/approach In this paper, a SPICE model of n-channel planar 4H-SiC MOSFET was built based on the device simulation results and measurement results. Firstly, a device model was simulated with Sentaurus TCAD, with measured parameters from fabricated planar 4H-SiC MOSFET previously. Then the device simulation results were analyzed and parameters for SPICE models were extracted. With these parameters, an accurate SPICE model was built and simulated. Findings The SPICE model exhibits the same performance as the measured results with different environment temperatures. The simulation results indicate that the maximum fitting error is 0.22 mA (7.33% approximately) at 200 °C. A common-source amplifier with this model is also simulated and the simulated gain is stable at different environment temperatures. Originality/value This paper provides a reliable modeling method for n-Channel Planar 4H-SiC MOSFET and reference value for the design of 4H-SiC high temperature integrated circuit.

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"Influence of Self-Heating Effect on I-V Dates of Party Depleted Submicron Silicon-on-Insulator CMOS Transistors at High Ambient Temperatures." International Journal of Innovative Technology and Exploring Engineering 9, no. 1 (November 10, 2019): 1446–50. http://dx.doi.org/10.35940/ijitee.a4244.119119.

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To solve the problems of high temperature microelectronics the influence of the self heating effect on the IV dates partially depleted submicron silicon–on-insulator CMOS transistor in the ambient temperature range from 525 K to 650 K is discussed. Approach consists in combination of experimental data and of computational simulating results. For simulation of electrothermal characteristics of SOI CMOS transistor is considered three-layered structure. Temperature distribution is calculated numerically using iterative algorithm in conjunction with software COMSOL Multiphysics. I-V dates of SOI CMOS transistors are calculated by means of two-dimensional models for n-and p-channel transistors of Sentaurus TCAD developed in the system of instrument and technological modelling. TCAD models are calibrated on experimental characteristics for 525 K. It is shown that with growth of ambient temperature the selfheating mechanism contribution consistently decreases. By results of modeling it is established that self-heating contributions at supply voltages 5.5 V to decreases for ntransistor in 2.8 times, p-transistor in 2.2 times. The relative decline of current n-type transistor for reduced from 11.6% to 5.5% and for p-type with 15% to 9%. However, different dynamics of current recession for n-and p-transistors is significant for analog applications that need to be considered at high-temperature circuit design. The proposed methodology allows to critically assess the contribution of the self-heating mechanism on the I-V dates for a wide range of high temperatures and supply voltages. Underestimating this fact leads to unreasonable values for the maximum temperature and limit of thermal stability for the separate SOI CMOS transistor. In total this can be a prerequisite for a significant simplification of the design of not only the chip construction but also the whole electronic Board.

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"Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator." International Journal of Innovative Technology and Exploring Engineering 8, no. 12S2 (December 31, 2019): 61–66. http://dx.doi.org/10.35940/ijitee.l1012.10812s219.

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This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.

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Journal articles on the topic 'Sentaurus Modeling'

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