Relevant bibliographies by topics / Sentaurus synopsys

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Sentaurus synopsys'

Author: Grafiati
Published: 4 June 2025
Last updated: 15 July 2025

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Journal articles on the topic "Sentaurus synopsys"

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Jaikumar, M. G., and Shreepad Karmalkar. "Calibration of Mobility and Interface Trap Parameters for High Temperature TCAD Simulation of 4H-SiC VDMOSFETs." Materials Science Forum 717-720 (May 2012): 1101–4. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1101.

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4H-Silicon Carbide VDMOSFET is simulated using the Sentaurus TCAD package of Synopsys. The simulator is calibrated against measured data for a wide range of bias conditions and temperature. Material parameters of 4H-SiC are taken from literature and used in the available silicon models of the simulator. The empirical parameters are adjusted to get a good fit between the simulated curves and measured data. The simulation incorporates the bias and temperature dependence of important physical mechanisms like interface trap density, coulombic interface trap scattering, surface roughness scattering and velocity saturation.
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Uhnevionak, Viktoryia, Alex Burenkov, Christian Strenger, et al. "Effect of Bulk Potential Engineering on the Transport Properties of SiC MOSFETs: Characterization and Interpretation." Materials Science Forum 821-823 (June 2015): 737–40. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.737.

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The effect of bulk potential engineering on the transport properties in the channel of SiC MOSFETs has been studied. For this purpose, n-channel SiC MOSFETs have been manufactured with different background doping concentrations and characterized electrically at room temperature by current-voltage as well as by Hall-effect measurements. To interpret the measurements performed, numerical simulations have been carried out using Sentaurus Device of Synopsys. The main finding of the simulation analysis is that the change in the depth of the band-bending has to be considered to explain the doping dependence of SiC MOSFET characteristics.
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Johannesson, Daniel, Muhammad Nawaz, and Hans Peter Nee. "TCAD Model Calibration of High Voltage 4H-SiC Bipolar Junction Transistors." Materials Science Forum 963 (July 2019): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.963.670.

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In this project, a Technology CAD (TCAD) model has been calibrated and verified against experimental data of a 15 kV silicon carbide (SiC) bipolar junction transistor (BJT). The device structure of the high voltage BJT has been implemented in the Synopsys Sentaurus TCAD simulation platform and design of experiment simulations have been performed to extract and fine-tune device parameters and 4H-SiC material parameters to accurately reflect the 15 kV SiC BJT experimental results. The set of calibrated TCAD parameters may serve as a base for further investigations of various SiC device design and device operation in electrical circuits.
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Kim, Ki Yeong, Joo Seok Noh, Tae Young Yoon, and Jang Hyun Kim. "Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers." Micromachines 12, no. 11 (2021): 1422. http://dx.doi.org/10.3390/mi12111422.

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In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.
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Nipoti, Roberta, Giovanna Sozzi, Maurizio Puzzanghera, and Roberto Menozzi. "Al+ implanted vertical 4H-SiC p-i-n diodes: experimental and simulated forward current-voltage characteristics." MRS Advances 1, no. 54 (2016): 3637–42. http://dx.doi.org/10.1557/adv.2016.315.

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ABSTRACT The temperature dependence of the forward and reverse current voltage characteristics of circular Al+ implanted 4H-SiC p-i-n vertical diodes of various diameters, post implantation annealed at 1950 °C/5 min, have been used to obtain the thermal activation energies of the defects responsible of the generation and the recombination currents, as well as the area and the periphery current component of the current voltage characteristics. The former have values compatible with those of the traps associated to the carbon vacancy defect in 4H-SiC. The hypothesis that only these traps may justify the trend of the current voltage characteristics of the studied diodes has been tested by simulations in a Synopsys Sentaurus TCAD suite.
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Moni, Jackuline, and T. Jaspar Vinitha Sundari. "Junctionless Tunneling Nanowire for Steep Subthreshold Slope." Advanced Science Letters 24, no. 8 (2018): 5695–99. http://dx.doi.org/10.1166/asl.2018.12179.

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Using standardized simulations, we report a meticulous learning of the Junctionless nanowire with tunneling mechanism and the dependence of Subthreshold slope on operational parameters by varying the channel diameter, Gate length and doping concentration using Synopsys Sentaurus TCAD simulations. For the first time, Junctionless Nanowire in the company of tunneling architecture is proposed and explored. Our simulation study shows that a decrease in channel diameter and doping concentration results in higher band to band generation and steeper slope. Junctionless tunneling nanowire of diameter 10 nm, gate length of 20 nm, and uniform doping concentration of 1e19 cm−3 obtains steepest Subthreshold swing of about 8 mV/dec (point) and 52 mV/dec (average), an on/off current ratio of 1010, on current of 10−5 A/um.
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Uhnevionak, Viktoryia, Alex Burenkov, Christian Strenger, et al. "Hall Factor Calculation for the Characterization of Transport Properties in N-Channel 4H-SiC MOSFETs." Materials Science Forum 778-780 (February 2014): 483–86. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.483.

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For the characterization ofn-channel 4H-SiC MOSFETs, current-voltage and Hall-effect measurements were carried out at room temperature. To interpret the Hall-effect measurements, the Hall factor for the electron transport in the channel of SiC MOSFETs was evaluated, for the first time. The method of the Hall factor calculation is based on the interdependence with mobility components via the respective scattering relaxation times. The results of the calculation reveal a strong dependence of the Hall factor on the gate voltage. Depending on the gate voltage applied, the values of the Hall factor vary between 1.3 and 1.5. Sheet carrier density and drift mobility values derived from the Hall-effect measurements using our new gate-voltage-dependent Hall factor show very good agreement with simulations performed with Sentaurus Device of Synopsys.
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Sahoo, Sasmita, Sidhartha Dash, and Guru P. Mishra. "An Accurate Drain Current Model for Symmetric Dual Gate Tunnel FET Using Effective Tunneling Length." Nanoscience &Nanotechnology-Asia 9, no. 1 (2018): 85–91. http://dx.doi.org/10.2174/2210681207666170612081017.

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Introduction: Here we propose an accurate drain current model for a Symmetric Dual Gate Tunnel FET (SDG-TFET) using effective tunneling length and generation rate of carrier over tunneling junction area. Analytical Modeling: The surface potential of the model is obtained by solving 2-dimensional Poisson’s equation and further extends to determine the magnitude of initial tunneling length and final tunneling length. The different DC performance indicators like drain current (ID), threshold voltage (Vth), transconductance (gm) and Subthreshold Slope (SS) for the present model are extensively investigated and the results are compared with that of Single Gate Tunnel FET (SGTFET). Conclusion: The practical importance of this model relies on its accuracy and improved electrostatic performance over SG-TFET. The analytical model results are validated using TCAD Sentaurus (Synopsys) device simulator.
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Koptev, N. S., and A. A. Pugachev. "TCAD-ASSISTED TECHNIQUE FOR DETERMINING THE PARAMETERS OF MICROLENSES USED IN PHOTOSENSITIVE CCD VLSI." Electronic engineering Series 2 Semiconductor devices 257, no. 2 (2020): 28–36. http://dx.doi.org/10.36845/2073-8250-2020-257-2-28-36.

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In this paper we introduce the simulation technique for photosensitive cell with CCD VLSI microlens with interline transfer. A microlens enhances the photosensitivity of the cell and reduces image blur. The technique is based on the calculation and comparison of the volumetric photogeneration rate integrals of different areas of the photocell, where generated charge carriers are collected and transferred. This technique does not require simulation of the full frame accumulation cycle of the cell, significantly reducing the time of simulation and enabling the evaluation of many design options for microlenses. The technique is implemented in the Sentaurus TCAD (by Synopsys). In the paper we present the results of simulation made for cells with various microlenses. The proposed technique can also be used for the optimization of microlenses of CMOS photodiode VLSI photocells.
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Danilenko, Alexander A., Anton V. Strygin, Nikolay I. Mikhailov, et al. "PROGRAMMING 2-BIT PIN DIODE IN SYNOPSYS TCAD." Journal of the Russian Universities. Radioelectronics, no. 5 (December 6, 2018): 51–59. http://dx.doi.org/10.32603/1993-8985-2018-21-5-51-59.

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The article is devoted to the modeling of a two-bit pin-diode. The possibility of programming opening time of the device based on the pin-diode is shown. The design consisting of a pin diode and two floating gates on the surface of i-region is considered. The addition of electrodes to the surface of the i-region makes it possible to regulate the concentration of electrons and holes within the larger limits in compare with the single-gate structure creating enriched and depleted are-as in the structure. Programming is carried out by applying the appropriate voltage to the control electrodes of the floating gates. It is shown that the charge generated on the floating gate changes characteristics of the i-region of the pin diode.The key elements of complex simulation of the two-gate pin diode are simulation of charge accumulation mechanism on the floating gate, simulation of pin-diode opening time and calibration of numerical model. Simulation is performed in Synopsys Sentaurus TCAD. Physical models describing traps and their parameters, particle tunneling, transport phenomena in dielectrics and amorphous films are used in simulation. As a result of modeling, the opening time dependences on size, floating gate location and floating gate charge magnitude are obtained.It is shown that the pin-diode 2-gate structures allow to change the opening time in a wider range than the single-gate ones. To program a large range of pin-diode opening times, it is 2 gate structure that is advisable to use. The obtained results indicate that it is possible to implement a two-bit programming pin-diode and expand its functionality.
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Dissertations / Theses on the topic "Sentaurus synopsys"

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Al, Hajjar Ahmad. "Caractérisation basse fréquence et simulation physique de transistors bipolaires hétérojonction en vue de l'analyse du bruit GR assisté par pièges." Thesis, Limoges, 2016. http://www.theses.fr/2016LIMO0045/document.

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Ce travail présente le développement d’un banc de mesure thermique, pour la mesure : de réseaux I (V), d’impédance basse fréquence et de bruit basse fréquence des composants semi-conducteurs. Le banc de mesure de bruit BF est composé d’un amplificateur de tension faible bruit, d’un amplificateur transimpédance, d’un analyseur FFT et d’un support thermique. Ce banc a permis d’extraire les sources de bruit en courants équivalentes aux accès du transistor pour différentes densités de courant et à différentes températures. Dans le but de calculer l’énergie d’activation et la section de capture des pièges grâce à la localisation des fréquences de coupures de bruit GR dans la technologie du TBH InGaP/GaAs. Dans un deuxième temps, nous avons étudié le bruit basse fréquence dans le transistor InGaP/GaAs et les jonctions base émetteur, base collecteur et la résistance TLM par le moyen de simulation physique et de mesure de densité spectrale de puissance de bruit basse fréquence. Grâce à ces mesures, nous avons pu extraire les sources de bruit internes locales commandées et non commandées. Cette extraction nous a permis de calculer les énergies d’activations, les sections de capture et de valider la simulation physique<br>This work presents the development of a thermal test bench for I(V) characteristics, for low frequency impedance and for low frequency noise of semiconductor components. This thermal bench for low frequency noise measurement is composed of a low-noise voltage amplifier, a low-noise transimpedance amplifier, an FFT vector signal analyzer and a thermal chuck. This measurement bench has allowed to extract the current noise sources equivalent to the access transistor at different current densities and at different temperatures. In order to calculate the activation energy and the capture cross section of traps thanks to the localization of the cutoff frequency of GR noise in HBT InGaP / GaAs technology. Secondly, we studied the low frequency noise in the transistor InGaP / GaAs and the differents junctions: emitter base, collector base and the base represented by the TLM resistance using physical simulations and measurements of low-frequency noise power spectrum density. Using this measurements, we extract the controlled and not controlled local internal noise sources. The extraction has allowed us to calculate the activation energy, the capture cross sections and validate the physical simulation
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Book chapters on the topic "Sentaurus synopsys"

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Wu, Yung-Chun, and Yi-Ruei Jhan. "Introduction of Synopsys Sentaurus TCAD Simulation." In 3D TCAD Simulation for CMOS Nanoeletronic Devices. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-3066-6_1.

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Conference papers on the topic "Sentaurus synopsys"

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Medvedev, Dmitriy, and Aleksey Malahanov. "MODELING OF THE HIGH-VOLTAGE SILICON SCHOTTKY DIODE." In CAD/EDA/SIMULATION IN MODERN ELECTRONICS 2021. Bryansk State Technical University, 2021. http://dx.doi.org/10.30987/conferencearticle_61c997f09d8527.44162014.

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