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1
Jaikumar, M. G., and Shreepad Karmalkar. "Calibration of Mobility and Interface Trap Parameters for High Temperature TCAD Simulation of 4H-SiC VDMOSFETs." Materials Science Forum 717-720 (May 2012): 1101–4. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1101.
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4H-Silicon Carbide VDMOSFET is simulated using the Sentaurus TCAD package of Synopsys. The simulator is calibrated against measured data for a wide range of bias conditions and temperature. Material parameters of 4H-SiC are taken from literature and used in the available silicon models of the simulator. The empirical parameters are adjusted to get a good fit between the simulated curves and measured data. The simulation incorporates the bias and temperature dependence of important physical mechanisms like interface trap density, coulombic interface trap scattering, surface roughness scattering and velocity saturation.
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Uhnevionak, Viktoryia, Alex Burenkov, Christian Strenger, et al. "Effect of Bulk Potential Engineering on the Transport Properties of SiC MOSFETs: Characterization and Interpretation." Materials Science Forum 821-823 (June 2015): 737–40. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.737.
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The effect of bulk potential engineering on the transport properties in the channel of SiC MOSFETs has been studied. For this purpose, n-channel SiC MOSFETs have been manufactured with different background doping concentrations and characterized electrically at room temperature by current-voltage as well as by Hall-effect measurements. To interpret the measurements performed, numerical simulations have been carried out using Sentaurus Device of Synopsys. The main finding of the simulation analysis is that the change in the depth of the band-bending has to be considered to explain the doping dependence of SiC MOSFET characteristics.
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Johannesson, Daniel, Muhammad Nawaz, and Hans Peter Nee. "TCAD Model Calibration of High Voltage 4H-SiC Bipolar Junction Transistors." Materials Science Forum 963 (July 2019): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.963.670.
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In this project, a Technology CAD (TCAD) model has been calibrated and verified against experimental data of a 15 kV silicon carbide (SiC) bipolar junction transistor (BJT). The device structure of the high voltage BJT has been implemented in the Synopsys Sentaurus TCAD simulation platform and design of experiment simulations have been performed to extract and fine-tune device parameters and 4H-SiC material parameters to accurately reflect the 15 kV SiC BJT experimental results. The set of calibrated TCAD parameters may serve as a base for further investigations of various SiC device design and device operation in electrical circuits.
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Kim, Ki Yeong, Joo Seok Noh, Tae Young Yoon, and Jang Hyun Kim. "Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers." Micromachines 12, no. 11 (2021): 1422. http://dx.doi.org/10.3390/mi12111422.
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In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.
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Nipoti, Roberta, Giovanna Sozzi, Maurizio Puzzanghera, and Roberto Menozzi. "Al+ implanted vertical 4H-SiC p-i-n diodes: experimental and simulated forward current-voltage characteristics." MRS Advances 1, no. 54 (2016): 3637–42. http://dx.doi.org/10.1557/adv.2016.315.
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ABSTRACT The temperature dependence of the forward and reverse current voltage characteristics of circular Al+ implanted 4H-SiC p-i-n vertical diodes of various diameters, post implantation annealed at 1950 °C/5 min, have been used to obtain the thermal activation energies of the defects responsible of the generation and the recombination currents, as well as the area and the periphery current component of the current voltage characteristics. The former have values compatible with those of the traps associated to the carbon vacancy defect in 4H-SiC. The hypothesis that only these traps may justify the trend of the current voltage characteristics of the studied diodes has been tested by simulations in a Synopsys Sentaurus TCAD suite.
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Moni, Jackuline, and T. Jaspar Vinitha Sundari. "Junctionless Tunneling Nanowire for Steep Subthreshold Slope." Advanced Science Letters 24, no. 8 (2018): 5695–99. http://dx.doi.org/10.1166/asl.2018.12179.
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Using standardized simulations, we report a meticulous learning of the Junctionless nanowire with tunneling mechanism and the dependence of Subthreshold slope on operational parameters by varying the channel diameter, Gate length and doping concentration using Synopsys Sentaurus TCAD simulations. For the first time, Junctionless Nanowire in the company of tunneling architecture is proposed and explored. Our simulation study shows that a decrease in channel diameter and doping concentration results in higher band to band generation and steeper slope. Junctionless tunneling nanowire of diameter 10 nm, gate length of 20 nm, and uniform doping concentration of 1e19 cm−3 obtains steepest Subthreshold swing of about 8 mV/dec (point) and 52 mV/dec (average), an on/off current ratio of 1010, on current of 10−5 A/um.
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Uhnevionak, Viktoryia, Alex Burenkov, Christian Strenger, et al. "Hall Factor Calculation for the Characterization of Transport Properties in N-Channel 4H-SiC MOSFETs." Materials Science Forum 778-780 (February 2014): 483–86. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.483.
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For the characterization ofn-channel 4H-SiC MOSFETs, current-voltage and Hall-effect measurements were carried out at room temperature. To interpret the Hall-effect measurements, the Hall factor for the electron transport in the channel of SiC MOSFETs was evaluated, for the first time. The method of the Hall factor calculation is based on the interdependence with mobility components via the respective scattering relaxation times. The results of the calculation reveal a strong dependence of the Hall factor on the gate voltage. Depending on the gate voltage applied, the values of the Hall factor vary between 1.3 and 1.5. Sheet carrier density and drift mobility values derived from the Hall-effect measurements using our new gate-voltage-dependent Hall factor show very good agreement with simulations performed with Sentaurus Device of Synopsys.
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Sahoo, Sasmita, Sidhartha Dash, and Guru P. Mishra. "An Accurate Drain Current Model for Symmetric Dual Gate Tunnel FET Using Effective Tunneling Length." Nanoscience &Nanotechnology-Asia 9, no. 1 (2018): 85–91. http://dx.doi.org/10.2174/2210681207666170612081017.
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Introduction: Here we propose an accurate drain current model for a Symmetric Dual Gate Tunnel FET (SDG-TFET) using effective tunneling length and generation rate of carrier over tunneling junction area. Analytical Modeling: The surface potential of the model is obtained by solving 2-dimensional Poisson’s equation and further extends to determine the magnitude of initial tunneling length and final tunneling length. The different DC performance indicators like drain current (ID), threshold voltage (Vth), transconductance (gm) and Subthreshold Slope (SS) for the present model are extensively investigated and the results are compared with that of Single Gate Tunnel FET (SGTFET). Conclusion: The practical importance of this model relies on its accuracy and improved electrostatic performance over SG-TFET. The analytical model results are validated using TCAD Sentaurus (Synopsys) device simulator.
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Koptev, N. S., and A. A. Pugachev. "TCAD-ASSISTED TECHNIQUE FOR DETERMINING THE PARAMETERS OF MICROLENSES USED IN PHOTOSENSITIVE CCD VLSI." Electronic engineering Series 2 Semiconductor devices 257, no. 2 (2020): 28–36. http://dx.doi.org/10.36845/2073-8250-2020-257-2-28-36.
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In this paper we introduce the simulation technique for photosensitive cell with CCD VLSI microlens with interline transfer. A microlens enhances the photosensitivity of the cell and reduces image blur. The technique is based on the calculation and comparison of the volumetric photogeneration rate integrals of different areas of the photocell, where generated charge carriers are collected and transferred. This technique does not require simulation of the full frame accumulation cycle of the cell, significantly reducing the time of simulation and enabling the evaluation of many design options for microlenses. The technique is implemented in the Sentaurus TCAD (by Synopsys). In the paper we present the results of simulation made for cells with various microlenses. The proposed technique can also be used for the optimization of microlenses of CMOS photodiode VLSI photocells.
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Danilenko, Alexander A., Anton V. Strygin, Nikolay I. Mikhailov, et al. "PROGRAMMING 2-BIT PIN DIODE IN SYNOPSYS TCAD." Journal of the Russian Universities. Radioelectronics, no. 5 (December 6, 2018): 51–59. http://dx.doi.org/10.32603/1993-8985-2018-21-5-51-59.
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The article is devoted to the modeling of a two-bit pin-diode. The possibility of programming opening time of the device based on the pin-diode is shown. The design consisting of a pin diode and two floating gates on the surface of i-region is considered. The addition of electrodes to the surface of the i-region makes it possible to regulate the concentration of electrons and holes within the larger limits in compare with the single-gate structure creating enriched and depleted are-as in the structure. Programming is carried out by applying the appropriate voltage to the control electrodes of the floating gates. It is shown that the charge generated on the floating gate changes characteristics of the i-region of the pin diode.The key elements of complex simulation of the two-gate pin diode are simulation of charge accumulation mechanism on the floating gate, simulation of pin-diode opening time and calibration of numerical model. Simulation is performed in Synopsys Sentaurus TCAD. Physical models describing traps and their parameters, particle tunneling, transport phenomena in dielectrics and amorphous films are used in simulation. As a result of modeling, the opening time dependences on size, floating gate location and floating gate charge magnitude are obtained.It is shown that the pin-diode 2-gate structures allow to change the opening time in a wider range than the single-gate ones. To program a large range of pin-diode opening times, it is 2 gate structure that is advisable to use. The obtained results indicate that it is possible to implement a two-bit programming pin-diode and expand its functionality.
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Gulomov, Jasurbek, Rayimjon Aliev, Murad Nasirov, and Jakhongir Ziyoitdinov. "MODELING METAL NANOPARTICLES INFLUENCE TO PROPERTIES OF SILICON SOLAR CELLS." International Journal of Advanced Research 8, no. 11 (2020): 336–45. http://dx.doi.org/10.21474/ijar01/12015.
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Nanotechnologies are entering every field. Nanoparticles have been widely used in medicine and technology. We decided to study the behavior of nanoparticles under the influence of light and its effects on solar cells, based on a number of properties. How gold and silver nanoparticles are introduced into the optical layer of the solar cell has been studied enough to affect the properties of the solar cell. However, the effect of silicon-based solar cell metal nanoparticles in the n domain on the solar cell has not been sufficiently studied. In addition, in this study, the properties of solar cells, which included nanoparticles of various shapes, were modeled. Since the end of the last century, new methods of modeling have been introduced into scientific research. A lot of modeling software has been developed. They are based on a numerical method. Synopsys program of Sentaurus TCAD software package was used in the modeling to ensure the accuracy and reliability of the research. Using Sentaurus TCAD, a model of a silicon-based solar cell with simple and various shapes of platinum nanoparticles embedded in the n field was developed. The focus is on determining the effect of the shape of a nanoparticle introduced on solar cells on its properties. The effect of nanoparticles on the optical and I-V characteristics of a solar cell is also analyzed in depth.
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Erman, Azwan Yahya, Kannan Ramani, and Lee Lini. "Simulation study of single event effects sensitivity on commercial power MOSFET with single heavy ion radiation." Bulletin of Electrical Engineering and Informatics 8, no. 4 (2019): 1260–67. https://doi.org/10.11591/eei.v8i4.1611.
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High-frequency semiconductor devices are key components for advanced power electronic system that require fast switching speed. Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the most famous electronic device that are used in much power electronic system. However, the application such as space borne, military and communication system needs Power MOSFET to withstand in radiation environments. This is very challenging for the engineer to develop a device that continuously operated without changing its electrical behavior due to radiation. Therefore, the main objective of this study is to investigate the Single Event Effect (SEE) sensitivity by using Heavy Ion Radiation on the commercial Power MOSFET. A simulation study using Sentaurus Synopsys TCAD software for process simulation and device simulation was done. The simulation results reveal that single heavy ion radiation has affected the device structure and fluctuate the I-V characteristic of commercial Power MOSFET.
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Zhang, Hao, Shupeng Chen, Hongxia Liu, et al. "Polarization Gradient Effect of Negative Capacitance LTFET." Micromachines 13, no. 3 (2022): 344. http://dx.doi.org/10.3390/mi13030344.
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In this paper, an L-shaped tunneling field effect transistor (LTFET) with ferroelectric gate oxide layer (Si: HfO2) is proposed. The electric characteristic of NC-LTFET is analyzed using Synopsys Sentaurus TCAD. Compared with the conventional LTFET, a steeper subthreshold swing (SS = 18.4 mV/dec) of NC-LTFET is obtained by the mechanism of line tunneling at low gate voltage instead of diagonal tunneling, which is caused by the non-uniform voltage across the gate oxide layer. In addition, we report the polarization gradient effect in a negative capacitance TFET for the first time. It is noted that the polarization gradient effect should not be ignored in TFET. When the polarization gradient parameter g grows larger, the dominant tunneling mechanism that affects the SS is the diagonal tunneling. The on-state current (Ion) and SS of NC-LTFET become worse.
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Wozny, Janusz, Zbigniew Lisik, and Jacek Podgorski. "Influence of the Metal–Semiconductor Interface Model on Power Conservation Principle in a Simulation of Bipolar Devices." Electronics 10, no. 24 (2021): 3120. http://dx.doi.org/10.3390/electronics10243120.
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The purpose of the study is to present a proper approach that ensures the energy conservation principle during electrothermal simulations of bipolar devices. The simulations are done using Sentaurus TCAD software from Synopsys. We focus on the drift-diffusion model that is still widely used for power device simulations. We show that without a properly designed contact(metal)–semiconductor interface, the energy conservation is not obeyed when bipolar devices are considered. This should not be accepted for power semiconductor structures, where thermal design issues are the most important. The correct model of the interface is achieved by proper doping and mesh of the contact-semiconductor region or by applying a dedicated model. The discussion is illustrated by simulation results obtained for the GaN p–n structure; additionally, Si and SiC structures are also presented. The results are also supported by a theoretical analysis of interface physics.
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Boughedda, A., M. Lakhdara, S. Latreche, R. Mendicino, and G. F. Dalla Betta. "Comparing different bulk radiation damage models in TCAD simulations of small-pitch 3D Si sensors." Journal of Instrumentation 16, no. 10 (2021): C10006. http://dx.doi.org/10.1088/1748-0221/16/10/c10006.
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Abstract Small-pitch, thin 3D Si sensors have been developed for the ATLAS and CMS experiment upgrades at the High Luminosity LHC. The pixel sizes are 50 × 50 µm2 with 1 readout column, and 25 × 100 µm2 with 1 or 2 readout columns (1E and 2E). Owing to the small inter-electrode distance, ranging from ∼28 µm to ∼51 µm in the considered layouts, these devices are expected to be extremely radiation hard. TCAD simulations by Synopsys Sentaurus, incorporating advanced radiation damage models, have been used for the design/optimization of these new 3D pixel sensors. In this study, we have compared the accuracy of different bulk damage models in predicting the signal efficiency of small-pitch 3D sensors irradiated at large fluences and its evolution with the bias voltage at different positions within the 3D cell. Selected simulation results will be reported in comparison to experimental data.
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Yin, Sujie, Wei Cao, Xiarong Hu, Xinglai Ge, and Dong Liu. "A Novel Super-Junction DT-MOS with Floating p Regions to Improve Short-Circuit Ruggedness." Micromachines 14, no. 10 (2023): 1962. http://dx.doi.org/10.3390/mi14101962.
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A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (tsc). The super-junction structure enables the device to possess an excellent compromise of breakdown voltage (BV) and specific on-resistance (Ron,sp). Under short-circuit conditions, the depletion of p-pillar, p-shield, and floating p regions can effectively reduce saturation current and improve short-circuit capability. The proposed device has minimum gate-drain charge (Qgd) and gate-drain capacitance (Cgd) compared with other devices. Moreover, the formation of floating p regions will not lead to an increase in process complexity. Therefore, the proposed MOSFET can maintain good dynamic and static performance and short-circuit ability together without increasing the difficulty of the process.
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Fondacci, A., T. Croci, D. Passeri, et al. "Design and optimisation of radiation resistant AC- and DC-coupled resistive LGADs." Journal of Instrumentation 20, no. 06 (2025): C06016. https://doi.org/10.1088/1748-0221/20/06/c06016.
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Abstract Future high-energy physics experiments require a paradigm shift in radiation detector design. In response to this challenge, resistive LGADs that combine Low Gain Avalanche Diode technology with resistive readout have been developed. The prototypes created so far, employing AC-coupled contacts, have demonstrated impressive performance, achieving a temporal resolution of 38 ps and a spatial resolution of 15 µm with a pixel pitch of 450 µm. To tackle some of the issues encountered up to this point, particularly the non-uniform response across the entire surface of the detector, a new version with DC-coupled contacts has recently been developed. The Synopsys® Sentaurus TCAD simulations that have guided the design of their first production, released by the Fondazione Bruno Kessler in November 2024, will be presented below along with a concise summary of the history of the prototypes with AC-coupled contacts.
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Azwan, Erman, Ramani Kannan, Lini Lee, and Saranya Krishnamurthy. "Study the Effects of Photon Radiation on Power MOSFET for Harsh Environment Application." MATEC Web of Conferences 225 (2018): 05013. http://dx.doi.org/10.1051/matecconf/201822505013.
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The rapid growth of the advanced technologies in power electronics system gives a challenge to the electronic device to sustain with the modern technologies nowadays. The challenges are also including the place where the system was installed for example the application in the harsh environment. Harsh environment application requires an electronic device deals with radiation pollution. Hence, the electronic device will suffer from this phenomenon and make the whole system to malfunction and break down. Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is one type of electronic device that is the most broadly for high voltage and high switching speed application. The aim of this paper is to studies the photon radiation effect toward the Power MOSFET performance. The study focus on the changing of the electrical characteristics of the device after radiated with photon radiation. Process simulation and Device simulation tools in Sentaurus Synopsys Software used for the research to validate all the theory.
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Tunga, Ashwin, Kexin Li, Ethan White, et al. "A comparison of a commercial hydrodynamics TCAD solver and Fermi kinetics transport convergence for GaN HEMTs." Journal of Applied Physics 132, no. 22 (2022): 225702. http://dx.doi.org/10.1063/5.0118104.
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Various simulations of a GaN HEMT are used to study the behaviors of two different energy-transport models: the Fermi kinetics transport model and a hydrodynamics transport model as it is implemented in the device simulator Sentaurus from Synopsys. The electron transport and heat flow equations of the respective solvers are described in detail. The differences in the description of electron flux and the discretization methods are highlighted. Next, the transport models are applied to the same simulated device structure using identical meshes, boundary conditions, and material parameters. Static simulations show the numerical convergence of Fermi kinetics to be consistently quadratic or faster, whereas the hydrodynamic model is often sub-quadratic. Further comparisons of large-signal transient simulations reveal the hydrodynamic model produces certain anomalous electron ensemble behaviors within the transistor structure. The fundamentally different electron dynamics produced by the two models suggest an underlying cause for their different numerical convergence characteristics.
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Tierno, Davide, Victor Vega-Gonzalez, Simone Esposto, and Ivan Ciofi. "Resistance modeling of short-range connections: impact of current spreading." Japanese Journal of Applied Physics 62, SC (2023): SC1034. http://dx.doi.org/10.35848/1347-4065/acad0b.
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Abstract We investigated the impact of current spreading on the resistance of short-range connections by performing simulations in Synopsys Sentaurus, based on a calibrated resistivity model. As a main case study, we considered vertical-horizontal-vertical (VHV) connections, a novel cell-routing architecture based on a two-level middle-of-line scheme, that has been proposed to boost the routing of four-track standard cells beyond the 2 nm technology node. We analyzed the impact of vias and line geometry on VHV link resistance and we found that low aspect ratio (AR) lines are needed to minimize the average cell resistance. We performed extensive resistance simulations of various short-range connection schemes beyond VHV links. We concluded that large AR lines are detrimental in all cases in which the link resistance is dominated by the vias. Finally, we show that ignoring current spreading can lead to a significant miscalculation of the link resistance in such scenarios.
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Maurya, Vishwajeet, Daniel Alquier, Mohammed El Amrani, Matthew Charles, and Julien Buckley. "Optimisation of Negative Fixed Charge Based Edge Termination for Vertical GaN Schottky Devices." Micromachines 15, no. 6 (2024): 719. http://dx.doi.org/10.3390/mi15060719.
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This study focuses on the impact of negative fixed charge, achieved through fluorine (F) implantation, on breakdown voltage (BV) enhancement in vertical GaN Schottky diodes. Several device and implant-related parameters are examined using Synopsys Sentaurus TCAD simulations in order to determine the optimum fixed negative charge concentration required to achieve the highest BV. The simulated structure consisted of a Schottky diode with a box consisting of negative fixed charges to achieve the edge termination of the Schottky device. An empirical equation is proposed to determine the optimum fixed charge concentration for the highest BV based on depth. The simulation also considered implantation profiles derived from SIMS data from an actual device implanted with multi-energy and multi-dose F. It is demonstrated that the BV has a similar dependence on the key parameters like in the box profile. In summary, this work provides valuable insights into optimizing edge termination techniques using negative fixed charge for improved BV in vertical GaN power devices.
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Martinez-Limia, Alberto, Peter Pichler, Christian Steen, Silke Paul, and Wilfried Lerch. "Modeling of the Diffusion and Activation of Arsenic in Silicon Including Clustering and Precipitation." Solid State Phenomena 131-133 (October 2007): 277–82. http://dx.doi.org/10.4028/www.scientific.net/ssp.131-133.277.
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We have developed a diffusion and activation model for implanted arsenic in silicon. The model includes the dynamic formation of arsenic-vacancy complexes (As4V) as well as the precipitation of a SiAs phase. The latter is mandatory to correctly describe concentrations above solid solubility while the former are needed to describe the reduced electrical activity as well as the generation of self-interstitials during deactivation. In addition, the activation state after solid-phase epitaxy and the segregation at the interface to SiO2 are taken into account. After implementation using the Alagator language in the latest version of the Sentaurus Process Simulator of Synopsys, the parameters of the model were optimized using reported series of diffusion coefficients for temperatures between 700 °C and 1200 °C, and using several SIMS profiles covering annealing processes from spike to very long times with temperatures between 700 °C and 1050 °C and a wide distribution of implantation energies and doses. The model was validated using data from flash-assisted RTP and spike annealing of ultra-low energy arsenic implants.
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Suh Song, Young, Hyunwoo Kim, Junsu Yu, and Jongho Lee. "Improvement in Self-Heating Characteristic by Utilizing Sapphire Substrate in Omega-Gate-Shaped Nanowire Field Effect Transistor for Wearable, Military, and Aerospace Application." Journal of Nanoscience and Nanotechnology 21, no. 5 (2021): 3092–98. http://dx.doi.org/10.1166/jnn.2021.19149.
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In this study, we propose an omega-shaped-gate nanowire field effect transistor (ONWFET) with a silicon-on-sapphire (SOS) substrate. In order to investigate improvements in the self-heating characteristic with the use of a SOS substrate, the lattice temperature is examined using a Synopsys Sentaurus 3D Technology computer-aided design (TCAD) simulator with the results compared to those with a silicon-on-insulator (SOI) substrate. To validate the proposed structure with the SOS substrate, the locations of hot spots and heat dissipation paths (heat sinks) depending on the substrate materials are also analyzed. The electrical characteristics, specifically the on-current (Ion), off-current (Ioff), and subthreshold swing (SS), were investigated as well. Hence, it is demonstrated here that incorporating a SOS substrate can improve both the self-heating characteristic and the SS at the same time. Therefore, enhanced logic devices are feasible if using an ONWFET with a SOS substrate. Examples include wearable devices and military and future aerospace applications achieved by the radiation-resistant material Al2O3 that has high thermal conductivity.
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Othman, Nurul Aida Farhana, Sharidya Rahman, Sharifah Fatmadiana Wan Muhamad Hatta, Norhayati Soin, Brahim Benbakhti, and Steven Duffy. "Design optimization of the graded AlGaN/GaN HEMT device performance based on material and physical dimensions." Microelectronics International 36, no. 2 (2019): 73–82. http://dx.doi.org/10.1108/mi-09-2018-0057.
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Purpose To design and optimize the traditional aluminum gallium nitride/gallium nitride high electron mobility transistor (HEMT) device in achieving improved performance and current handling capability using the Synopsys’ Sentaurus TCAD tool. Design/methodology/approach Varying material and physical considerations, specifically investigating the effects of graded barriers, spacer interlayer, material selection for the channel, as well as study of the effects in the physical dimensions of the HEMT, have been extensively carried out. Findings Critical figure-of-merits, specifically the DC characteristics, 2DEG concentrations and mobility of the heterostructure device, have been evaluated. Significant observations include enhancement of maximum current density by 63 per cent, whereas the electron concentration was found to propagate by 1,020 cm−3 in the channel. Practical implications This work aims to provide tactical optimization to traditional heterostructure field effect transistors, rendering its application as power amplifiers, Monolithic Microwave Integrated Circuit (MMICs) and Radar, which requires low noise performance and very high radio frequency design operations. Originality/value Analysis in covering the breadth and complexity of heterostructure devices has been carefully executed through extensive TCAD modeling, and the end structure obtained has been optimized to provide best performance.
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Pape, Sebastian, Michael Moll, Marcos Fernández García, and Moritz Wiehe. "TCAD Simulation of Two Photon Absorption—Transient Current Technique Measurements on Silicon Detectors and LGADs." Sensors 24, no. 24 (2024): 8032. https://doi.org/10.3390/s24248032.
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Device simulation plays a crucial role in complementing experimental device characterisation by enabling deeper understanding of internal physical processes. However, for simulations to be trusted, experimental validation is essential to confirm the accuracy of the conclusions drawn. In the framework of semiconductor detector characterisation, one powerful tool for such validation is the Two Photon Absorption-Transient Current Technique (TPA-TCT), which allows for highly precise, three-dimensional spatially-resolved characterisation of semiconductor detectors. In this work, the TCAD framework Synopsys Sentaurus is used to simulate depth-resolved TPA-TCT data for both p-type pad detectors (PINs) and Low Gain Avalanche Detectors (LGADs). The simulated data are compared against experimentally measured TPA-TCT results. Through this comparison, it is demonstrated that TCAD simulations can reproduce the TPA-TCT measurements, providing valuable insights into the TPA-TCT itself. Another significant outcome of this study is the successful simulation of the gain reduction mechanism, which can be observed in LGADs with increasing densities of excess charge carriers. This effect is demonstrated in an p-type LGAD with a thickness of approximately 286 µm. The results confirm the ability of TCAD to model the complex interaction between carrier dynamics and device gain.
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Liu, An-Chen, Yu-Wen Huang, Hsin-Chu Chen, and Hao-Chung Kuo. "Improvement Performance of p-GaN Gate High-Electron-Mobility Transistors with GaN/AlN/AlGaN Barrier Structure." Micromachines 15, no. 4 (2024): 517. http://dx.doi.org/10.3390/mi15040517.
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This study demonstrates a particular composited barrier structure of high-electron-mobility transistors (HEMTs) with an enhancement mode composed of p-GaN/GaN/AlN/AlGaN/GaN. The purpose of the composite barrier structure device is to increase the maximum drain current, reduce gate leakage, and achieve lower on-resistance (Ron) performance. A comparison was made between the conventional device without the composited barrier and the device with the composited barrier structure. The maximum drain current is significantly increased by 37%, and Ron is significantly reduced by 23%, highlighting the synergistic impact of the composite barrier structure on device performance improvement. This reason can be attributed to the undoped GaN (u-GaN) barrier layer beneath p-GaN, which was introduced to mitigate Mg diffusion in the capping layer, thus addressing its negative effects. Furthermore, the AlN barrier layer exhibits enhanced electrical properties, which can be attributed to the critical role of high-energy-gap properties that increase the 2DEG carrier density and block leakage pathways. These traps impact the device behavior mechanism, and the simulation for a more in-depth analysis of how the composited barrier structure brings improvement is introduced using Synopsys Sentaurus TCAD.
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Ryzhova, Daria, Ivan Pavlov, and Ivan Asapov. "Buried power rails and backside power distribution for nanometer-scale IC design." EPJ Web of Conferences 321 (2025): 03002. https://doi.org/10.1051/epjconf/202532103002.
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The technologies of buried power rails and backside power distribution networks are promising tools for reducing the size of nanoscale CMOS-based circuits. They provide significant improvement in many system-level parameters, for example, voltage drop and power losses are reduced by more than 2 times, and when using a ruthenium buried power rail - by more than 4 times, while also significantly reducing the delay on critical paths and the overall circuit area. However, to fully realize the potential of this technology, it is necessary to solve a number of problems related to the technological process and architecture. In this paper, the authors examine the prospects and challenges associated with the implementation of buried power rail technology and backside power distribution networks. Physical characteristics of semiconductor devices were also selected for model creation and technological simulation in the Synopsys Sentaurus TCAD environment, as well as for physical synthesis in commercial computer-aided design systems and open-source software. The developed models and methods will be included in the open design flow for integrated CMOS circuits with a technological process of 15 nm and below.
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Han, Ke, Shanglin Long, Zhongliang Deng, Yannan Zhang, and Jiawei Li. "A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications." Micromachines 11, no. 2 (2020): 164. http://dx.doi.org/10.3390/mi11020164.
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This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing ( S S AVG ) and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( I ON ) (11.9 μ A), a low OFF-state current ( I OFF ) ( 2.85 × 10 − 9 μ A), and a low and steady S S AVG (57.29 mV/decade), with the OFF-state current increasing by 10 7 times. The GAS GAA TFET has high potential for use in low-power applications.
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Shailesh, M. Gheewala, Parmesh Chinthakunta, N. Patel Piyush, and Dhavse Rasika. "Simulation and Fabrication of Macro Porous Silicon for Highly Chemicapacitive Detection for Aqueous Solvent." Journal of Sensor Research and Technologies 3, no. 2 (2021): 1–14. https://doi.org/10.5281/zenodo.4857229.
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<em>Porous structured silicon material is most suited for sensing applications. In this paper, the fabricated porous structure silicon chemicapacitive device for sensing different chemical aqueous solvents. The design of the Porous Structure Silicon simulating in the 2-Dimension Synopsys Sentaurus Technology Computer-Aided Design (TCAD) tool. In the silicon substrate, the porous structure was fabricated by laser etching using Pulse Fiber Laser. Field emission scanning electron microscopy shows the average pore diameter 55.22 µm and pore depth 98.90 µm. Two front sides silver contact electrodes on the porous structure silicon made by colloidal silver conductive paste. The fabricated chemicapacitive device tested for different chemical aqueous solvents. The sensing electrical parameter is measured by the LCR meter. The application of the porous structure silicon chemicapacitive demonstrates the different concentrations of the ethyl alcohol aqueous solvent, which is used in medial, food, beverages, and fuel application. The fabricated chemicapacitive device gives a stable performance for 35 days of standard ambient temperature and pressure. The limit of detection and sensitivity of the fabricated chemicapacitive device was 0.474 ppm and 0.26 nF/ppm, respectively. The chemicapacitive based porous structure silicon is suitable for economical sensing and monitoring chemical aqueous solvent used in agriculture, beverages, chemical, medical, and pharmaceutical industries.</em>
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Shi, Yijun, Zongqi Cai, Yun Huang, et al. "An AlGaN/GaN Lateral Bidirectional Current-Regulating Diode with Two Symmetrical Hybrid Ohmic-Schottky Structures." Micromachines 13, no. 7 (2022): 1157. http://dx.doi.org/10.3390/mi13071157.
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Bidirectional current-regulating ability is needed for AC light emitting diode (LED) drivers. In previous studies, various rectifier circuits have been used to provide constant bidirectional current. However, the usage of multiple electronic components can lead to additional costs and power consumption. In this work, a novel AlGaN/GaN lateral bidirectional current-regulating diode (B-CRD) featuring two symmetrical hybrid-trench electrodes is proposed and demonstrated by TCAD Sentaurus (California USA) from Synopsys corporation. Through shortly connecting the Ohmic contact and trench Schottky contact, the unidirectional invariant current can be obtained even with the applied voltage spanning a large range of 0–200 V. Furthermore, with the combination of two symmetrical hybrid-trench electrodes at each side of the device, the proposed B-CRD can deliver an excellent steady current in different directions. Through the TCAD simulation results, it was found that the device’s critical characteristics (namely knee voltage and current density) can be flexibly modulated by tailoring the depth and length of the trench Schottky contact. Meanwhile, it was also demonstrated through the device/circuit mixed-mode simulation that the proposed B-CRD can respond to the change in voltage in a few nanoseconds. Such a new functionality combined with excellent performance may make the proposed B-CRD attractive in some special fields where the bidirectional current-limiting function is needed.
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Malahanov, Aleksey, and Dmitriy Medvedev. "MODELING POWER CHARACTERISTICS OF SCHOTTKY DIODE UNDER EXTREME OPERATION MODES." Automation and modeling in design and management 2022, no. 2 (2022): 92–100. http://dx.doi.org/10.30987/2658-6436-2022-2-92-100.
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The results of device-technological modelling of static current-voltage characteristics (CVC), as well as the dependences of differential resistance and power dissipation for the structure of a silicon carbide Schottky diode in Synopsys Sentaurus TCAD are presented. As a result of the research and modelling, the design and technological parameters of the Schottky diode are selected, on the basis of which the current-voltage characteristics are obtained, comparable with the specified accuracy with the physical experiment (the anode current is not less than 100 A, the breakdown voltage is not less than 1400 V at a temperature of 77 K). Verifying the static characteristics of the Schottky diode obtained by the instrumental-technological modelling is carried out by comparing the results of a computational experiment with a physical study of the Cree C4D20120D diode for a temperature range from 300 K to 77 K. The novelty of the work lies in developing an instrument-technological model (ITM) of a semiconductor device that takes into consideration a crystal self-heating effect; obtaining results reflecting the characteristics of a semiconductor device in the normal and extreme temperature operating conditions; in obtaining dependences reflecting the change in differential resistance and power dissipation; in having the possibility to use the results of the developed ITM for the industrial implementation of the silicon carbide Schottky diode at Russian enterprises in the form of discrete semiconductor devices, or elements as part of semiconductor power modules.
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Danilenko, A. A., A. D. Ivanov, V. L. Ivanov, V. V. Marochkin, M. N. Ivanovich, and P. V. Vsevolodovich. "The Characteristics of the pin-Structure with a Discrete Metallic Surface i-Region." Journal of the Russian Universities. Radioelectronics 23, no. 1 (2020): 41–51. http://dx.doi.org/10.32603/1993-8985-2020-23-1-41-51.
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Introduction. Currently, an interest in improving pin-structures continues to be the focus of attention of developers of electronic devices. Devices that use controlled pin-structures include: non-volatile memory, static voltage protection device, pin-diodes with adjustable characteristics, etc. However, insufficient attention is paid to the issue of controlling the characteristics of pin-structures by using discrete metallization on the surface of i-region.Aim. Investigation of the influence of discrete metallization of the surface of i-region on static and dynamic characteristics of pin-structure, defect compensation, and efficiency control of the pin-photodetector.Materials and methods. The pin-structure under study consisted of p + -boron-doped region; n + -phosphorusdoped region; i-phosphorus-doped region; semi-insulating substrate; metallization of the substrate; polysilicon control gate; and a silicon oxide dielectric layer. Two-dimensional numerical analysis of the potential distribution, of the concentration of free charge carriers and currents was performed in the Synopsys Sentaurus TCAD environment.Results. Two-dimensional analysis of discretely metallized pin-structures was performed. The stresses applied to the gates of i-region that compensated the influence of defects formed by electron irradiation were determined. Four pin-photodetector structures were modeled, in which the control gates were performed in the form of metal–dielectric–semiconductor structure. The possibility of increasing the sensitivity of the pinphotodetector by applying the corresponding potentials to the gates was demonstrated.Conclusion. An effect of discrete metallization of i-region of the pin-structure was investigated. A method for correcting of the characteristics of the irradiated pin-diode to the initial characteristics was proposed. It makes possible to use such diodes in electronics with high requirements for operating in areas with high radiation. The design of a high-sensitivity photodetector with control gates on the surface of i-region and with the structure of low alloy i-region split into two regions (p- and n–type conductivity) was proposed.
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Khanna, Raghav. "(Invited) Breakdown Improvement and Reverse Recovery Characterization in Vertical GaN PN Diodes." ECS Meeting Abstracts MA2022-01, no. 31 (2022): 1308. http://dx.doi.org/10.1149/ma2022-01311308mtgabs.
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Wide bandgap semiconductor devices based on gallium nitride (GaN) and silicon carbide (SiC) are attractive semiconductor technologies for future generation power electronics. Lateral GaN HEMTs have dominated the low voltage arena, while SiC MOSFETs have been the preferred technology for higher voltage applications. Devices based on GaN are regarded as having a strong potential for next generation power electronics owing to their high electron mobility, high thermal conductivity, high critical electric field and very low reverse recovery time. The theoretical high voltage capability of GaN is superior to both SiC and silicon (Si), which has resulted in significant government investment for the development of vertical GaN architectures, with a particular emphasis on thicker epitaxial layers, as well as more reliable substrates. The relative improvement in the development of native GaN substrates over the recent years has encouraged production of homo-epitaxial GaN-on-GaN vertical devices with low defect densities and reduced capacitances. Some major advantages of vertical GaN devices include their design robustness, due to avalanche breakdown capability, as well as their ability to attain higher blocking voltages through appropriate edge termination. One of the major challenges in designing junction terminations in GaN vertical devices is the limitation in selective area ptype doping. Selective area p-type doping in GaN is typically performed via Mg implantation, which is known to have a low activation efficiency as well as limited range of implant energy and dosage. Addressing these limitations requires innovative design of termination structures. Iterative refinement between TCAD modeling and fabrication can facilitate design optimization to improve breakdown potential. Circuit simulation can be used to project the performance of the device in various applications and benchmark its performance against other conventional materials. This paper proposes a vertical GaN diode with a blocking capability of 1.3 kV, acquired through a simple technique of edge termination. The initial device design consists of a very highly doped (2 × 1020 cm−3) p++ capping layer on top of the pGaN layer to facilitate the formation of a low resistance ohmic contact with the anode metal. Four samples differing in p-type doping levels are studied under reverse bias using Sentaurus TCAD (Synopsys). The simulations are used to examine the regions of the device that are highly susceptible to field crowding, leading to design considerations for improved breakdown performance. It is shown both through simulations and empirically, that elimination of the highly doped p++ capping layer allows the lower doped p-type layer to serve as a Junction Termination Extension (JTE). The proposed simplified technique of edge termination is produced by the regulation of charge in the lower doped pGaN layer, and does not require selective area p-type doping, thereby substantially improving the manufacturability. The empirically validated diode characteristics are then exported to a circuit simulator and compared to a similarly-rated commercially available Si ultra-fast diode using a double pulse test (DPT). Comparison of the switching characteristics of both the diodes reveals that the proposed GaN diode shows significantly higher efficiency during reverse recovery. Fig. 1 shows the shows the initial device design under consideration. A TCAD model of this device was then implemented in Sentaurus TCAD (Synopsys). The simulated device structure is shown in Fig. 2. Fig. 2(a) illustrates a magnified view of the drift and pGaN layer, above the substrate, while the mesh structure of the entire device is shown Fig. 2(b). Fig. 3 illustrates simulated and experimental static characteristics of the devices, both in terms of forward conduction, and reverse breakdown. As can be seen in Fig. 3, the model accurately predicts the static characteristics of the device. However, wafers two and three (W2 and W3) have significantly lower pGaN doping than wafer one and wafer four. This would suggest a greater breakdown voltage for wafer 2 and wafer 3. However, as seen in Fig. 3, this was not the case. Further analysis via TCAD reveals that the p++ capping layer is the reason for the premature breakdown of W2 and W3. Fig. 4 shows electric field distribution plots for W3 before and after selective removal of the p++ capping layer. Prior to removal, the electric field is unable to uniformly spread across the junction, as seen in Fig. 4(a). On the contrary, after removal of the p++ capping layer, a more uniform electric field distribution is obtained. These simulated results were validated experimentally as seen in Fig. 5. The p++ capping layer was etched away everywhere except underneath the anode. From Fig. 5, the breakdown potential of the device improves by approximately 50%. Figure 1
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Eneman, Geert, Anabela Veloso, Paola Favia, et al. "(Invited) Mechanical Stress Simulations for Advanced Logic Devices." ECS Meeting Abstracts MA2023-02, no. 30 (2023): 1520. http://dx.doi.org/10.1149/ma2023-02301520mtgabs.
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Novel transistor concepts are continuously being investigated to scale beyond FinFETs and nanosheets. One such architecture is the Complementary FET (CFET), consisting of an NFET and a PFET fabricated on top of each other [1-4], offering increased device density thanks to its stacking. However, additional challenges arise, such as significantly complicated processing and higher complexity of the connections between devices. Another concern lies in the optimization of the device performance by incorporating mechanical channel strain: in particular for the top-channel device it is challenging to employ traditional stressors efficiently, as it is largely disconnected from the substrate underneath. The purpose of this study is to study whether a CFET technology, and especially its top-channel device can be properly stressed. To this end, a TCAD process simulation flow that mimics the relevant steps for stress modeling has been built using Sentaurus-Process [5]. An example of a quarter-structure of the simulated CFET at the end of the simulation (after channel release) is shown in Fig. 1. The device has a gate length of 14nm, a fin-like silicon channel both for the top and bottom device (5nm width, 30nm height), and fully strained source/drain (S/D) epitaxial layers in the bottom and top devices. For the top (NFET) device, the source/drain epi does not fill up all available space but consists rather of a thin layer grown against the sidewalls of the device, as observed experimentally. Tungsten contacts are added to connect the devices, and a thin oxide layer is present in the source/drain regions to isolate the top from the bottom device. Fig. 2 shows the longitudinal channel stress in the channels for a varying composition of the top-channel S/D epi. A large compressive (i.e. negative) stress is generated in the bottom PFET channels, thanks to the strained Si0.5Ge0.5 bottom S/D epi. On the other hand, the channel stress in the top channel is much smaller and becomes more tensile (positive) for higher Ge% in the top S/D. This opposite trend from traditional S/D’s was reported for nanowires in [6] and can be explained by the fact that the top S/D does not fill up the available space, which leads also to a large reduction in absolute channel stress. Another observation from Fig. 2 is that the stress in the bottom channel is independent of the composition in the top S/D, indicating that the devices are mechanically decoupled. Fig. 3 plots the channel stress in the structure after various steps of the simulation, showing that a small channel stress is generated after S/D etch by the presence of the sacrificial layer (Si0.75Ge0.25) between the channels. Furthermore, dummy gate removal tends to increase the absolute channel stress. Finally, the bottom S/D epi growth does not affect the top-channel stress, again confirming the mechanical decoupling of both channels to first order. Fig. 4 shows how the channel stress is affected for an intrinsic tensile stress of 2GPa in the tungsten or oxide isolation between the devices. Tungsten is a rather ineffective stressor due to its high stiffness: less than 200MPa tensile top-channel stress is generated by a stressed tungsten in its S/D’s. For the bottom device, the effect is even smaller due to the increased distance between the bottom-tungsten and the channel. The oxide isolation proves to be a more efficient stressor for the top channel, leading to about 1GPa additional tensile stress which is concentrated at the bottom of the channel. The presentation will highlight the importance of other stress components besides longitudinal stress. Furthermore, whereas the results in Figs. 1-4 were obtained for fin-like (vertically elongated) devices, a CFET technology can also be built using nanosheet (horizontally elongated) channels. It will be shown that changing towards this type of channels leads to a significant change of the stressor effectiveness in CFET technologies. These insights will help us to continue improving the device performance in advanced transistor architectures like CFETs. References [1] W. Rachmady et al, IEDM Tech. Dig., 697 (2019). [2] S. Subramanian et al., VLSI Tech. Dig., TH3.1 (2020). [3] C.-Y. Huang et al, IEDM Tech. Dig., 425 (2020). [4] M. Radosavljevic et al., IEDM Tech. Dig., 721 (2021). [5] Sentaurus Process Reference Manual, Synopsys, M-2016.12 (2016). [6] G. Eneman et al., ECS Trans. 98 (5), pp. 253 (2020) Figure 1
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Liu, Xue Qing, Sauvik Chowdhury, Collin W. Hitchcock, and T. Paul Chow. "Impact of Cell Geometry on Zero-Energy Turn-Off of SiC Power MOSFETs." Materials Science Forum 924 (June 2018): 756–60. http://dx.doi.org/10.4028/www.scientific.net/msf.924.756.
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1200V SiC power MOSFETs of various cell geometries are modeled in Synopsis Inc. Sentaurus TCAD. The impact of cell geometry on switching loss is studied by comparing the turn-on and turn-off losses using refined calculation methods. Under optimum circuit conditions, two different novel unit cell designs each achieve lower switching losses than conventional designs. For all the designs, lossless turn-on is impossible but lossless turn-off is achievable under circuit and biasing conditions that produce sufficiently rapid gate slew.
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Yang, Shao-Ming, Gene Sheu, Tzu Chieh Lee, Ting Yao Chien, Chieh Chih Wu, and Yun Jung Lin. "Design of a Low on Resistance High Voltage (120V) Novel 3D NLDMOS with Side Isolation Based on 0.35um BCD Process Technology." MATEC Web of Conferences 201 (2018): 02004. http://dx.doi.org/10.1051/matecconf/201820102004.
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High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and successfully simulated. We implemented in a conventional 0.35um BCDMOS process to present of a novel high side 120V LDMOS have reduced surface field (RESURF) and Liner p-top structure with side isolation technology. The device has been research to achieve a benchmark specific on-resistance of 189 mΩ-mm2 while maintaining horizontal breakdown voltage and vertical isolation voltage both to target breakdown voltage of 120V. In ESOA, we also proposed a better performance of both device without kirk effect.
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Mohapatra, Sushanta, Kumar Pradhan, and Prasanna Sahu. "ZTC bias point of advanced fin based device: The importance and exploration." Facta universitatis - series: Electronics and Energetics 28, no. 3 (2015): 393–405. http://dx.doi.org/10.2298/fuee1503393m.
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The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25?C to 225?C is reviewed to extend the benchmark of device scalability. The impact of fin height (HFin), fin width (WFin), and temperature (T) on immense performance metrics including on-off ratio (Ion/Ioff), transconductance (gm), gain (AV), cut-off frequency (fT), static power dissipation (PD), energy (E), energy delay product (EDP), and sweet spot (gmfT/ID) of the FinFET is successfully carried out by commercially available TCAD simulator SentaurusTM from Synopsis Inc.
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Zacharias, Joel, Pramod Martha, and V. Seena. "Polymer Ring–Flexure–Membrane Suspended Gate FET Gas Sensor: Design, Modelling and Simulation." Micromachines 14, no. 5 (2023): 944. http://dx.doi.org/10.3390/mi14050944.
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This work reports the design, modelling, and simulation of a novel polymer MEMS gas sensor platform called a ring–flexure–membrane (RFM) suspended gate field effect transistor (SGFET). The sensor consists of a suspended polymer (SU-8) MEMS based RFM structure holding the gate of the SGFET with the gas sensing layer on top of the outer ring. During gas adsorption, the polymer ring–flexure–membrane architecture ensures a constant gate capacitance change throughout the gate area of the SGFET. This leads to efficient transduction of the gas adsorption-induced nanomechanical motion input to the change in the output current of the SGFET, thus improving the sensitivity. The sensor performance has been evaluated for sensing hydrogen gas using the finite element method (FEM) and TCAD simulation tools. The MEMS design and simulation of the RFM structure is carried out using CoventorWare 10.3, and the design, modelling, and simulation of the SGFET array is carried out using the Synopsis Sentaurus TCAD. A differential amplifier circuit using RFM-SGFET is designed and simulated in Cadence Virtuoso using the lookup table (LUT) of the RFM-SGFET. The differential amplifier exhibits a sensitivity of 2.8 mV/MPa for a gate bias of 3 V and a maximum detection range of up to 1% hydrogen gas concentration. This work also presents a detailed fabrication process integration plan to realize the RFM-SGFET sensor using a tailored self-aligned CMOS process adopting the surface micromachining process.
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Tessler, Nir, Seonuk Jeon, and Jiyong Woo. "Enhancing the Performance of Electrochemical RAM (ECRAM) through Modeling Guided Device Engineering." ECS Meeting Abstracts MA2024-01, no. 30 (2024): 1497. http://dx.doi.org/10.1149/ma2024-01301497mtgabs.
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Traditionally, the only ions allowed or welcomed by the microelectronic industry are those that act as fixed dopants. The issue of mobile ions became welcome primarily due to the memristor technology however, thin film transistor technologies benefit from them too. The electrochemical (transistor) random access memory (ECRAM) is emerging as a promising building block for multi-level neuromorphic computing. Using FAB-compatible materials we construct the ECRAM using CuOx as the gate and ions source (Cu+). The morphology of the HfOx gate insulator layer is tuned to render it ion transporting such that it can act as a uniform electrolyte layer. Lastly, the channel material is WOx with tungsten metal as the source/drain contact. While there are several reports of ECRAM devices, the operation mechanisms are not fully known/understood thus withholding progress of this field. Using the Sentaurus device simulator by Synopsis, including the hydrogen diffusion module, we simulate the mixed ionic electronic operation of the device. We have recently reported that by fitting the simulation to the device performance, we could identify the potentiation mechanism (i.e., insulator charging) and the occurrence of copper plating that takes place under high Cu+ ion flux (as in fast charging of Li batteries).[1] In the first part of the talk, we will expand on the chemical-physics details of the ECRAM device mentioned above. Next, we will present a new device architecture where we remove the WOx layer and study the ionic-electronic conduction of a modified HfOx layer. By fine-tuning the stoichiometry of the HfOx layer, it assumes both roles of ionic electrolyte and electronic conducting channel. Following detailed modelling of the measured properties, we introduce AlO2 as an ionic barrier layer at the WOx/HfOx interface to enhance the ionic retention of the HfOx layer. Using the above three device architectures in conjunction with the mixed ionic-electronic device simulation we reveal the role of the two memory mechanisms: a) Electric field-activated ion transport and b) Structure-induced trapping by ion-barrier layers. Reference [1] Nir Tessler, Nayeon Kim, Heebum Kang, Jiyong Woo; Switching mechanisms of CMOS-compatible ECRAM transistors—Electrolyte charging and ion plating. J. Appl. Phys. 21 August 2023; 134 (7): 074501. https://doi.org/10.1063/5.0154153 Figure 1
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Li, Yuan, Wang Weizhu, Boon Lee Kean, et al. "On the Operation Mechanism and Device Modeling of AlGaN/GaN High Electron Mobility Transistors (HEMTs)." September 26, 2012. https://doi.org/10.5281/zenodo.1057627.
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In this work, the physical based device model of AlGaN/GaN high electron mobility transistors (HEMTs) has been established and the corresponding device operation behavior has been investigated also by using Sentaurus TCAD from Synopsys. Advanced AlGaN/GaN hetero-structures with GaN cap layer and AlN spacer have been considered and the GaN cap layer and AlN spacer are found taking important roles on the gate leakage blocking and off-state breakdown voltage enhancement.
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"Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator." International Journal of Innovative Technology and Exploring Engineering 8, no. 12S2 (2019): 61–66. http://dx.doi.org/10.35940/ijitee.l1012.10812s219.
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This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.
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Zeumault, Andre, Shamiul Alam, Zack Wood, Ryan J. Weiss, Ahmedullah Aziz, and Garrett S. Rose. "TCAD Modeling of Resistive-Switching of HfO2 Memristors: Efficient Device-Circuit Co-Design for Neuromorphic Systems." Frontiers in Nanotechnology 3 (October 6, 2021). http://dx.doi.org/10.3389/fnano.2021.734121.
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In neuromorphic computing, memristors (or “memory resistors”) have been primarily studied as key elements in artificial synapse implementations, where the memristor provides a variable weight with intrinsic long-term memory capabilities, based on its modifiable resistive-switching characteristics. Here, we demonstrate an efficient methodology for simulating resistive-switching of HfO2 memristors within Synopsys TCAD Sentaurus—a well established, versatile framework for electronic device simulation, visualization and modeling. Kinetic Monte Carlo is used to model the temporal dynamics of filament formation and rupture wherein additional band-to-trap electronic transitions are included to account for polaronic effects due to strong electron-lattice coupling in HfO2. The conductive filament is modeled as oxygen vacancies which behave as electron traps as opposed to ionized donors, consistent with recent experimental data showing p-type conductivity in HfOx films having high oxygen vacancy concentrations and ab-initio calculations showing the increased thermodynamic stability of neutral and charged oxygen vacancies under conditions of electron injection. Pulsed IV characteristics are obtained by inputting the dynamic state of the system—which consists of oxygen ions, unoccupied oxygen vacancies, and occupied oxygen vacancies at various positions—into Synopsis TCAD Sentaurus for quasi-static simulations. This allows direct visualization of filament electrostatics as well as the implementation of a nonlocal, trap-assisted-tunneling model to estimate current-voltage characteristics during switching. The model utilizes effective masses and work functions of the top and bottom electrodes as additional parameters influencing filament dynamics. Together, this approach can be used to provide valuable device- and circuit-level insight, such as forming voltage, resistance levels and success rates of programming operations, as we demonstrate.
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DeMeo, Dante F., and Thomas E. Vandervelde. "Simulations of Gallium Antimonide (GaSb) p-B-n Thermophotovoltaic Cells." MRS Proceedings 1329 (2011). http://dx.doi.org/10.1557/opl.2011.1469.
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ABSTRACTThe focus of this paper is the characterization of novel thermophotovoltaic (TPV) cell designs which employ a monovalent barrier layer in the p-n junction. The use of a barrier layer enables these cells to operate at longer wavelengths, higher efficiencies, and higher operating temperatures. Initial designs have been made using gallium antimonide (GaSb), which is one of the more common TPV materials. Simulations were performed using Sentaurus by Synopsys to determine barrier materials as well as to optimize the cell. The p-B-n cell was then compared to a simple p-n junction. The simulations show that a p-B-n cell outperforms a typical p-n junction. Additionally, we expect to see increased performance differentials from this device structure when moving to longer wavelength devices.
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Geißendörfer, Stefan, Karsten von Maydell, and Carsten Agert. "Numerical 3D-Simulation of Micromorph Silicon Thin Film Solar Cells." MRS Proceedings 1321 (2011). http://dx.doi.org/10.1557/opl.2011.934.
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ABSTRACTIn this contribution 1, 2 and 3-dimensional simulations of micromorph silicon solar cells are presented. In order to simulate solar cells with rough interfaces, the surface topographies were measured via atomic force microscopy (AFM) and transferred into the commercial software Sentaurus TCAD (Synopsys). The model of the structure includes layer thicknesses and optoelectronic parameters like complex refractive index and defect structure. Results of the space resolved optical generation rates by using of the optical solver Raytracer are presented. The space resolved optical generation rate inside the semiconductor layers depends on the structure of the transparent conductive oxides (TCO) interface. In this contribution the influence of different optical generation rates on the electrical characteristics of the solar cell device are investigated. Furthermore, the optical and electrical results of the 1D, 2D and 3D structures, which have equal layer thicknesses and optoelectronic parameters, are compared.
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Yahya, Erman Azwan, Ramani Kannan, and Lini Lee. "Simulation study of single event effects sensitivity on commercial power MOSFET with single heavy ion radiation." Bulletin of Electrical Engineering and Informatics 8, no. 4 (2019). http://dx.doi.org/10.11591/eei.v8i4.1611.
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High-frequency semiconductor devices are key components for advanced power electronic system that require fast switching speed. Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the most famous electronic device that are used in much power electronic system. However, the application such as space borne, military and communication system needs Power MOSFET to withstand in radiation environments. This is very challenging for the engineer to develop a device that continuously operated without changing its electrical behavior due to radiation. Therefore, the main objective of this study is to investigate the Single Event Effect (SEE) sensitivity by using Heavy Ion Radiation on the commercial Power MOSFET. A simulation study using Sentaurus Synopsys TCAD software for process simulation and device simulation was done. The simulation results reveal that single heavy ion radiation has affected the device structure and fluctuate the I-V characteristic of commercial Power MOSFET.
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Chaitanya Akshara, Poreddy, Ramakant Yadav, and Vydya Ram Prasad. "Performance Enhancement of Gallium Nitride High Electron Mobility Transistor for High Frequency Applications Using AlInGaN as Back Barrier Layer." physica status solidi (a), May 10, 2025. https://doi.org/10.1002/pssa.202500334.
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In this work, a novel gallium nitride/aluminium gallium nitride (GaN/AlGaN) high electron mobility transistor (HEMT) structures, such as TiN as Schottky contact, HEMT with TiN as Schottky contact, and AlInGaN barrier layer are propounded and have analyzed its DC, RF performance parameters in comparison with SiO2‐based metal‐oxide‐semiconductor high electron mobility transistor (MOSHEMT) utilizing Synopsys Sentaurus technology computer‐aided design (TCAD) simulator. HEMT with TiN as Schottky contact and AlInGaN barrier layer is showing peak transconductance (Gm) of 135 mS mm−1, which is higher than HEMT with TiN as Schottky contact, that is, 117 mS mm−1. The device with TiN Schottky gate contact for the HEMT exhibits high cutoff frequency (fT = 20 GHz) and maximum oscillation frequency (fmax = 94.6 GHz) when compared with SiO2‐based MOSHEMT (fT = 12.8 GHz, fmax = 27.5 GHz). Introducing the AlInGaN barrier layer for the TiN Schottky contact‐based HEMT further increased the cutoff frequency (fT = 59.6 GHz) and maximum oscillation frequency (fmax = 324 GHz), indicating high frequency operation range for communication applications.
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Michalak, Tyler J., Chris Borst, Dan Franca, Josh Herman, and Martin Rodgers. "Simulation of Millisecond Laser Anneal on SOI: A Study of Dopant Activation and Mobility and its Application to Scaled FinFET Thermal Processing." MRS Proceedings 1562 (2013). http://dx.doi.org/10.1557/opl.2013.825.
Full textAbstract:
ABSTRACTThis work investigates scanning laser annealing used for ultra-shallow junction (USJ) activation. We investigate the laser system via simulation to determine the peak temperature achieved in the active area during processing. We employed the Sentaurus TCAD software by Synopsys to perform a 2D simulation of a laser scans across the active area of the device, solving the heat equation in both time and space. An absorber layer is deposited on the wafer surface to enhance the absorption of incident energy and reduce SOI reflectivity. An effective absorption coefficient of α=8000cm-1 was calculated for the absorber layer, calibrated with the experimental laser intensity. This absorption coefficient correctly predicts the silicon temperature as a function of power with any arbitrarily defined scan speed. To investigate the role of dopant activation, an SOI wafer was implanted with arsenic 25 keV, dose 3e15 /1.5e15 cm-2 and laser annealed in areas of target temperatures ranging from 850-1300°C. The sheet resistance was measured using 4-point probe showing sheet resistance improvement with increasing laser temperature. The extracted temperature cycle from the 2D heat simulation was used as an equivalent millisecond RTA in a full 3D process simulation to study dopant distribution and activation using Sentaurus Process Kinetic Monte Carlo (KMC), considering the effect of dopants, dopant clusters, and point defects. The results of this simulation demonstrate deactivation of arsenic above 1050°C, which is inconsistent with Hall measurements that suggest increasing laser temperature will increase mobility and activation. The results are analyzed versus the expected trends and suggest future improvements needed to the KMC model or the laser temperature profiles in order to describe activation kinetics in millisecond anneals within SOI.
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Morozzi, Arianna, Francesco Moscatelli, Tommaso Croci, and Daniele Passeri. "TCAD Modeling of Surface Radiation Damage Effects: A State-Of-The-Art Review." Frontiers in Physics 9 (February 2, 2021). http://dx.doi.org/10.3389/fphy.2021.617322.
Full textAbstract:
A comprehensive numerical model which accounts for surface damage effects induced by radiation on silicon particle detectors is presented with reference to the state-of-the-art Synopsys Sentaurus Technology CAD (TCAD) tool. The overall aim of this work is to present the “Perugia 2019 Surface” damage modeling scheme, fully implemented within the TCAD environment, which effectively describes the surface damage effects induced by radiation in silicon sensors relying on a limited number of parameters relevant for physics. To this end, extensive measurement campaigns have been recently performed on gated-diodes and MOS capacitors at Fondazione Bruno Kessler (FBK) in Italy, Hamamatsu Photonics (HPK) in Japan and Infineon Technologies (IFX) in Austria on both n-type and p-type substrates (with and without p-spray isolation implants), in order to extrapolate the relevant parameters which rule the surface damage effects. The integrated interface trap density and the oxide charge density, have been determined before and after X-ray irradiation with doses ranging from 0.05 to 100 Mrad(SiO2), for each specific foundry and technology flavor. The main guidelines of this study are the versatility and generality of the simulation approach.
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Vyšniauskas, J., K. Ikamas, D. Vizbaras, and A. Lisauskas. "Two-dimensional hydrodynamic modelling of AlGaN/GaN transistor-based THz detectors." Lithuanian Journal of Physics 63, no. 4 (2023). http://dx.doi.org/10.3952/physics.2023.63.4.4.
Full textAbstract:

 
 
 Here, we report on numerical modelling of AlGaN/GaN HEMT terahertz detectors using a two-dimensional solver based on three Boltzmann transport equation (BTE) moments and the Poisson equation. We use the Synopsys TCAD Sentaurus program package, which offers a wide material database and the possibility to include traps and polarization charges for the formation of the channel without any doping. The implications of different levels of model simplifications are addressed both analytically and numerically. We calculated the current responsivity R, to THz radiation on the drain voltage in the frequency range 0.01-3.0 THz for three AlGaN layer thicknesses d= 15, 20 and 25 nm and different gate lengths. We demonstrate that only a hydrodynamic model can reproduce the change in the sign in current responsivity at the gate voltage UG9 (R1 = 0 at UG = UG0). The energy flux factor in the energy balance equation determines this effect. For the simulated structures, we find that the noise equivalent power may be as low as 0.1 pW/VHz at 0.04 THz and 10 pW/VHz at 3.0 THz.
 
 
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Morozzi, Arianna, Francesco Moscatelli, Tommaso Croci, and Daniele Passeri. "TCAD Modeling of Surface Radiation Damage Effects: A State-Of-The-Art Review." February 2, 2021. https://doi.org/10.3389/fphy.2021.617322.
Full textAbstract:
A comprehensive numerical model which accounts for surface damage effects induced by radiation on silicon particle detectors is presented with reference to the state-of-the-art Synopsys Sentaurus Technology CAD (TCAD) tool. The overall aim of this work is to present the "Perugia 2019 Surface" damage modeling scheme, fully implemented within the TCAD environment, which effectively describes the surface damage effects induced by radiation in silicon sensors relying on a limited number of parameters relevant for physics. To this end, extensive measurement campaigns have been recently performed on gated-diodes and MOS capacitors at Fondazione Bruno Kessler (FBK) in Italy, Hamamatsu Photonics (HPK) in Japan and Infineon Technologies (IFX) in Austria on both n-type and p-type substrates (with and without p-spray isolation implants), in order to extrapolate the relevant parameters which rule the surface damage effects. The integrated interface trap density and the oxide charge density, have been determined before and after X-ray irradiation with doses ranging from 0.05 to 100 Mrad(SiO2), for each specific foundry and technology flavor. The main guidelines of this study are the versatility and generality of the simulation approach.