Relevant bibliographies by topics / SentaurusTM TCAD simulation

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'SentaurusTM TCAD simulation'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "SentaurusTM TCAD simulation"

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Boufouss, E., J. Alvarado, and D. Flandre. "Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000077–82. http://dx.doi.org/10.4071/hitec-eboufouss-ta25.

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A temperature dependence analysis of the single event transient current induced by heavy ions irradiation is performed in the range of 300K to 500K on a 1μm SOI CMOS MOSFET standard 6T-SRAM cell. The Sentaurus TCAD mixed-mode numerical simulation showed a significant impact of the temperature on the current induced by the radiation and as a result, an increase of the 6T-SRAM sensitivity upon radiation. A SOI MOSFET compact model introduced in SPICE as a Verilog-A module reproducing the single event effects was developed. This model shows a very good agreement with the TCAD simulations results but with a drastic reduction of the simulation time. Furthermore this model could be extended to other circuits simulations. This result is of importance to allow for extensive circuit design studies which cannot be carried out with TCAD physical simulations.
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Johannesson, Daniel, Muhammad Nawaz, and Hans Peter Nee. "TCAD Model Calibration of High Voltage 4H-SiC Bipolar Junction Transistors." Materials Science Forum 963 (July 2019): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.963.670.

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In this project, a Technology CAD (TCAD) model has been calibrated and verified against experimental data of a 15 kV silicon carbide (SiC) bipolar junction transistor (BJT). The device structure of the high voltage BJT has been implemented in the Synopsys Sentaurus TCAD simulation platform and design of experiment simulations have been performed to extract and fine-tune device parameters and 4H-SiC material parameters to accurately reflect the 15 kV SiC BJT experimental results. The set of calibrated TCAD parameters may serve as a base for further investigations of various SiC device design and device operation in electrical circuits.
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Dargar, Shashi Kant, J. K. Srivastava, Santosh Bharti, and Abha Nyati. "Performance Evaluation of GaN based Thin Film Transistor using TCAD Simulation." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 1 (February 1, 2017): 144. http://dx.doi.org/10.11591/ijece.v7i1.pp144-151.

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<p>As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10<sup>7 </sup>~8.3×10<sup>8</sup>, and a sub-threshold slope of 0.44V/dec. Sentaurus TCAD simulations is the tool which offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.</p>
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Jiang, Yi Fan, B. Jayant Baliga, and Alex Q. Huang. "Influence of Lateral Straggling of Implated Aluminum Ions on High Voltage 4H-SiC Device Edge Termination Design." Materials Science Forum 924 (June 2018): 361–64. http://dx.doi.org/10.4028/www.scientific.net/msf.924.361.

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This paper presents the analysis of Aluminum profile implanted into 4H-SiC with low background doping concentration. A strong lateral straggling effect was discovered with secondary electron potential contrast (SEPC) method, and analyzed by Sentaurus Monto Carlo simulations. The effect of lateral straggling was included in the edge termination design using Sentaurus TCAD simulation tool, and the results are compared with design not including the lateral straggling effect. The effect of interface charge on the electric field distribution and breakdown voltage of different 10 kV device edge termination designs was compared and analyzed.
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Kuznetsov, Maksim, Sergey Kalinin, Alexey Cherkaev, and Dmitriy Ostertak. "Investigating physical model interface in the TCAD Sentaurus environment." Transaction of Scientific Papers of the Novosibirsk State Technical University, no. 3 (November 18, 2020): 39–48. http://dx.doi.org/10.17212/2307-6879-2020-3-39-48.

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Currently, the application SDevice software package TCAD Sentaurus is a reliable tool for electrophysical simulation of silicon CMOS transistors operating in the temperature range of -60 °C – +125 °C. To adapt the modeling process to specific physical conditions of the devices, application SDevice has an extensive library of models of electrophysical parameters, in particular models of mobility or band gap energy. However, when the device operates under extreme cryogenic conditions, there is a need to rework these models using a special Physical Model Interface (PMI). The paper presents methodological features of work with PMI and results of implementation of custom parameter models for silicon devices.
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Zhu, Shunwei, Hujun Jia, Tao Li, Yibo Tong, Yuan Liang, Xingyu Wang, Tonghui Zeng, and Yintang Yang. "Novel High-Energy-Efficiency AlGaN/GaN HEMT with High Gate and Multi-Recessed Buffer." Micromachines 10, no. 7 (July 2, 2019): 444. http://dx.doi.org/10.3390/mi10070444.

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A novel AlGaN/GaN high-electron-mobility transistor (HEMT) with a high gate and a multi-recessed buffer (HGMRB) for high-energy-efficiency applications is proposed, and the mechanism of the device is investigated using technology computer aided design (TCAD) Sentaurus and advanced design system (ADS) simulations. The gate of the new structure is 5 nm higher than the barrier layer, and the buffer layer has two recessed regions in the buffer layer. The TCAD simulation results show that the maximum drain saturation current and transconductance of the HGMRB HEMT decreases slightly, but the breakdown voltage increases by 16.7%, while the gate-to-source capacitance decreases by 17%. The new structure has a better gain than the conventional HEMT. In radio frequency (RF) simulation, the results show that the HGMRB HEMT has 90.8%, 89.3%, and 84.4% power-added efficiency (PAE) at 600 MHz, 1.2 GHz, and 2.4 GHz, respectively, which ensures a large output power density. Overall, the results show that the HGMRB HEMT is a better prospect for high energy efficiency than the conventional HEMT.
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Moni, Jackuline, and T. Jaspar Vinitha Sundari. "Junctionless Tunneling Nanowire for Steep Subthreshold Slope." Advanced Science Letters 24, no. 8 (August 1, 2018): 5695–99. http://dx.doi.org/10.1166/asl.2018.12179.

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Using standardized simulations, we report a meticulous learning of the Junctionless nanowire with tunneling mechanism and the dependence of Subthreshold slope on operational parameters by varying the channel diameter, Gate length and doping concentration using Synopsys Sentaurus TCAD simulations. For the first time, Junctionless Nanowire in the company of tunneling architecture is proposed and explored. Our simulation study shows that a decrease in channel diameter and doping concentration results in higher band to band generation and steeper slope. Junctionless tunneling nanowire of diameter 10 nm, gate length of 20 nm, and uniform doping concentration of 1e19 cm−3 obtains steepest Subthreshold swing of about 8 mV/dec (point) and 52 mV/dec (average), an on/off current ratio of 1010, on current of 10−5 A/um.
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Phetchakul, Toempong, Wittaya Luanatikomkul, Chana Leepattarapongpan, E. Chaowicharat, Putapon Pengpad, and Amporn Poyai. "The Study of p-n and Schottky Junction for Magnetodiode." Advanced Materials Research 378-379 (October 2011): 663–67. http://dx.doi.org/10.4028/www.scientific.net/amr.378-379.663.

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This paper presents the simulation model of Dual Magnetodiode and Dual Schottky Magnetodiode using Sentaurus TCAD to simulate the virtual structure of magneto device and apply Hall Effect to measure magnetic field response of the device. Firstly, we use the program to simulate the magnetodiode with p-type semiconductor and aluminum anode and measure electrical properties and magnetic field sensitivity. Simulation results show that sensitivity of Dual Schottky magnetodiode is higher than that of Dual magnetodiode.
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Salemi, Arash, Hossein Elahipanah, Carl Mikael Zetterling, and Mikael Östling. "10+ kV Implantation-Free 4H-SiC PiN Diodes." Materials Science Forum 897 (May 2017): 423–26. http://dx.doi.org/10.4028/www.scientific.net/msf.897.423.

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Implantation-free mesa etched 10+ kV 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. An area-optimized junction termination extension (O-JTE) is implemented in order to achieve a high breakdown voltage. The diodes design allows a high breakdown voltage of about 19.3 kV according to simulations by Sentaurus TCAD. No breakdown voltage is recorded up to 10 kV with a very low leakage current of 0.1 μA. The current spreading within the thick drift layer is considered and a voltage drop (VF) of 8.3 V and 11.4 V are measured at 50 A/cm2 and 100 A/cm2, respectively. The differential on-resistance (Diff. Ron) of 67.7 mΩ.cm2 and 55.7 mΩ.cm2 are measured at 50 A/cm2 and 100 A/cm2, respectively.
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Salemi, Arash, Benedetto Buono, Anders Hallén, Jawad ul Hassan, Peder Bergman, Carl Mikael Zetterling, and Mikael Östling. "Fabrication and Design of 10 kV PiN Diodes Using On-Axis 4H-SiC." Materials Science Forum 778-780 (February 2014): 836–40. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.836.

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10 kV PiN diodes using on-axis 4H-SiC were designed, fabricated, and measured. A lifetime enhancement procedure was done by carbon implantation followed by high temperature annealing to increase lifetime to above 2 μs. The device simulation software Sentaurus TCAD has been used in order to optimize the diode. All fabricated diodes are fully functional and have a VFof 3.3 V at 100 A/cm2at 25°C, which was decreased to 3.0 V at 300°C.
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Dissertations / Theses on the topic "SentaurusTM TCAD simulation"

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Lale, Adem. "Architectures d'intégration mixte monolithique-hybride de cellules de commutation de puissance sur puces multi-pôles silicium et assemblages optimisés." Thesis, Toulouse 3, 2017. http://www.theses.fr/2017TOU30174/document.

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Actuellement, le module de puissance (convertisseur de puissance) standard hybride 2D est la technologie de référence qui domine le marché de la moyenne et de la forte puissance. Ce dernier se présente sous la forme d'un boitier à multi-puces discrètes. Les puces à semi-conducteur sont reliées entre elles par des faisceaux de wire-bonding (câblage par fils) pour former des cellules de commutation. La technologie d'interconnexion wire-bonding présente une grande maturité technologique, et ses modes de défaillance sont bien connus aujourd'hui. Toutefois, cette technologie est un facteur limitant en termes de performances électrique et thermomécanique, d'intégrabilité tridimensionnelle et de productivité. Ces travaux de thèse ont pour objectif de proposer et d'étudier de nouvelles architectures de convertisseurs de puissance très intégrés. Comparée à la technologie hybride, dite de référence, les architectures proposées visent à un degré d'intégration plus poussé, avec un effort d'intégration partagé et conjoint au niveau semi-conducteur (intégration monolithique) et au niveau assemblage (intégration hybride). L'intégration monolithique consiste à intégrer les interrupteurs formant les cellules de commutation dans de nouvelles architectures de puces, passant ainsi de la notion de puce dipôle à celle de macro-puce multi-pôle. L'intégration hybride repose sur le développement de nouvelles technologies de report et d'assemblage de ces macro-puces. Pour valider les trois nouvelles architectures d'intégrations proposées, la démarche a consisté dans un premier temps à étudier et valider le fonctionnement des nouvelles puces par des simulations SentaurusTM TCAD. Ensuite, les puces multi-pôles ont été réalisées en s'appuyant sur la filière IGBT disponible dans la plateforme de micro-fabrication du LAAS-CNRS. Pour finir, les puces ont été reportées sur des cartes PCB, afin de réaliser des circuits de conversions prototypes. La maille de commutation très intégrée proposée présente une inductance parasite inférieure au nanohenry, ce qui est remarquable comparée à ce qui est présenté dans l'état de l'art (env. 20 nH)
Currently, the standard 2D hybrid power module (power converter) is the reference technology for the medium and high power market. This hybrid power module is a discrete multi-chip case. The semi-conductor chips are interconnected by wire-bonding to form switching cells. The wire-bonding interconnection technology is a limiting factor in terms of electrical and thermomechanical performances, three-dimensional integrability and productivity. The aim of this thesis is to study new architectures of very integrated power converters. Compared to the so-called hybrid reference technology, the proposed architectures aim at a greater degree of integration, with an integration at both the semi-conductor level (monolithic integration) and the packaging level (hybrid integration). Monolithic integration consists in integrating switching cells into new multi-terminal macro-chip architectures. Hybrid integration consists in developing of new technologies to assemble these macro-chips. To validate the different proposed integration architectures, the first step was to study and validate the operating modes of the new chips by SentaurusTM TCAD simulations. Then, the multi-terminal chips were realized in the micro and nanotechnology platform of LAAS-CNRS laboratory. Finally, the chips were bonded on PCB substrates to realize power converter circuit prototypes. The highly integrated switching loop presents a stray inductance loop lower than one nanohenry, wich is an important improvement as compared to the values reported in literature (about 20 nH)
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Bui, Thi Thanh Huyen. "Terminaisons verticales de jonction remplies avec des couches diélectriques isolantes pour des application haute tension utilisant des composants grand-gap de forte puissance." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI061/document.

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Le développement de l’énergie renouvelable loin des zones urbaines demande le transport d'une grande quantité d’énergie sur de longues distances. Le transport d’électricité en courant continu haute tension (HVDC) présente beaucoup d’avantages par rapport à celui en courant alternatif. Dans ce contexte il est nécessaire de développer des convertisseurs de puissance constitués par des composants électroniques très haute tension, 10 à 30 kV. Si les composants en silicium ne peuvent pas atteindre ces objectifs, le carbure de silicium (SiC) se positionne comme un matériau semiconducteur alternatif prometteur. Pour supporter des tensions élevées, une région de "drift", relativement large et peu dopée constitue le cœur du composant de puissance. En pratique l’obtention d’une tension de blocage effective dépend de plusieurs facteurs et surtout de la conception d'une terminaison de jonction adaptée. Cette thèse présente une méthode pour améliorer la tenue en tension des composants en SiC basée sur l’utilisation des terminaisons de jonctions : Deep Trench Termination. Cette méthode utilise une tranchée gravée profonde en périphérie du composant, remplie avec un matériau diélectrique pour supporter l'étalement des lignes équipotentielles. La conception de la diode avec cette terminaison a été faite par simulation TCAD, avec deux niveaux de tension 3 et 20 kV. Les travaux ont pris en compte les caractéristiques du matériau, les charges à l’interface de la tranchée et les limites technologiques pour la fabrication. Ce travail a abouti sur la fabrication de démonstrateurs et leur caractérisation pour valider notre conception. Lors de la réalisation de ces structures, la gravure plasma du SiC a été optimisée dans un bâti ICP de manière à obtenir une vitesse de gravure élevée et en conservant une qualité électronique de l'état des surfaces gravées. Cette qualité est confirmée par les résultats de caractérisation obtenus avec des tenues en tension proches de celle idéale
The development of renewable energy away from urban areas requires the transmission of a large amount of energy over long distances. High Voltage Direct Current (HVDC) power transmission has many advantages over AC power transmission. In this context, it is necessary to develop power converters based on high voltage power electronic components, 10 to 30 kV. If silicon components cannot achieve these objectives, silicon carbide (SiC) is positioned as a promising alternative semiconductor material. To support high voltages, a drift region, relatively wide and lightly doped is the heart of the power component. In practice obtaining an effective blocking voltage depends on several factors and especially the design of a suitable junction termination. This thesis presents a method to improve the voltage withstand of SiC components based on the use of junction terminations: Deep Trench Termination. This method uses a trench deep etching around the periphery of the component, filled with a dielectric material to support the spreading of the equipotential lines. The design of the diode with this termination was done by TCAD simulation, with two voltage levels 3 and 20 kV. The work took into account the characteristics of the material, the interface charge of the trench and the technological limits for the fabrication. This work resulted in the fabrication of demonstrators and their characterization to validate the design. During the production of these structures, plasma etching of SiC has been optimized in an ICP reactor so as to obtain a high etching rate and maintaining an electronic quality of the state of etched surfaces. This quality is confirmed by the results of characterization obtained with blocking voltage close to the ideal one
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Legal, Julie. "Intégration des fonctions de protection avec les dispositifs IGBT." Phd thesis, Université Paul Sabatier - Toulouse III, 2010. http://tel.archives-ouvertes.fr/tel-00564270.

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La fiabilité et la disponibilité des systèmes de gestion de l'énergie sont les conditions de base pour la généralisation de solutions électriques dans de nombreuses applications. Les dispositifs de puissance doivent être performants non seulement en régime normal, mais aussi en régimes extrêmes, par exemple lors des courts-circuits. Pour cela, les interrupteurs de puissance sont associés de façon discrète à des systèmes de détection et de protection. Une solution pour améliorer la fiabilité des dispositifs consiste à intégrer monolithiquement, au sein d'une même puce, l'interrupteur et les fonctions de détection et de protection. Ces dispositifs intégrés exploitent les interactions électriques qui apparaissent dans la puce pour détecter la défaillance et ainsi la stopper. L'interrupteur de puissance est ainsi protégé et se remet en conduction une fois la défaillance corrigée. Les composants de puissance seront ainsi capables de se protéger lors d'une défaillance. L'objectif de cette thèse est de proposer des solutions d'intégration de fonctions de protection et de diagnostic rapprochées avec les dispositifs IGBT afin d'augmenter la fiabilité et la disponibilité des systèmes de puissance. Les fonctions de protection sur lesquelles nous nous sommes focalisés sont le miroir de courant ("Sense") et le capteur d'anode ("Capteur de Tension d'Anode") pour détecter les courts-circuits. Ces deux capteurs ont été étudiés à l'aide de simulation 2D puis réalisés technologiquement. Un circuit de détection et de protection des IGBT contre les courts-circuits, comprenant le capteur de tension d'anode intégré monolithiquement, est proposé et simulé. Les tests électriques des capteurs en mode statique permettent de mieux comprendre leur comportement. Enfin, l'interrupteur IGBT associé à ses fonctions de détection et de protection est testé de manière discrète dans un circuit de commutation en condition de court-circuit afin de valider le fonctionnement.
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Baccar, El Boubkari Fedia. "Évaluation des mécanismes de défaillance et de la fiabilité d’une nouvelle terminaison haute tension : approche expérimentale et modélisation associée." Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0266/document.

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Ces travaux s’intègrent dans le projet de recherche SUPERSWITCH dans lequel des solutions alternatives à l’IGBT, utilisées dans les convertisseurs de puissance dans la gamme des tenues en tension 600-1200 V, sont envisagées. Les nouvelles structures du transistor MOS basées sur le principe de Super-Jonction tel que le transistor DT-SJMOSFET et sa terminaison originale, la « Deep Trench Termination » se propose comme alternative aux IGBT. Dans ce contexte, cette thèse se focalise sur la caractérisation de la robustesse de la terminaison DT2 adapté à une diode plane. Après avoir effectué un état de l’art sur les composants de puissances à semi-conducteur unidirectionnels en tension, les terminaisons des composants de puissance et la fiabilité des modules de puissance, un véhicule de test a été conçu en vue de réaliser les différents essais de vieillissement accéléré et suivi électrique. La fiabilité de la terminaison DT2 a été évaluée par des essais expérimentaux et des simulations numériques, dont une méthodologie innovante a été proposée. Au final de nouvelles structures ont été proposées pour limiter les problèmes de délaminage et de charges aux interfaces mis en avant dans notre étude
This work is a part of the research project SUPERSWITCH in which alternatives solutions to the IGBT, are investigated. This solution was used IGBT in power converters in the 600-1200 V breakdown voltage range. The new MOSFET structures based on the super-junction, such as the DT-SJMOSFET and its "Deep Trench Termination", is proposed as an alternative to IGBT. In this context, this thesis focuses on the robustness characterization of the DT2 termination adapted to a planar diode. After a state of the art on unidirectional voltage power components, the power components termination, and power modules reliability, a test vehicle has been designed in order to carry out different accelerated ageing tests and electrical monitoring. The reliability of DT2 termination was evaluated by experimental tests and numerical simulations. An innovative modeling methodology has been proposed. Finally, new structures have been proposed to limit the delamination failure mechanisms and interface charges problems highlighted in this thesis
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Book chapters on the topic "SentaurusTM TCAD simulation"

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Wu, Yung-Chun, and Yi-Ruei Jhan. "Introduction of Synopsys Sentaurus TCAD Simulation." In 3D TCAD Simulation for CMOS Nanoeletronic Devices, 1–17. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-3066-6_1.

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"Simulation of JLFETS Using Sentaurus TCAD." In Junctionless Field-Effect Transistors, 385–438. Wiley, 2019. http://dx.doi.org/10.1002/9781119523543.ch9.

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Conference papers on the topic "SentaurusTM TCAD simulation"

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Li, Yonghong, Chaohui He, and Chunmei Xia. "Simulation of Heavy Ion Source-Drain Penetration Effect in SOI MOS and Bulk MOS." In 18th International Conference on Nuclear Engineering. ASMEDC, 2010. http://dx.doi.org/10.1115/icone18-29782.

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The Single Event Effects (SEE) of Silicon On Insulator (SOI) and bulk-silicon NMOS are simulated using the SENTAURUS-TCAD device simulator. The Source-Drain Penetration Effect, which is caused by a heavy ion, was shown. It is proved that when the feature size of device become less than a certain scale, both Direct Channel Effect and Indirect Channel Effect occur. By comparing the distributions of equipotential lines in the MOSFETs’ channels of the different feature size devices during the ion strikes indirectly, the Source-Drain-Penetration Effect occurs more evidently when the device feature size is getting smaller.
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Wozny, Janusz, Jacek Podgorski, Ewa Raj, and Zbigniew Lisik. "Good Practices of Electrothermal Simulation of p-n Structures Using Sentaurus TCAD." In 2019 IEEE 15th International Conference on the Experience of Designing and Application of CAD Systems (CADSM). IEEE, 2019. http://dx.doi.org/10.1109/cadsm.2019.8779329.

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Trinh, Cham Thi, Amran Al-Ashouri, Lars Korte, Daniel Amkreutz, Steve Albrecht, Bernd Stannowski, and Rutger Schlatmann. "Electrical and optical simulation of perovskite/silicon tandem solar cells using Tcad-Sentaurus." In 2021 IEEE 48th Photovoltaic Specialists Conference (PVSC). IEEE, 2021. http://dx.doi.org/10.1109/pvsc43889.2021.9519104.

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Ануфриев, Владимир, Vladimir Anufriev, Антон Козлов, and Anton Kozlov. "INVESTIGATION OF THE INTEGRAL MAGNETO SENSITIVITY HALL SENSOR WITH PN JUNCTIONS BY THE SENTAURUS TCAD NUMERICAL MODELING." In CAD/EDA/Simulation in Modern Electronics. Bryansk State Technical University, 2018. http://dx.doi.org/10.30987/conferencearticle_5c19e5de650781.53271413.

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Baccar, F., H. Arbess, L. Theolier, S. Azzopardi, and E. Woirgard. "New simulation method for Deep Trench Termination diode (DT2) using mixed-mode TCAD sentaurus." In 2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE). IEEE, 2015. http://dx.doi.org/10.1109/eurosime.2015.7103122.

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Kara, Dogacan, and F. Nazli Donmezer Akgun. "Electrothermal Analysis of the Field-Plated AlGaN/GaN HEMTs With SiO2 Passivation." In ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2017 Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/ipack2017-74125.

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AlGaN/GaN high electron mobility transistors (HEMTs) are widely used in high frequency and power applications of the space and military industries due to their high RF power densities. When operated in full capacity, reliability of GaN HEMTs drop significantly due to device degradation, electron collapse phenomena, and concentrated heating effects. Although significant research has been done to investigate the effects of passivation, field-plates on the device degradation and the electron collapse separately, combined electrothermal analysis of the field-plates and the SiO2 passivation on GaN HEMTs has not been performed from the perspective of device reliability. For this purpose, electrothermal simulations of the field-plated and non-field-plated devices with different SiO2 passivation thicknesses are performed using Sentaurus TCAD to obtain the electrical field distribution and Joule heating caused temperature distribution in operating devices. Using these results, electrical and thermal effects of the field-plates on the devices with different SiO2 passivation thicknesses are analyzed to obtain the most effective and reliable operating conditions.
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