Journal articles: 'SentaurusTM TCAD simulation'

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Boufouss, E., J. Alvarado, and D. Flandre. "Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000077–82. http://dx.doi.org/10.4071/hitec-eboufouss-ta25.

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A temperature dependence analysis of the single event transient current induced by heavy ions irradiation is performed in the range of 300K to 500K on a 1μm SOI CMOS MOSFET standard 6T-SRAM cell. The Sentaurus TCAD mixed-mode numerical simulation showed a significant impact of the temperature on the current induced by the radiation and as a result, an increase of the 6T-SRAM sensitivity upon radiation. A SOI MOSFET compact model introduced in SPICE as a Verilog-A module reproducing the single event effects was developed. This model shows a very good agreement with the TCAD simulations results but with a drastic reduction of the simulation time. Furthermore this model could be extended to other circuits simulations. This result is of importance to allow for extensive circuit design studies which cannot be carried out with TCAD physical simulations.

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Johannesson, Daniel, Muhammad Nawaz, and Hans Peter Nee. "TCAD Model Calibration of High Voltage 4H-SiC Bipolar Junction Transistors." Materials Science Forum 963 (July 2019): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.963.670.

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In this project, a Technology CAD (TCAD) model has been calibrated and verified against experimental data of a 15 kV silicon carbide (SiC) bipolar junction transistor (BJT). The device structure of the high voltage BJT has been implemented in the Synopsys Sentaurus TCAD simulation platform and design of experiment simulations have been performed to extract and fine-tune device parameters and 4H-SiC material parameters to accurately reflect the 15 kV SiC BJT experimental results. The set of calibrated TCAD parameters may serve as a base for further investigations of various SiC device design and device operation in electrical circuits.

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Dargar, Shashi Kant, J. K. Srivastava, Santosh Bharti, and Abha Nyati. "Performance Evaluation of GaN based Thin Film Transistor using TCAD Simulation." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 1 (February 1, 2017): 144. http://dx.doi.org/10.11591/ijece.v7i1.pp144-151.

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As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×107 ~8.3×108, and a sub-threshold slope of 0.44V/dec. Sentaurus TCAD simulations is the tool which offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.

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Jiang, Yi Fan, B. Jayant Baliga, and Alex Q. Huang. "Influence of Lateral Straggling of Implated Aluminum Ions on High Voltage 4H-SiC Device Edge Termination Design." Materials Science Forum 924 (June 2018): 361–64. http://dx.doi.org/10.4028/www.scientific.net/msf.924.361.

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This paper presents the analysis of Aluminum profile implanted into 4H-SiC with low background doping concentration. A strong lateral straggling effect was discovered with secondary electron potential contrast (SEPC) method, and analyzed by Sentaurus Monto Carlo simulations. The effect of lateral straggling was included in the edge termination design using Sentaurus TCAD simulation tool, and the results are compared with design not including the lateral straggling effect. The effect of interface charge on the electric field distribution and breakdown voltage of different 10 kV device edge termination designs was compared and analyzed.

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Kuznetsov, Maksim, Sergey Kalinin, Alexey Cherkaev, and Dmitriy Ostertak. "Investigating physical model interface in the TCAD Sentaurus environment." Transaction of Scientific Papers of the Novosibirsk State Technical University, no. 3 (November 18, 2020): 39–48. http://dx.doi.org/10.17212/2307-6879-2020-3-39-48.

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Currently, the application SDevice software package TCAD Sentaurus is a reliable tool for electrophysical simulation of silicon CMOS transistors operating in the temperature range of -60 °C – +125 °C. To adapt the modeling process to specific physical conditions of the devices, application SDevice has an extensive library of models of electrophysical parameters, in particular models of mobility or band gap energy. However, when the device operates under extreme cryogenic conditions, there is a need to rework these models using a special Physical Model Interface (PMI). The paper presents methodological features of work with PMI and results of implementation of custom parameter models for silicon devices.

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Zhu, Shunwei, Hujun Jia, Tao Li, Yibo Tong, Yuan Liang, Xingyu Wang, Tonghui Zeng, and Yintang Yang. "Novel High-Energy-Efficiency AlGaN/GaN HEMT with High Gate and Multi-Recessed Buffer." Micromachines 10, no. 7 (July 2, 2019): 444. http://dx.doi.org/10.3390/mi10070444.

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A novel AlGaN/GaN high-electron-mobility transistor (HEMT) with a high gate and a multi-recessed buffer (HGMRB) for high-energy-efficiency applications is proposed, and the mechanism of the device is investigated using technology computer aided design (TCAD) Sentaurus and advanced design system (ADS) simulations. The gate of the new structure is 5 nm higher than the barrier layer, and the buffer layer has two recessed regions in the buffer layer. The TCAD simulation results show that the maximum drain saturation current and transconductance of the HGMRB HEMT decreases slightly, but the breakdown voltage increases by 16.7%, while the gate-to-source capacitance decreases by 17%. The new structure has a better gain than the conventional HEMT. In radio frequency (RF) simulation, the results show that the HGMRB HEMT has 90.8%, 89.3%, and 84.4% power-added efficiency (PAE) at 600 MHz, 1.2 GHz, and 2.4 GHz, respectively, which ensures a large output power density. Overall, the results show that the HGMRB HEMT is a better prospect for high energy efficiency than the conventional HEMT.

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Moni, Jackuline, and T. Jaspar Vinitha Sundari. "Junctionless Tunneling Nanowire for Steep Subthreshold Slope." Advanced Science Letters 24, no. 8 (August 1, 2018): 5695–99. http://dx.doi.org/10.1166/asl.2018.12179.

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Using standardized simulations, we report a meticulous learning of the Junctionless nanowire with tunneling mechanism and the dependence of Subthreshold slope on operational parameters by varying the channel diameter, Gate length and doping concentration using Synopsys Sentaurus TCAD simulations. For the first time, Junctionless Nanowire in the company of tunneling architecture is proposed and explored. Our simulation study shows that a decrease in channel diameter and doping concentration results in higher band to band generation and steeper slope. Junctionless tunneling nanowire of diameter 10 nm, gate length of 20 nm, and uniform doping concentration of 1e19 cm−3 obtains steepest Subthreshold swing of about 8 mV/dec (point) and 52 mV/dec (average), an on/off current ratio of 1010, on current of 10−5 A/um.

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Phetchakul, Toempong, Wittaya Luanatikomkul, Chana Leepattarapongpan, E. Chaowicharat, Putapon Pengpad, and Amporn Poyai. "The Study of p-n and Schottky Junction for Magnetodiode." Advanced Materials Research 378-379 (October 2011): 663–67. http://dx.doi.org/10.4028/www.scientific.net/amr.378-379.663.

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This paper presents the simulation model of Dual Magnetodiode and Dual Schottky Magnetodiode using Sentaurus TCAD to simulate the virtual structure of magneto device and apply Hall Effect to measure magnetic field response of the device. Firstly, we use the program to simulate the magnetodiode with p-type semiconductor and aluminum anode and measure electrical properties and magnetic field sensitivity. Simulation results show that sensitivity of Dual Schottky magnetodiode is higher than that of Dual magnetodiode.

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Salemi, Arash, Hossein Elahipanah, Carl Mikael Zetterling, and Mikael Östling. "10+ kV Implantation-Free 4H-SiC PiN Diodes." Materials Science Forum 897 (May 2017): 423–26. http://dx.doi.org/10.4028/www.scientific.net/msf.897.423.

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Implantation-free mesa etched 10+ kV 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. An area-optimized junction termination extension (O-JTE) is implemented in order to achieve a high breakdown voltage. The diodes design allows a high breakdown voltage of about 19.3 kV according to simulations by Sentaurus TCAD. No breakdown voltage is recorded up to 10 kV with a very low leakage current of 0.1 μA. The current spreading within the thick drift layer is considered and a voltage drop (VF) of 8.3 V and 11.4 V are measured at 50 A/cm2 and 100 A/cm2, respectively. The differential on-resistance (Diff. Ron) of 67.7 mΩ.cm2 and 55.7 mΩ.cm2 are measured at 50 A/cm2 and 100 A/cm2, respectively.

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Salemi, Arash, Benedetto Buono, Anders Hallén, Jawad ul Hassan, Peder Bergman, Carl Mikael Zetterling, and Mikael Östling. "Fabrication and Design of 10 kV PiN Diodes Using On-Axis 4H-SiC." Materials Science Forum 778-780 (February 2014): 836–40. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.836.

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10 kV PiN diodes using on-axis 4H-SiC were designed, fabricated, and measured. A lifetime enhancement procedure was done by carbon implantation followed by high temperature annealing to increase lifetime to above 2 μs. The device simulation software Sentaurus TCAD has been used in order to optimize the diode. All fabricated diodes are fully functional and have a VFof 3.3 V at 100 A/cm2at 25°C, which was decreased to 3.0 V at 300°C.

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Patil, Kalawati, and B. K. Mishra. "Dielectric Dependent Absorption Characteristics in CNFET Infrared Phototransistor." International Journal of Engineering and Technologies 19 (December 2020): 11–21. http://dx.doi.org/10.18052/www.scipress.com/ijet.19.11.

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In future infrared photodetectors, single-walled carbon nanotubes (SWCNTs) are considered as potential candidates due to their band gap, high absorption coefficient (104 - 105 cm −1), high charge carrier mobility and ease of processability. The SWCNT based Field Effect Transistors (CNFETs) are being seriously considered for applications in optoelectronics. In the proposed work optically controlled back gated CNFET is modeled in Sentaurus TCAD to observe the impact of high dielectric oxides on its photoabsorption. The model is based on analytical approximations and parameters extracted from quantum mechanical simulations of the device and depending on the nanotube diameter and the different gate oxide materials. A small deviation in SWCNT chirality shows significant change (more than 50 %) in channel current. Transfer characteristics of the device are analyzed under dark and illuminated conditions. CNFET integrated with HfO2 dielectrics exhibits superior performance with a significant rise in photocurrent current. Precise two dimensional TCAD simulation results and visual figures affirm that the ON state performance of CNFET has significant dependency on the dielectric strength as well as width of the gate oxide and its application in enhancing the performance of carbon nanotube based infrared photo detectors.

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Rodríguez, Raúl, Benito González, Javier García, Gaetan Toulon, Frédéric Morancho, and Antonio Núñez. "DC Gate Leakage Current Model Accounting for Trapping Effects in AlGaN/GaN HEMTs." Electronics 7, no. 10 (September 21, 2018): 210. http://dx.doi.org/10.3390/electronics7100210.

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A DC leakage current model accounting for trapping effects under the gate of AlGaN/GaN HEMTs on silicon has been developed. Based on TCAD numerical simulations (with Sentaurus Device), non-local tunneling under the Schottky gate is necessary to reproduce the measured transfer characteristics in a subthreshold regime. Once the trap concentration and distribution are determined in the device, the resulting gate leakage current is modeled making use of Verilog-A, for typical operation regimes.

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Jaikumar, M. G., and Shreepad Karmalkar. "Calibration of Mobility and Interface Trap Parameters for High Temperature TCAD Simulation of 4H-SiC VDMOSFETs." Materials Science Forum 717-720 (May 2012): 1101–4. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1101.

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4H-Silicon Carbide VDMOSFET is simulated using the Sentaurus TCAD package of Synopsys. The simulator is calibrated against measured data for a wide range of bias conditions and temperature. Material parameters of 4H-SiC are taken from literature and used in the available silicon models of the simulator. The empirical parameters are adjusted to get a good fit between the simulated curves and measured data. The simulation incorporates the bias and temperature dependence of important physical mechanisms like interface trap density, coulombic interface trap scattering, surface roughness scattering and velocity saturation.

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Palomo, F. R., P. Fernández-Martínez, J. M. Mogollón, S. Hidalgo, M. A. Aguirre, D. Flores, I. López-Calle, and J. A. de Agapito. "Simulation of femtosecond pulsed laser effects on MOS electronics using TCAD Sentaurus customized models." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 23, no. 4-5 (January 19, 2010): 379–99. http://dx.doi.org/10.1002/jnm.736.

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Palacios A., César, Noemi Guerra, Marco Guevara, and María José López. "TCAD 2D numerical simulations for increasing efficiency of AlGaAs – GaAs Solar Cells." I+D Tecnológico 14, no. 2 (December 14, 2018): 96–107. http://dx.doi.org/10.33412/idt.v14.2.2078.

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The performance of solar cells has improved quickly in recent years, the latest research focuses on thin cells, multijunction cells, solar cells of the group III-V compounds, Tandem cells, etc. In the present work, numerical simulations are developed, using SENTAURUS TCAD as a tool, in order to obtain a solar cell model based on Galium Arsenide (GaAs). This solar cell corresponds to the so-called "Thin Films" due to the fact that can make layers thinner than we would have if we work with conventional semiconductors, such as; Silicon or Germanium; thus opening the possibility of placing the cell as a top layer within a tandem solar cell configuration with compounds of group III-V. That is why two types of simulations are performed with respect to the contact of the rear contact; one corresponds to the cell with a lower contact equal to the length of the cell and the other with a small contact of 5 μm. In addition, the cell undergoes an optimization process by modifying the geometry and doping of the layers that comprise it, in order to improve its performance. To achieve this objective, the initial conditions and the appropriate simulation parameters must be determined, which have been selected and corroborated with the literature, allowing us to arrive at coherent results and optimal models of solar cell design through numerical simulations.

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Adak, Sarosij, and Sanjit Kumar Swain. "Impact of High-K Dielectric Materials on Performance Analysis of Underlap In0.17Al0.83N/GaN DG-MOSHEMTs." Nano 14, no. 05 (May 2019): 1950060. http://dx.doi.org/10.1142/s1793292019500607.

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This work systematically investigated the effect of high-[Formula: see text] oxide materials on the performance of InAlN/GaN heterostructure underlap double gate (DG) MOS-HEMTs by considering 2D Sentaurus TCAD simulation. During the course of simulation, hydrodynamic mobility model was implemented and the obtained results were used for validating the model with the previously published experimental results. Different device performance parameters are thoroughly studied for different high-[Formula: see text] oxide materials by performing extensive simulations. It is verified that short channel effects (SCEs), key analog and RF figures of merits parameters and [Formula: see text]th improved with an increase in the value of high-[Formula: see text] oxide material. Moreover, it is also revealed that there is a significant growth in the values of key analog and RF figures of merits with respect to high-[Formula: see text] values. This analysis suggested that use of a suitable value of high-[Formula: see text]-valued oxide material in InAlN/GaN heterostructure underlap DG MOS-HEMTs can be one of the alternatives for future high speed and microwave applications.

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Koptev, N. S., and A. A. Pugachev. "TCAD-ASSISTED TECHNIQUE FOR DETERMINING THE PARAMETERS OF MICROLENSES USED IN PHOTOSENSITIVE CCD VLSI." Electronic engineering Series 2 Semiconductor devices 257, no. 2 (2020): 28–36. http://dx.doi.org/10.36845/2073-8250-2020-257-2-28-36.

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In this paper we introduce the simulation technique for photosensitive cell with CCD VLSI microlens with interline transfer. A microlens enhances the photosensitivity of the cell and reduces image blur. The technique is based on the calculation and comparison of the volumetric photogeneration rate integrals of different areas of the photocell, where generated charge carriers are collected and transferred. This technique does not require simulation of the full frame accumulation cycle of the cell, significantly reducing the time of simulation and enabling the evaluation of many design options for microlenses. The technique is implemented in the Sentaurus TCAD (by Synopsys). In the paper we present the results of simulation made for cells with various microlenses. The proposed technique can also be used for the optimization of microlenses of CMOS photodiode VLSI photocells.

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Khalid, Muhammad, Waseem Raza, Saira Riaz, and Shahzad Naseem. "Simulation and Analysis of Static and Dynamic Performance of Normally-off TIVJFET Using Sentaurus TCAD." Materials Today: Proceedings 2, no. 10 (2015): 5720–25. http://dx.doi.org/10.1016/j.matpr.2015.11.117.

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Dehzangi, Arash, Farhad Larki, Sawal Hamid Md Ali, Sabar Derita Hutagalung, Md Shabiul Islam, Mohd Nizar Hamidon, Susthitha Menon, Azman Jalar, Jumiah Hassan, and Burhanuddin Yeop Majlis. "Study of the side gate junctionless transistor in accumulation region." Microelectronics International 33, no. 2 (May 3, 2016): 61–67. http://dx.doi.org/10.1108/mi-03-2015-0027.

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Purpose The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition. Design/methodology/approach The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 μm for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley–Read–Hall (SRH) carrier recombination/generation. Findings We have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components’ variation, carrier’s concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers’ movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime. Originality/value The proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results.

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Yang, Shao-Ming, Gene Sheu, Tzu Chieh Lee, Ting Yao Chien, Chieh Chih Wu, and Yun Jung Lin. "Design of a Low on Resistance High Voltage (120V) Novel 3D NLDMOS with Side Isolation Based on 0.35um BCD Process Technology." MATEC Web of Conferences 201 (2018): 02004. http://dx.doi.org/10.1051/matecconf/201820102004.

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High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and successfully simulated. We implemented in a conventional 0.35um BCDMOS process to present of a novel high side 120V LDMOS have reduced surface field (RESURF) and Liner p-top structure with side isolation technology. The device has been research to achieve a benchmark specific on-resistance of 189 mΩ-mm2 while maintaining horizontal breakdown voltage and vertical isolation voltage both to target breakdown voltage of 120V. In ESOA, we also proposed a better performance of both device without kirk effect.

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Danilenko, Alexander A., Anton V. Strygin, Nikolay I. Mikhailov, Vadim V. Perepelovsky, Yaroslav N. Panichev, Vladislav V. Marochkin, and Vladimir L. Ivanov. "PROGRAMMING 2-BIT PIN DIODE IN SYNOPSYS TCAD." Journal of the Russian Universities. Radioelectronics, no. 5 (December 6, 2018): 51–59. http://dx.doi.org/10.32603/1993-8985-2018-21-5-51-59.

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The article is devoted to the modeling of a two-bit pin-diode. The possibility of programming opening time of the device based on the pin-diode is shown. The design consisting of a pin diode and two floating gates on the surface of i-region is considered. The addition of electrodes to the surface of the i-region makes it possible to regulate the concentration of electrons and holes within the larger limits in compare with the single-gate structure creating enriched and depleted are-as in the structure. Programming is carried out by applying the appropriate voltage to the control electrodes of the floating gates. It is shown that the charge generated on the floating gate changes characteristics of the i-region of the pin diode.The key elements of complex simulation of the two-gate pin diode are simulation of charge accumulation mechanism on the floating gate, simulation of pin-diode opening time and calibration of numerical model. Simulation is performed in Synopsys Sentaurus TCAD. Physical models describing traps and their parameters, particle tunneling, transport phenomena in dielectrics and amorphous films are used in simulation. As a result of modeling, the opening time dependences on size, floating gate location and floating gate charge magnitude are obtained.It is shown that the pin-diode 2-gate structures allow to change the opening time in a wider range than the single-gate ones. To program a large range of pin-diode opening times, it is 2 gate structure that is advisable to use. The obtained results indicate that it is possible to implement a two-bit programming pin-diode and expand its functionality.

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Wang, You, Yu Mao, Qizheng Ji, Ming Yang, Zhaonian Yang, and Hai Lin. "Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET." Electronics 10, no. 4 (February 11, 2021): 454. http://dx.doi.org/10.3390/electronics10040454.

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Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

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Li, Han, Chen Wang, Lin Chen, Hao Zhu, and Qingqing Sun. "A Semi-Floating Gate Memory Based on SOI Substrate by TCAD Simulation." Electronics 8, no. 10 (October 21, 2019): 1198. http://dx.doi.org/10.3390/electronics8101198.

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Over the past decade, the dimensional scaling of semiconductor electronic devices has been facing fundamental and physical challenges, and there is currently an urgent need to increase the ability of dynamic random-access memory (DRAM). A semi-floating gate (SFG) transistor has been proposed as a capacitor-less memory with faster speed and higher density as compared with the conventional one-transistor one-capacitor (1T1C) DRAM technology. The integration of SFG-based memory on the silicon-on-insulator (SOI) substrate has been demonstrated in this work by using the Sentaurus Technology Computer-Aided Design (TCAD) simulation. An enhancement in retention characteristics, anti-disturbance ability, and fast writing capability, have been illustrated. The device exhibits a low operation voltage, a large threshold voltage window of ~3 V, and an ultra-fast writing of 4 ns. In addition, the SOI-based memory has shown a much-improved anti-irradiation capability compared to the devices based on bulk silicon, which makes it much more attractive in broader applications.

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Nipoti, Roberta, Giovanna Sozzi, Maurizio Puzzanghera, and Roberto Menozzi. "Al+ implanted vertical 4H-SiC p-i-n diodes: experimental and simulated forward current-voltage characteristics." MRS Advances 1, no. 54 (2016): 3637–42. http://dx.doi.org/10.1557/adv.2016.315.

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ABSTRACT The temperature dependence of the forward and reverse current voltage characteristics of circular Al+ implanted 4H-SiC p-i-n vertical diodes of various diameters, post implantation annealed at 1950 °C/5 min, have been used to obtain the thermal activation energies of the defects responsible of the generation and the recombination currents, as well as the area and the periphery current component of the current voltage characteristics. The former have values compatible with those of the traps associated to the carbon vacancy defect in 4H-SiC. The hypothesis that only these traps may justify the trend of the current voltage characteristics of the studied diodes has been tested by simulations in a Synopsys Sentaurus TCAD suite.

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Gan, Lu-Rong, Ya-Rong Wang, Lin Chen, Hao Zhu, and Qing-Qing Sun. "A Floating Gate Memory with U-Shape Recessed Channel for Neuromorphic Computing and MCU Applications." Micromachines 10, no. 9 (August 23, 2019): 558. http://dx.doi.org/10.3390/mi10090558.

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We have simulated a U-shape recessed channel floating gate memory by Sentaurus TCAD tools. Since the floating gate (FG) is vertically placed between source (S) and drain (D), and control gate (CG) and HfO2 high-k dielectric extend above source and drain, the integrated density can be well improved, while the erasing and programming speed of the device are respectively decreased to 75 ns and 50 ns. In addition, comprehensive synaptic abilities including long-term potentiation (LTP) and long-term depression (LTD) are demonstrated in our U-shape recessed channel FG memory, highly resembling the biological synapses. These simulation results show that our device has the potential to be well used as embedded memory in neuromorphic computing and MCU (Micro Controller Unit) applications.

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Wang, Ying, Chan Shan, Wei Piao, Xing-ji Li, Jian-qun Yang, Fei Cao, and Cheng-hao Yu. "3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance." Micromachines 9, no. 12 (December 14, 2018): 659. http://dx.doi.org/10.3390/mi9120659.

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In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench isolation (STI) of 3.5 × 1012 cm−2. Moreover, it has the advantages of a small footprint, no limitation in W/L design, and a small gate capacitance compared with the enclosed gate layout. Beside the Z gate layout, a non-radiation-hardened single gate layout and a radiation-hardened enclosed gate layout are simulated using the Sentaurus 3D technology computer-aided design (TCAD) software. First, the transfer characteristics curves (Id-Vg) curves of the three layouts are compared to verify the radiation tolerance characteristic of the Z gate layout; then, the threshold voltage and the leakage current of the three layouts are extracted to compare their TID responses. Lastly, the threshold voltage shift and the leakage current increment at different radiation doses for the three layouts are presented and analyzed.

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Choi, Yejoo, Jinwoong Lee, Jaehyuk Lim, Seungjun Moon, and Changhwan Shin. "Impact of Process-Induced Variations on Negative Capacitance Junctionless Nanowire FET." Electronics 10, no. 16 (August 7, 2021): 1899. http://dx.doi.org/10.3390/electronics10161899.

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In this study, the impact of the negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated and compared to those of the baseline junctionless nanowire FET (JL-NWFET) in both linear (Vds = 0.05 V) and saturation (Vds = 0.5 V) modes. Sentaurus TCAD and MATLAB were used for the simulation of the baseline JL-NWFET and negative capacitance JL-NWFET (NC-JL-NWFET). Owing to the NC effect, the NC-JL-NWFET showed less variation in terms of device performance, such as σ[Vt], σ[SS], σ[Ion/Ioff], σ[Vt]/µ[Vt], σ[SS]/µ[SS], and σ[Ion/Ioff]/µ[Ion/Ioff], and enhanced device performance, which implies that the NC effect can successfully control the variation-induced degradation.

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Adak, Sarosij, Sanjit Kumar Swain, Hemant Pardeshi, Hafizur Rahaman, and Chandan Kumar Sarkar. "Effect of Barrier Thickness on Linearity of Underlap AlInN/GaN DG-MOSHEMTs." Nano 12, no. 01 (January 2017): 1750009. http://dx.doi.org/10.1142/s1793292017500096.

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In this proposed work, an extensive study on the linearity performance of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) has been analyzed using 2D Sentaurus TCAD simulation. Specifically a brief comparison is made on the linearity and intermodulation distortion characteristics of the proposed device due to variation of barrier layer thickness from 2 nm to 6 nm. Various parameters such as transconductance ([Formula: see text], second-order transconductance ([Formula: see text]), third-order transconductance ([Formula: see text]), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3) and third-order intermodulation distortion (IMD3) of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) are discussed. The simulated results obtained confirms that by careful optimization of barrier layer thickness linearity characteristics of this proposed device can be improved, which can be suitable for analog and circuit applications.

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Zhu, Shunwei, Hujun Jia, Xingyu Wang, Yuan Liang, Yibo Tong, Tao Li, and Yintang Yang. "Improved MRD 4H-SiC MESFET with High Power Added Efficiency." Micromachines 10, no. 7 (July 17, 2019): 479. http://dx.doi.org/10.3390/mi10070479.

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An improved multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (IMRD 4H-SiC MESFET) with high power added efficiency is proposed and studied by co-simulation of advanced design system (ADS) and technology computer aided design (TCAD) Sentaurus software in this paper. Based on multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (MRD 4H-SiC MESFET), the recessed area of MRD MESFET on both sides of the gate is optimized, the direct current (DC), radio frequency (RF) parameters and efficiency of the device is balanced, and the IMRD MESFET with a best power-added efficiency (PAE) is finally obtained. The results show that the PAE of the IMRD MESFET is 68.33%, which is 28.66% higher than the MRD MESFET, and DC and RF performance have not dropped significantly. Compared with the MRD MESFET, the IMRD MESFET has a broader prospect in the field of microwave radio frequency.

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Nguyen, Thi Thanh Huyen, Mihai Lazar, Jean Louis Augé, Hervé Morel, Luong Viet Phung, and Dominique Planson. "Vertical Termination Filled with Adequate Dielectric for SiC Devices in HVDC Applications." Materials Science Forum 858 (May 2016): 982–85. http://dx.doi.org/10.4028/www.scientific.net/msf.858.982.

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Recently, thanks to the advancement in SiC process technology, the deep trench termination (DT2) technique becomes an appropriate choice for future high voltage SiC power device. This technique termination is based on the use of a wide and deep trench, which is filled by a dielectric and associated with a field plate. DT2 technique increases the breakdown voltage (VBR) to a value near to the ideal one that can be obtained in a plan case; and at the same time, reduces drastically the chip area comparing to the previous conventional techniques. In this work, the DT2 used for a 3 kV 4H-SiC bipolar vertical diode is presented. Simulations using TCAD SENTAURUS software show that a maximum breakdown voltage of 3286 V at room temperature can be achieved with a deep trench of 20μm corresponding to 98 % of a parallel plane breakdown voltage for the drift layer of 18 μm. Those simulations also point out the important impact of the structure of the trench; the dielectric critical electric filled (Ec), the permittivity (εr) of the dielectric filled, etching defects as microtrench, fixed charges at the interfaces...on the VBR of power device.

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Chakraborty, Chaitali, and Chayanika Bose. "Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures." Journal of Advanced Dielectrics 06, no. 01 (March 2016): 1650001. http://dx.doi.org/10.1142/s2010135x16500016.

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The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal–oxide–semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si[Formula: see text]substrate interface than to SiO2/Al–gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due to charging of the dielectric in the presence of NCs. Higher breakdown voltage and smaller leakage current are also obtained in the case of dual NC-layered MOS device. A new phenomenon of smearing out of the capacitance–voltage curve is observed in the presence of dual NC layer indicating generation of interface traps. An internal electric field developed between these two charged NC layers is expected to generate such interface traps at the SiO2/Si interface.

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Ke, Haotao, Yifan Jiang, Adam J. Morgan, and Douglas C. Hopkins. "Investigation of Package Effects on the Edge Termination E-Field for HV WBG Power Semiconductors." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000224–30. http://dx.doi.org/10.4071/isom-2017-wa32_092.

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Abstract The edge termination of a power semiconductor is defined as the spatial junction terminations around the edges of the power devices. Guard rings are used to contour the internal depletion regions and E-fields as they terminate at the edge termination, i.e. the intersection of the depletion regions and the wafer saw line where the crystal damage is located. Since there is no specific package for WBG power devices, wire bonds are still widely used to interconnect to the topside metal pads of the power devices. From previous research it is shown that wire bonding will not affect the E-field around the guard rings on a WBG device. However, planar power package, such as double-sided and power flip-chip device packaging could be a problem where the close distance between the topside of the power device and conducting plane may negatively affect the E-field distribution of the guard rings, which in turn lowers the reverse blocking capability of the WBG power device and increases leakage current creating greater on-state power loss, or even early break down. Few works have shown the Electric field distribution in embedded power modules. Therefore, a more detailed investigation and possible solution is needed for the proliferation of double-sided power packages. To investigate this packaging problem simulations were performed in Sentaurus TCAD and COMSOL based on the device physics and package geometries. Guard ring structures in 1.2kV and 10kV SiC Schottky Barrier Diode (SBD) were built and simulated in various double-sided package geometries, together with the thermal and mechanical evaluation of the package, to observe the influence on the E-field distribution in and out the WBG device. Different double-sided package structures were evaluated and a guideline (spacing/pad size/etc.) summarized for double-sided design. Moreover, a new bevel edge termination method was evaluated for double-sided WBG power semiconductor devices. Experimental reverse blocking test results will be reported in various temperature (from 25°C to 175°C) to verify the function of the package. The tests are on 1200V/50A SiC SBD (Schottky Barrier Diode) from Global Power Technology, which has double-sided Ag on both sides.

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Lee, Mankoo, Dipankar Pramanik, Haifan Liang, Ed Korczynski, and Jeroen van Duren. "Optimization of Graded CIGS Solar Cells Using TCAD Simulations." MRS Proceedings 1447 (2012). http://dx.doi.org/10.1557/opl.2012.1167.

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ABSTRACTTo understand paths towards higher efficiency (η) for copper-indium-gallium-(sulfur)-selenide [CIG(S)Se] solar cells, we investigated a variety of absorber composition grading schemes for various back-side gallium (Ga), front-side sulfur (S), and double-graded Ga composition depth profiles in TCAD 1D/2D simulations. We fitted experimental results of a Back-Side Graded (BSG) solar cell with our TCAD models, prior to investigating other grading and interface schemes. The BSG solar cell was fabricated on a High Productivity Combinatorial (HPC™) platform based on sputtering Cu(In,Ga) followed by selenization. Our TCAD simulation methodology for optimizing CIG(S)Se solar cells started with a sensitivity analysis using 1D Solar-cell CAPacitance Simulator (SCAPS) [1] by selecting a typical range of key model parameters and analyzing the impact on η. We then used a 2D commercially-available Sentaurus simulation tool [2] to incorporate wavelength-dependent optical characteristics. As a result, we provide insight in the impact of grading schemes on efficiency for a fixed ‘material quality’ equal to an in-house BSG solar cell. We also quantify the effects of interface layers like MoSe2 at the Mo/CIG(S)Se interface, and an inverted surface layer at the CIG(S)Se/CdS interface.

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"Simulation photoelectric parameters of vertical junction solar cells." International Journal of Advanced Trends in Computer Science and Engineering 10, no. 2 (April 5, 2021): 543–48. http://dx.doi.org/10.30534/ijatcse/2021/131022021.

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Many properties of the solar cells are being studied extensively. In this study, the basic photoelectric parameters of vertical junction solar cell were modeled. Attempts were made to approach the scientific work both physically and programmatically. In terms of programming, a perfect algorithm has been developed for modeling vertical junction solar cell in the Sentaurus TCAD software package. Using this algorithm, a vertical junction solar cell was modeled. The main focus was on the comparison of the photoelectric parameters of a vertical junction solar cell consisting of 3 elements with the photoelectric parameters of a vertical solar cell consisting of single element. The results obtained were physically based.

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"Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator." International Journal of Innovative Technology and Exploring Engineering 8, no. 12S2 (December 31, 2019): 61–66. http://dx.doi.org/10.35940/ijitee.l1012.10812s219.

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This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.

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Yahya, Erman Azwan, Ramani Kannan, and Lini Lee. "Simulation study of single event effects sensitivity on commercial power MOSFET with single heavy ion radiation." Bulletin of Electrical Engineering and Informatics 8, no. 4 (December 1, 2019). http://dx.doi.org/10.11591/eei.v8i4.1611.

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High-frequency semiconductor devices are key components for advanced power electronic system that require fast switching speed. Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the most famous electronic device that are used in much power electronic system. However, the application such as space borne, military and communication system needs Power MOSFET to withstand in radiation environments. This is very challenging for the engineer to develop a device that continuously operated without changing its electrical behavior due to radiation. Therefore, the main objective of this study is to investigate the Single Event Effect (SEE) sensitivity by using Heavy Ion Radiation on the commercial Power MOSFET. A simulation study using Sentaurus Synopsys TCAD software for process simulation and device simulation was done. The simulation results reveal that single heavy ion radiation has affected the device structure and fluctuate the I-V characteristic of commercial Power MOSFET.

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Geißendörfer, Stefan, Karsten von Maydell, and Carsten Agert. "Numerical 3D-Simulation of Micromorph Silicon Thin Film Solar Cells." MRS Proceedings 1321 (2011). http://dx.doi.org/10.1557/opl.2011.934.

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ABSTRACTIn this contribution 1, 2 and 3-dimensional simulations of micromorph silicon solar cells are presented. In order to simulate solar cells with rough interfaces, the surface topographies were measured via atomic force microscopy (AFM) and transferred into the commercial software Sentaurus TCAD (Synopsys). The model of the structure includes layer thicknesses and optoelectronic parameters like complex refractive index and defect structure. Results of the space resolved optical generation rates by using of the optical solver Raytracer are presented. The space resolved optical generation rate inside the semiconductor layers depends on the structure of the transparent conductive oxides (TCO) interface. In this contribution the influence of different optical generation rates on the electrical characteristics of the solar cell device are investigated. Furthermore, the optical and electrical results of the 1D, 2D and 3D structures, which have equal layer thicknesses and optoelectronic parameters, are compared.

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Lee, Mankoo, Xuena Zhang, and Dipankar Pramanik. "Analysis of Cu-Line EM Failure Kinetics Using Mass Transport TCAD Simulations." MRS Proceedings 1559 (2013). http://dx.doi.org/10.1557/opl.2013.870.

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ABSTRACTWe describe a mass transport TCAD simulation by using a Sentaurus S-Interconnect tool [1] that models reported electro-migration (EM) behaviors: EM induced resistance (R) change, line length (L) effect, and temperature (T) dependency on L and current density (j) products. We performed trend and sensitivity analyses for key physical EM model parameters: Cu-void formation, a sudden jump in line R associated with void growth, and Cu-vacancy (Cv) and void (Cvoid) profiles. In this manner, we develop a new methodology for accurately determining the EM lifetime by identifying an “EM-aware” region to define the L dependence of Cu-lines under high current stress. This includes electron flow dependency to explain line and via depletion effects for void formations under various stress conditions. We report a non-linearity in the L dependence on the jL product and a slight temperature dependence on the Blech Threshold (jL)c.

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Li, Joel B., and Bruce M. Clemens. "Modeling the Performance of Biaxially-Textured Silicon Solar Cells." MRS Proceedings 1670 (2014). http://dx.doi.org/10.1557/opl.2014.590.

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ABSTRACTGrain boundaries (GBs) in polycrystalline silicon (poly-Si) thin film solar cells are frequently found to be detrimental for device performance. Biaxiallytextured silicon with grains that are well-aligned in-plane and out-of-plane can possess fewer GB defects. In this work, we use TCAD Sentaurus device simulator and known experimental work to investigate and quantify the potential performance gains of biaxially-textured silicon. Simulation shows there can be performance gain from well-aligned grains when GB defects dominate carrier recombination or when grains are small. On the other hand, when intra-grain defects dominate recombination and grains are large, well-aligned grains do not lead to much performance gain. Another important result from our simulation is when intra-grain and GB defects are few, Jsc is almost independent of grain size while Voc drops with decreasing grain size.

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"Performance Analysis of Double Gate Hetero Junction Tunnel Fet." International Journal of Innovative Technology and Exploring Engineering 9, no. 2S3 (December 30, 2019): 232–34. http://dx.doi.org/10.35940/ijitee.b1058.1292s319.

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In this paper, a novel heterojunction tunnel field-effect transistor (HTFET) using Sentaurus technology computer-aided design (TCAD) simulations has been presented. The InAs/GaSb compound materials are used in both single gate heterojunction TFET (SG-HTFET) and Double gate heterojunction TFET (DG-HTFET) with SiO2 gate oxide layer to increase performance of the device.The implemented SG-HTFET and DG-HTFET device are increase the TFET's cross-sectional tunnel area. This result develops the subthreshold swing (SS) by 2.45 times, drive current (ION) is close to 10-6 A/µm, leakage current (IOFF) is close to 10-17 A/µm and also diminish the ambipolarity of the device compared to the TFET.

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"Impact of band to band Tunneling on Transient performance of Dual Gate Tunnel Field Effect Transistor (TFET)." International Journal of Innovative Technology and Exploring Engineering 8, no. 9 (July 10, 2019): 284–88. http://dx.doi.org/10.35940/ijitee.h7236.078919.

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Tunnel Field Effect Transistor (TFET) is gated reverse biased P-I-N diode structured semiconductor device and can be considered as a reliable low power device. TCAD (Sentaurus 2D) simulations for various Gate metal work function (4.1-4.3 eV) shows that its ON-current (ION) arises from quantum mechanical band-to-band tunneling (B2BT) and observed that threshold Voltage (VT) for TFET decreases with increase in Gate metal work function. The thermionic emission of electrons in MOSFET limits the sub-threshold swing (SS) by 60 mV/dec whereas TFET has potential for low SS ie. SS<60 mV/dec. TCAD Simulations confirmed that that the Gate – Drain capacitance (Cgd) strongly follows the Gate capacitance (Cgg) all over the voltage range (0-0.9V) which increases the miller capacitance for TFET. It is investigated that for TFET, the injection of carriers into the channel is through B2BT which effectively couples the Gate charge to the Drain. A look up table based Verilog-A model is generated for TFET and used to simulate the static and dynamic behavior of TFET based digital circuit in Cadence spectre. Miller effect causes the peak voltage overshoots are noticed at the drain side during transient responses and can be responsible for dynamic power loss and high turn ON/OFF delay

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Morozzi, Arianna, Francesco Moscatelli, Tommaso Croci, and Daniele Passeri. "TCAD Modeling of Surface Radiation Damage Effects: A State-Of-The-Art Review." Frontiers in Physics 9 (February 2, 2021). http://dx.doi.org/10.3389/fphy.2021.617322.

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A comprehensive numerical model which accounts for surface damage effects induced by radiation on silicon particle detectors is presented with reference to the state-of-the-art Synopsys Sentaurus Technology CAD (TCAD) tool. The overall aim of this work is to present the “Perugia 2019 Surface” damage modeling scheme, fully implemented within the TCAD environment, which effectively describes the surface damage effects induced by radiation in silicon sensors relying on a limited number of parameters relevant for physics. To this end, extensive measurement campaigns have been recently performed on gated-diodes and MOS capacitors at Fondazione Bruno Kessler (FBK) in Italy, Hamamatsu Photonics (HPK) in Japan and Infineon Technologies (IFX) in Austria on both n-type and p-type substrates (with and without p-spray isolation implants), in order to extrapolate the relevant parameters which rule the surface damage effects. The integrated interface trap density and the oxide charge density, have been determined before and after X-ray irradiation with doses ranging from 0.05 to 100 Mrad(SiO2), for each specific foundry and technology flavor. The main guidelines of this study are the versatility and generality of the simulation approach.

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Tang, Zhenyu, Xiaoyan Tang, Shi Pu, Yimeng Zhang, Hang Zhang, Yuming Zhang, and Song Bo. "Study on high temperature model based on the n-Channel planar 4H-SiC MOSFET." Circuit World ahead-of-print, ahead-of-print (June 10, 2021). http://dx.doi.org/10.1108/cw-12-2020-0351.

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Purpose To use the 4H-SiC material in integrated circuits for high temperature application, an accurate and simple circuit model of n-channel planar 4H-SiC MOSFET is required. Design/methodology/approach In this paper, a SPICE model of n-channel planar 4H-SiC MOSFET was built based on the device simulation results and measurement results. Firstly, a device model was simulated with Sentaurus TCAD, with measured parameters from fabricated planar 4H-SiC MOSFET previously. Then the device simulation results were analyzed and parameters for SPICE models were extracted. With these parameters, an accurate SPICE model was built and simulated. Findings The SPICE model exhibits the same performance as the measured results with different environment temperatures. The simulation results indicate that the maximum fitting error is 0.22 mA (7.33% approximately) at 200 °C. A common-source amplifier with this model is also simulated and the simulated gain is stable at different environment temperatures. Originality/value This paper provides a reliable modeling method for n-Channel Planar 4H-SiC MOSFET and reference value for the design of 4H-SiC high temperature integrated circuit.

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Michalak, Tyler J., Chris Borst, Dan Franca, Josh Herman, and Martin Rodgers. "Simulation of Millisecond Laser Anneal on SOI: A Study of Dopant Activation and Mobility and its Application to Scaled FinFET Thermal Processing." MRS Proceedings 1562 (2013). http://dx.doi.org/10.1557/opl.2013.825.

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ABSTRACTThis work investigates scanning laser annealing used for ultra-shallow junction (USJ) activation. We investigate the laser system via simulation to determine the peak temperature achieved in the active area during processing. We employed the Sentaurus TCAD software by Synopsys to perform a 2D simulation of a laser scans across the active area of the device, solving the heat equation in both time and space. An absorber layer is deposited on the wafer surface to enhance the absorption of incident energy and reduce SOI reflectivity. An effective absorption coefficient of α=8000cm-1 was calculated for the absorber layer, calibrated with the experimental laser intensity. This absorption coefficient correctly predicts the silicon temperature as a function of power with any arbitrarily defined scan speed. To investigate the role of dopant activation, an SOI wafer was implanted with arsenic 25 keV, dose 3e15 /1.5e15 cm-2 and laser annealed in areas of target temperatures ranging from 850-1300°C. The sheet resistance was measured using 4-point probe showing sheet resistance improvement with increasing laser temperature. The extracted temperature cycle from the 2D heat simulation was used as an equivalent millisecond RTA in a full 3D process simulation to study dopant distribution and activation using Sentaurus Process Kinetic Monte Carlo (KMC), considering the effect of dopants, dopant clusters, and point defects. The results of this simulation demonstrate deactivation of arsenic above 1050°C, which is inconsistent with Hall measurements that suggest increasing laser temperature will increase mobility and activation. The results are analyzed versus the expected trends and suggest future improvements needed to the KMC model or the laser temperature profiles in order to describe activation kinetics in millisecond anneals within SOI.

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"Influence of Self-Heating Effect on I-V Dates of Party Depleted Submicron Silicon-on-Insulator CMOS Transistors at High Ambient Temperatures." International Journal of Innovative Technology and Exploring Engineering 9, no. 1 (November 10, 2019): 1446–50. http://dx.doi.org/10.35940/ijitee.a4244.119119.

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To solve the problems of high temperature microelectronics the influence of the self heating effect on the IV dates partially depleted submicron silicon–on-insulator CMOS transistor in the ambient temperature range from 525 K to 650 K is discussed. Approach consists in combination of experimental data and of computational simulating results. For simulation of electrothermal characteristics of SOI CMOS transistor is considered three-layered structure. Temperature distribution is calculated numerically using iterative algorithm in conjunction with software COMSOL Multiphysics. I-V dates of SOI CMOS transistors are calculated by means of two-dimensional models for n-and p-channel transistors of Sentaurus TCAD developed in the system of instrument and technological modelling. TCAD models are calibrated on experimental characteristics for 525 K. It is shown that with growth of ambient temperature the selfheating mechanism contribution consistently decreases. By results of modeling it is established that self-heating contributions at supply voltages 5.5 V to decreases for ntransistor in 2.8 times, p-transistor in 2.2 times. The relative decline of current n-type transistor for reduced from 11.6% to 5.5% and for p-type with 15% to 9%. However, different dynamics of current recession for n-and p-transistors is significant for analog applications that need to be considered at high-temperature circuit design. The proposed methodology allows to critically assess the contribution of the self-heating mechanism on the I-V dates for a wide range of high temperatures and supply voltages. Underestimating this fact leads to unreasonable values for the maximum temperature and limit of thermal stability for the separate SOI CMOS transistor. In total this can be a prerequisite for a significant simplification of the design of not only the chip construction but also the whole electronic Board.

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Vyšniauskas, Juozas, and Eugenijus Gaubas. "Simulation of dynamic characteristics of GaN p-i-n avalanche diode operating as particle detector with internal gain." Lithuanian Journal of Physics 58, no. 2 (July 20, 2018). http://dx.doi.org/10.3952/physics.v58i2.3747.

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An evolution of the transient characteristics of the GaN p-i-n diodes, operating in the avalanche mode and acting as particle sensors, has been simulated by using the Synopsys TCAD Sentaurus software package and the drift-diffusion approach. Profiling of the charge generation, recombination and drift-diffusion processes has been performed over a nanosecond time-scale with a precision of a few picoseconds and emulated through the photo-excitation of an excess carrier domain at different locations of the active volume of a diode. Shockley–Read–Hall (SRH), Auger and radiative recombination processes have been taken into account. Fast and slow components within a current transient have been analysed based on the consideration of the carrier spatial distribution at different instants of the avalanche process. The internal gain due to charge multiplication ensures the sufficient charge collection on electrodes of the relatively thin (5 µm) diode operating in the avalanche mode. It has been shown that the simulated evolution of the detector transient responses by employing the drift-diffusion approach reproduces properly the qualitative modifications of the main features of a detector with an internal gain, realized by induction of the avalanche processes governed by the applied external voltage.

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Journal articles on the topic 'SentaurusTM TCAD simulation'

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