Relevant bibliographies by topics / SERDES

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'SERDES'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 April 2022

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Journal articles on the topic "SERDES"

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Kamm, Matthias, Hongshin Jun, and Luis Boluna. "SerDes Interoperability and Optimization." IEEE Design & Test of Computers 29, no. 5 (October 2012): 47–53. http://dx.doi.org/10.1109/mdt.2012.2201910.

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Moreira, P., S. Baron, S. Bonacini, O. Cobanoglu, F. Faccio, S. Feger, R. Francisco, et al. "The GBT-SerDes ASIC prototype." Journal of Instrumentation 5, no. 11 (November 29, 2010): C11022. http://dx.doi.org/10.1088/1748-0221/5/11/c11022.

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Volkov, Yu A., and V. M. Kalmykov. "Building a Telecommunication Network Based on the SERDES Platforms." Quality and life 26, no. 2 (2020): 38–41. http://dx.doi.org/10.34214/2312-5209-2020-26-2-38-41.

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Jeong, Woojin, Hoseung Song, Eunmin Choi, Suwon Kang, and Ji-Woong Choi. "Automotive SerDes Performance Evaluation under In-line Connector Channels." Transaction of the Korean Society of Automotive Engineers 28, no. 11 (November 1, 2020): 789–96. http://dx.doi.org/10.7467/ksae.2020.28.11.789.

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Zinner, Helge. "Automotive Ethernet und SerDes im Wettbewerb." ATZelektronik 15, no. 7-8 (July 2020): 40–43. http://dx.doi.org/10.1007/s35658-020-0227-x.

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Zinner, Helge. "Automotive Ethernet and SerDes in Competition." ATZelectronics worldwide 15, no. 7-8 (July 2020): 40–43. http://dx.doi.org/10.1007/s38314-020-0232-0.

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YAMAGUCHI, K. "Channel-Count-Independent BIST for Multi-Channel SerDes." IEICE Transactions on Electronics E89-C, no. 3 (March 1, 2006): 314–19. http://dx.doi.org/10.1093/ietele/e89-c.3.314.

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Kim, Jongsun, and Jintae Kim. "A High-speed SerDes Transceiver for Wireless Proximity Communication." JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 18, no. 1 (February 28, 2018): 42–48. http://dx.doi.org/10.5573/jsts.2018.18.1.042.

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Kumar, Ashok, and Sanjeev Mehta. "Design of 12B/14B: A Novel SERDES Encoding Technique." International Journal of Information Technology and Computer Science 6, no. 9 (August 8, 2014): 32–38. http://dx.doi.org/10.5815/ijitcs.2014.09.04.

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Wang, Bin, and Qing Sheng Hu. "A High-Speed 64b/66b Decoder Used in SerDes." Applied Mechanics and Materials 556-562 (May 2014): 1549–52. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1549.

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A high-speed 64b/66b decoder for SerDes system was designed in TSMC 0.18-μm CMOS Technology. The chip is composed of Block Sync, Descrambler, Decode Process and Receive Control. To make the system can be work in high speed, we use a lot of technology such as pipeline strategy, optimization of complicated logics and parallel descrambler.
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Dissertations / Theses on the topic "SERDES"

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Kas, Adem. "Validation of Power Dissipation of SerDes IPs." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-291216.

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Post-Silicon validation of a designed ASIC is an essential step in the product development process. During the validation process, all specifications of the ASICs have to be controlled in a lab environment. Serializer/Deserialiser(SerDes) blocks in an ASIC are used to perform high-speed serial data communication between distinct integrated circuits. The goal of the thesis is to validate the power consumption of SerDes IP blocks provided by different vendors in an ASIC. To validate power consumption, current and voltage values are read from power supply lines. Then these values are digitized and stored on a Raspberry Pi. To perform these operations, the initial firmware provided by vendors is improved to control SerDes operations, and software is developed to control the Raspberry Pi. Power measured operation is performed for every possible data rate for each SerDes modules. Power measurement is also performed for different temperature range in industry standards with the highest possible data rate for each SerDes IP block. As a final step, measured power consumption values are compared to vendors’ data.
Validering av en designad ASIC efter kisel är ett viktigt steg i produktutvecklingsprocessen. Under valideringsprocessen måste alla specifikationer för ASIC kontrolleras i en laboratoriemiljö. Serializer / Deserialiser (SerDes) -block i en ASIC används för att utföra höghastighets seriell datakommunikation mellan distinkta integrerade kretsar. Målet med avhandlingen är att validera strömförbrukningen för SerDes IP-block som tillhandahålls av olika leverantörer i en ASIC. För att validera strömförbrukningen läses strömoch spänningsvärden från strömförsörjningsledningarna. Sedan digitaliseras dessa värden och lagras på en Raspberry Pi. För att utföra dessa operationer förbättras den inledande firmware som tillhandahålls av leverantörer för att styra SerDesoperationer och programvara utvecklas för att styra Raspberry Pi. Effektmätt operation utförs för varje möjlig datahastighet för varje SerDes-modul. Mätoperationer utförs också för olika temperaturintervall i branschstandarder med högsta möjliga datahastighet för varje SerDes IP-block. Som ett sista steg jämförs uppmätta energiförbrukningsvärden med leverantörens data.
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Rogers, Michael. "High-speed low-voltage line driver for SerDes applications." Thesis, Oxford Brookes University, 2009. https://radar.brookes.ac.uk/radar/items/d7f9d856-ae6d-4eab-bb7d-aa54376560d6/1/.

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The driving factor behind this research was to design & develop a line driver capable of meeting the demanding specifications of the next generation of SerDes devices. In this thesis various line driver topologies were analysed to identify a topology suited for a high-speed low-voltage operating environment. This thesis starts of by introducing a relatively new high-speed communication Device called SerDes. SerDes is used in wired chip-to-chip communications and operates by converting a parallel data stream in a serial data stream that can be then transmitted at a higher bit rate, existing SerDes devices operate up to 12.5Gbps. A matching SerDes device at the destination will then convert the serial data stream back into a parallel data stream to be read by the destination ASIC. SerDes typically uses a line driver with a differential output. Using a differential line driver increases the resilience to outside sources of noise and reduces the amount of EM radiation produced by transmission. The focus of this research is to design and develop a line driver that can operate at 40Gbps and can function with a power supply of less than IV. This demanding specification was decided to be an accurate representation of future requirements that a line driver in a SerDes device will have to conform to. A suitable line driver with a differential output was identified to meet the demanding specifications and was modified so that it can perfonn an equalisation technique called pre-distortion. Two variations of the new topology were outlined and a behavioural model was created for both using Matlab Simulink. The behavioural model for both variants proved the concept, however only one variant maintained its perfomance once the designs were implemented at transistor level in Cadence, using a 65nm CMOS technology provided by Texas Instruments. The final line driver design was then converted into a layout design, again using Cadence, and RC parasitics were extracted to perfom a post-layout simulation. The post layout simulation shows that the novel line driver can operate at 40Gbps with a power supply of 1 V - O.8V and has a power consumption of 4.54m W /Gbps. The Deterministic Jitter added by the line driver is 12.9ps.
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Müller, Markus Roman [Verfasser], and Ulrich [Akademischer Betreuer] Brüning. "Digital Centric Multi-Gigabit SerDes Design and Verification / Markus Roman Müller ; Betreuer: Ulrich Brüning." Heidelberg : Universitätsbibliothek Heidelberg, 2018. http://d-nb.info/1177691191/34.

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Manoni, Simone. "EPAC Multi-FPGA SerDes: Enabling Partitioning of the European Processor Accelerator on Multiple FPGAs." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2022.

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European Processor Initiative (EPI) è un progetto attualmente implementato nella seconda fase di un accordo con la Commissione europea, il cui scopo è quello di progettare e attuare una tabella di marcia per una nuova famiglia di processori europei a basso consumo per l'extreme scale computing, Big-Data, HPC e altre applicazioni emergenti. La prima fase di EPI è iniziata nel dicembre 2018 ed è stata completata con successo nel novembre 2021, con la consegna dei primi 143 test chip (EPACs) per l'unione europea. Il bring-up dei test chip è avvenuto con successo e ha eseguito il suo primo programma inviando i tradizionali saluti "Hello World!" in diverse lingue. Per eseguire tutte le necessarie procedure di prototipazione e test necessarie prima di inviare un chip in produzione, è necessario che l'EPAC sia emulato da un dispositivo FPGA. Tuttavia, la dimensione di EPAC è troppo grande per implementare e prototipare il progetto completo sulla maggior parte degli FPGA commerciali. Pertanto, fino ad ora, la prototipazione è stata è stata effettuata disabilitando diverse parti del sistema una per una, in modo che il sistema ridotto potesse essere implementato in un singolo FPGA. Il lavoro presentato in questa tesi, che è stato svolto all'interno di Semidynamics Technology Services per EPI, ha avuto come contributo la concezione del partizionamento EPAC su un sistema multi-FPGA, la definizione dell'architettura e la progettazione di un modulo Serializzatore-Deserializzatore che permette il partizionamento EPAC del sistema multi-FPGA, al fine di realizzare un emulatore Full-Chip.
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Guin, Ujjwal. "DESIGN FOR BIT ERROR RATE ESTIMATION OF HIGH SPEED SERIAL LINKS." Master's thesis, Temple University Libraries, 2010. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/105599.

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Electrical Engineering
M.S.E.
High-speed serial links in modern communication systems often require the Bit-Error-Rate (BER) to be at the level of 10 −12 or lower. From the industry perspective, major drawbacks in high volume production test for the serial links with low BER are the excessive test time for comparing each captured bit for error detection and costly instrumentation. In this thesis, we focus on developing a novel BER estimation methodology and its implementation. We propose a novel BER estimation methodology and an effective self-test system, which not only eliminates the usage of expensive measuring instruments, but also significantly reduces the test time. In the proposed BER estimation, we show that the total jitter (TJ) spectral information of a test SerDes is successfully estimated from the known TJ distribution of a golden SerDes. We propose a novel BER estimation formula that incorporates not only the TJ spectral information of the serial data, but also the TJ spectral information of the recovered clock. Our proposed estimation formula enables efficient BER estimation without excessive test time, and its accuracy does not depend on the jitter present in the serial data stream of the SerDes. The experimental results demonstrate that the test time for the proposed BER estimation is in the order of seconds, which translates to the test time savings of more than hundred times compared to the traditional BER measurement for the same accuracy. To implement the proposed BER estimation methodology, we have developed a novel time-to-digital converter (TDC). This design effectively measures the delay between two signals and converts it into the digital format. Performance of the TDC has been evaluated and presented using ModelSim and SPICE simulation.
Temple University--Theses
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Gobbi, Vitaliano. "Progetto e sperimentazione di un convertitore seriale parallelo su FPGA per un flusso video LVDS a elevata frequenza generato da una telecamera stereo." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2012. http://amslaurea.unibo.it/3345/.

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Mahmoud, Ahmed Gamal Mohamed. "Boundary-scan for High-speed Serial Links." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2018.

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The complexity of integrated circuit (IC) designs continues to increase with the constant advancement of process technology and decrease of feature size in a relentless effort to achieve better performance and reach new milestones. However, with the increasing density and complexity comes a higher probability of defects occurring as well as a higher impact of these defects on the overall performance. Testing, thus, proves essential in order to guarantee defect-free designs. Effective and efficient testing in terms of both cost and time becomes essential as well because of the continually rising cost of testing. Abstract Serializer-deserializer (SerDes) devices or serial-link transceivers, which represent the device-under-test (DUT) in this thesis, are no different. Since the interface is the bottleneck in the performance of various systems, efforts continue to push for faster, smaller, and more power-efficient SerDes, leaving it with stringent specifications to meet. This leads to it being susceptible to the higher defect probability we just mentioned. As these are wireline transceivers, the robustness of the interconnects is especially critical. These defects that affect the interconnects are troublesome due to the fact that it is relatively easy for the fault to be masked which would indicate a non-existent fault within the design itself. In this thesis, we propose a test receiver that is capable of putting the interconnects under test in both DC-coupled and AC-coupled scenarios in compliance with the IEEE-1149.1 and IEEE-1149.6 standards.
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Borrami, Sina. "A control unit for a Digitizer System for the PANDA Electromagnetic Calorimeter." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-421560.

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PANDA is the next generation hadron physics detector under construction at the Facility for Antiproton and Ion Research (FAIR) in Darmstadt, Germany to accurately detect and parameterize particles with kinetic energies from 1MeV to 8GeV. PANDA is a 4π detector and due to its unique shape, all the readout electronic from ADC modules, power supplies, and a controller unit is housed in the liquid-cooled crates mounted inside the detector. Therefore, the readout electronics are exposed to a high level of magnetic field and radiation. The controller unit as the critical component of the digitization system with adequate radiation resiliency governs the crate. The control unit manages power supplies, monitors the radiation damages of each ADC modules, offer a mechanism to re-program the ADC module firmware, and finally features a redundant communication for the crate over fiber optics. The purpose of this thesis is to study and design the controller unit hardware that meets the specification of the PANDA experiment.
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Bidaj, Klodjan. "Modélisation du bruit de phase et de la gigue d'une PLL, pour les liens séries haut débit." Thesis, Bordeaux, 2016. http://www.theses.fr/2016BORD0355/document.

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La vitesse des liens séries haut débit (USB, SATA, PCI-express, etc.) a atteint les multi-gigabits par seconde, et continue à augmenter. Deux des principaux paramètres électriques utilisés pour caractériser les performances des SerDes sont la gigue transmis à un niveau de taux d’erreur donné et la capacité du récepteur à suivre la gigue à un taux d’erreur donné.Modéliser le bruit de phase des différents components du SerDes, et extraire la gigue temporelle pour la décomposer, aideraient les ingénieurs en conception de circuits à atteindre les meilleurs résultats pour les futures versions des SerDes. Générer des patterns de gigue synthétiques de bruits blancs ou colorés permettrait de mieux analyser les effets de la gigue dans le système pendant la phase de vérification.La boucle d’asservissement de phase est un des contributeurs de la gigue d’horloge aléatoire et déterministe à l’intérieur du système. Cette thèse présente une méthode pour modéliser la boucle d’asservissement de phase avec injection du bruit de phase et estimation de la gigue temporelle. Un modèle dans le domaine temporel en incluant les effets de non-linéarité de la boucle a été créé pour estimer cette gigue. Une nouvelle méthode pour générer des patterns synthétiques de gigue avec une distribution Gaussienne à partir de profils de bruit de phase coloré a été proposée.Les standards spécifient des budgets séparés de gigue aléatoire et déterministe. Pour décomposer la gigue de la sortie de la boucle d’asservissement de phase (ou la gigue généré par la méthode présentée), une nouvelle technique pour analyser et décomposer la gigue a été proposée. Les résultats de modélisation corrèlent bien avec les mesures et cette technique aidera les ingénieurs de conception à identifier et quantifier proprement les sources de la gigue ainsi que leurs impacts dans les systèmes SerDes.Nous avons développé une méthode, pour spécifier la boucle d’asservissement de phase en termes de bruit de phase. Cette méthode est applicable à tout standard (USB, SATA, PCIe, …) et définit les profils de bruits de4phases pour les différentes parties de la boucle d’asservissement de phase, pour s’assurer que les requis des standards sont satisfaits en termes de gigue. Ces modèles nous ont également permis de générer les spécifications de la PLL, pour des standards différents
Bit rates of high speed serial links (USB, SATA, PCI-express, etc.) have reached the multi-gigabits per second, and continue to increase. Two of the major electrical parameters used to characterize SerDes Integrated Circuit performance are the transmitted jitter at a given bit error rate (BER) and the receiver capacity to track jitter at a given BER.Modeling the phase noise of the different SerDes components, extracting the time jitter and decomposing it, would help designers to achieve desired Figure of Merit (FoM) for future SerDes versions. Generating white and colored noise synthetic jitter patterns would allow to better analyze the effect of jitter in a system for design verification.The phase locked loop (PLL) is one of the contributors of clock random and periodic jitter inside the system. This thesis presents a method for modeling the PLL with phase noise injection and estimating the time domain jitter. A time domain model including PLL loop nonlinearities is created in order to estimate jitter. A novel method for generating Gaussian distribution synthetic jitter patterns from colored noise profiles is also proposed.The Standard Organizations specify random and deterministic jitter budgets. In order to decompose the PLL output jitter (or the generated jitter from the proposed method), a new technique for jitter analysis and decomposition is proposed. Modeling simulation results correlate well with measurements and this technique will help designers to properly identify and quantify the sources of deterministic jitter and their impact on the SerDes system.We have developed a method, for specifying PLLs in terms of Phase Noise. This method works for any standard (USB, SATA, PCIe, …), and defines Phase noise profiles of the different parts of the PLL, in order to be sure that the standard requirements are satisfied in terms of Jitter
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Muppalla, Ashwin K. "Ultra low power multi-gigabit digital CMOS modem technology for millimeter wave wireless systems." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41084.

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The objective of this research is to present a low power modem technology for a high speed millimeter wave wireless system. The first part of the research focuses on a robust ASIC design methodology. There are several aspects of the ASIC flow that require special attention such as logical synthesis, timing driven physical placement, Clock Tree Synthesis, Static Timing Analysis, estimation and reduction of power consumption and LVS and DRC closure. The latter part is dedicated to high speed baseband circuits such as Coherent and Non coherent demodulator which are critical components of a multi-gigabit wireless communication system. The demodulator operates at input data rates of multiple gigabits per second, which presents the challenge of designing the building blocks to operate at speeds of multiple GHz. The high speed complex multiplier is a major component of the non coherent demodulator. As part of the coherent demodulator the complex multiplier derotates the input sequence by multiplying with cosine and sine functions, Costas error calculator computes the phase error in the derotated input signal. The NCO (Numerically controlled Oscillator) is a look up table based system used to generate the cosine and sine functions, used by the derotator.The CIC filter is used to decimate the costas error signal as the loop bandwidth is significantly smaller compared to the sampling frequency. All these modules put together form the coherent demodulator which is an integral part of the wireless communication system. An implementation of Serdes is also presented which acts as an interface between the baseband modules and the RF front end.
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Books on the topic "SERDES"

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Stauffer, David R. High speed serdes devices and applications. New York: Springer, 2008.

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Rockrohr, James Donald, Amanullah Mohammad, Clarence Rosser Ogilvie, Kent Dramstad, Michael A. Sorna, Jeanne Trinko Mechler, and David Robert Stauffer. High Speed Serdes Devices and Applications. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-79834-9.

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BEA WebLogic server administration kit. Upper Saddle River, NJ: Prentice Hall, 2002.

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Preul, Wyatt. Professional Community server themes. Indianapolis, IN: Wiley, 2008.

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Wolverton, Van. Official Netscape FastTrack server book: Build a full-server Web site the easy way : for Windows NT & Windows 95. Research Triangle Park, NC: Ventana, 1997.

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Lipschutz, Robert P. Mastering Netscape FastTrack server. San Francisco: Sybex, 1996.

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Wyatt, Allen. Netscape FastTrack server. Rocklin, Calif: Prima Pub., 1996.

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Drew, Kittel, ed. Designing & implementing Microsoft index server. Indianapolis, IN: Sams.net, 1997.

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Carraze, Alain. Les series tele. Paris: Hachette Pratique, 2007.

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Christian, Gross. Professional NT Internet Information Server 2 administration. Olton, Birmingham [England]: Wrox Press, 1996.

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Book chapters on the topic "SERDES"

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Rockrohr, James Donald. "Serdes Concepts." In High Speed Serdes Devices and Applications, 1–29. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-79834-9_1.

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Zhang, Feng. "High-Speed Data Transfer Based on SERDES." In High-speed Serial Buses in Embedded Systems, 41–84. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1868-3_2.

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Nagesh, K. Arpitha, and D. R. Shilpa. "Verification of SerDes Design Using UVM Methodology." In Lecture Notes in Electrical Engineering, 607–16. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-0275-7_49.

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Rockrohr, James Donald. "Chip Integration." In High Speed Serdes Devices and Applications, 425–74. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-79834-9_10.

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Rockrohr, James Donald. "HSS Features and Functions." In High Speed Serdes Devices and Applications, 31–98. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-79834-9_2.

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Rockrohr, James Donald. "HSS Architecture and Design." In High Speed Serdes Devices and Applications, 99–124. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-79834-9_3.

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Rockrohr, James Donald. "Protocol Logic and Specifications." In High Speed Serdes Devices and Applications, 125–64. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-79834-9_4.

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Rockrohr, James Donald. "Overview of Protocol Standards." In High Speed Serdes Devices and Applications, 165–261. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-79834-9_5.

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Rockrohr, James Donald. "Reference Clocks." In High Speed Serdes Devices and Applications, 263–96. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-79834-9_6.

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Rockrohr, James Donald. "Test and Diagnostics." In High Speed Serdes Devices and Applications, 297–344. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-79834-9_7.

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Conference papers on the topic "SERDES"

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Tong, Tiancang, Bohong Wang, He Zheng, Xin Li, and Ares Cao. "Serdes SSC ATE solution." In 2016 China Semiconductor Technology International Conference (CSTIC). IEEE, 2016. http://dx.doi.org/10.1109/cstic.2016.7464079.

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Pan, Po-Chin, Hung-Hsiang Cheng, and Chen-Chao Wang. "High speed SerDes design verification." In 2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). IEEE, 2014. http://dx.doi.org/10.1109/impact.2014.7048438.

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Gupta, H. S., R. M. Parmar, and R. K. Dave. "High speed LVDS driver for SERDES." In 2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems (ELECTRO-2009). IEEE, 2009. http://dx.doi.org/10.1109/electro.2009.5441164.

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Young, Brian, and Amarjit S. Bhandal. "Package design for high-speed SerDes." In 2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS). IEEE, 2010. http://dx.doi.org/10.1109/edaps.2010.5682990.

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Sawaby, Abdelrahman M., Abdelrahman M. Elshorbge, Omar T. Abdelhalim, Mahmoud A. Farghaly, Mahmoud Sherif Taha, Yehia Hamdy Yehia, Salma El-Sawy, Mohamed Samir Fouad, and Hassan Mostafa. "A 10 Gb/s SerDes Transceiver." In 2021 3rd Novel Intelligent and Leading Emerging Sciences Conference (NILES). IEEE, 2021. http://dx.doi.org/10.1109/niles53778.2021.9600520.

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Chung, Kun-Wook, Samuel Steidl, Thomas Krawczyk, Roger Miller, Song Shang, Taqi Mohiuddin, Jay Cormier, and Craig Hornbuckle. "SerDes chips for 100Gbps Dual-Polarization DQPSK." In National Fiber Optic Engineers Conference. Washington, D.C.: OSA, 2009. http://dx.doi.org/10.1364/nfoec.2009.jwa91.

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Wenzel, Robert, Tingdong Zhou, and Steve Karako. "Flip-chip package for 28G SerDes interface." In 2016 IEEE 25th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS). IEEE, 2016. http://dx.doi.org/10.1109/epeps.2016.7835407.

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Xu, Chaolong, Zhang Luo, Jinwen Li, Kefei Wang, and Zhengbin Pang. "A high-speed transceiver with optical SerDes." In Applied Optics and Photonics China (AOPC2015), edited by Yanbiao Liao, Weixu Zhang, Desheng Jiang, Wei Wang, and Gilberto Brambilla. SPIE, 2015. http://dx.doi.org/10.1117/12.2199213.

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Sunter, S., and A. Roy. "Testing SerDes beyond 4 Gbps - changing priorities." In 2007 IEEE 29th Custom Integrated Circuits Conference. IEEE, 2007. http://dx.doi.org/10.1109/cicc.2007.4405698.

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Kumar, Ashok, Sanjeev Mehta, Sandip Paul, Hari Shanker Gupta, and R. M. Parmar. "Indigenous development of SERDES interface for miniaturization." In 2012 1st International Conference on Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN). IEEE, 2012. http://dx.doi.org/10.1109/et2ecn.2012.6470106.

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Reports on the topic "SERDES"

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Rapisarda, Stefano M., Paul M. Rubinov, and Neal G. Wilcer. D-Zero detector electronics Run IIb upgrade project: VME LVDS SERDES buff (VLSB) module specification. Office of Scientific and Technical Information (OSTI), March 2011. http://dx.doi.org/10.2172/1128114.

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Fox, K. M., T. B. Edwards, and W. T. Riley. Characterization of the LAWB99-series and ORLEC-series Glasses. Office of Scientific and Technical Information (OSTI), December 2017. http://dx.doi.org/10.2172/1411196.

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Turner, Aimee L. Genomic Science Series. Office of Scientific and Technical Information (OSTI), October 2006. http://dx.doi.org/10.2172/1041387.

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Broemeling, Lyle. Changing Time Series. Fort Belvoir, VA: Defense Technical Information Center, August 1986. http://dx.doi.org/10.21236/ada178030.

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Joubert, S. B., T. Burr, and J. C. Scovel. Disaggregating times series data. Office of Scientific and Technical Information (OSTI), May 1997. http://dx.doi.org/10.2172/481896.

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Muller, Peter. 'Aha Huliko'a Workshop Series. Fort Belvoir, VA: Defense Technical Information Center, September 2007. http://dx.doi.org/10.21236/ada605149.

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Krim, Hamid. Interdisciplinary Distinguished Seminar Series. Fort Belvoir, VA: Defense Technical Information Center, August 2014. http://dx.doi.org/10.21236/ada610852.

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Lewis, Stephanie. CUTR Transportation Webcast Series. Tampa, FL: University of South Florida, November 2018. http://dx.doi.org/10.5038/cutr-nctr-rr-2018-11.

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Sun, Lushan, and Sherry Haar. Naturally Refined Series: Rippled. Ames: Iowa State University, Digital Repository, February 2013. http://dx.doi.org/10.31274/itaa_proceedings-180814-604.

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Muller, Peter. 'Aha Huliko'a Workshop Series. Fort Belvoir, VA: Defense Technical Information Center, September 1997. http://dx.doi.org/10.21236/ada628216.

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You might also be interested in the extended bibliographies on the topic 'SERDES' for particular source types:
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