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Journal articles on the topic 'SERDES'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 April 2022

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1

Kamm, Matthias, Hongshin Jun, and Luis Boluna. "SerDes Interoperability and Optimization." IEEE Design & Test of Computers 29, no. 5 (October 2012): 47–53. http://dx.doi.org/10.1109/mdt.2012.2201910.

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2

Moreira, P., S. Baron, S. Bonacini, O. Cobanoglu, F. Faccio, S. Feger, R. Francisco, et al. "The GBT-SerDes ASIC prototype." Journal of Instrumentation 5, no. 11 (November 29, 2010): C11022. http://dx.doi.org/10.1088/1748-0221/5/11/c11022.

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3

Volkov, Yu A., and V. M. Kalmykov. "Building a Telecommunication Network Based on the SERDES Platforms." Quality and life 26, no. 2 (2020): 38–41. http://dx.doi.org/10.34214/2312-5209-2020-26-2-38-41.

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4

Jeong, Woojin, Hoseung Song, Eunmin Choi, Suwon Kang, and Ji-Woong Choi. "Automotive SerDes Performance Evaluation under In-line Connector Channels." Transaction of the Korean Society of Automotive Engineers 28, no. 11 (November 1, 2020): 789–96. http://dx.doi.org/10.7467/ksae.2020.28.11.789.

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5

Zinner, Helge. "Automotive Ethernet und SerDes im Wettbewerb." ATZelektronik 15, no. 7-8 (July 2020): 40–43. http://dx.doi.org/10.1007/s35658-020-0227-x.

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6

Zinner, Helge. "Automotive Ethernet and SerDes in Competition." ATZelectronics worldwide 15, no. 7-8 (July 2020): 40–43. http://dx.doi.org/10.1007/s38314-020-0232-0.

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7

YAMAGUCHI, K. "Channel-Count-Independent BIST for Multi-Channel SerDes." IEICE Transactions on Electronics E89-C, no. 3 (March 1, 2006): 314–19. http://dx.doi.org/10.1093/ietele/e89-c.3.314.

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8

Kim, Jongsun, and Jintae Kim. "A High-speed SerDes Transceiver for Wireless Proximity Communication." JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 18, no. 1 (February 28, 2018): 42–48. http://dx.doi.org/10.5573/jsts.2018.18.1.042.

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9

Kumar, Ashok, and Sanjeev Mehta. "Design of 12B/14B: A Novel SERDES Encoding Technique." International Journal of Information Technology and Computer Science 6, no. 9 (August 8, 2014): 32–38. http://dx.doi.org/10.5815/ijitcs.2014.09.04.

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10

Wang, Bin, and Qing Sheng Hu. "A High-Speed 64b/66b Decoder Used in SerDes." Applied Mechanics and Materials 556-562 (May 2014): 1549–52. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1549.

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A high-speed 64b/66b decoder for SerDes system was designed in TSMC 0.18-μm CMOS Technology. The chip is composed of Block Sync, Descrambler, Decode Process and Receive Control. To make the system can be work in high speed, we use a lot of technology such as pipeline strategy, optimization of complicated logics and parallel descrambler.

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11

Song, Shiming, and Yu Sui. "System Level Optimization for High-Speed SerDes: Background and the Road Towards Machine Learning Assisted Design Frameworks." Electronics 8, no. 11 (October 28, 2019): 1233. http://dx.doi.org/10.3390/electronics8111233.

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This decade has witnessed wide use of data-driven systems, from multimedia to scientific computing, and in each case quality data movement infrastructure is required, many with SerDes as a cornerstone. On the one hand, HPC and machine learning cloud infrastructure carry exabytes of data in a year through the backplanes of data centers. On the other hand, the growing need for edge computing in the IoT places a tight envelope on the energy per bits. In this survey, we give a system level overview of the common design challenges in implementing SerDes solutions under different scenarios and propose simulation methods benefiting from advanced machine learning techniques. Preliminary results with the proposed simulation platform are demonstrated and analyzed through machine learning based design methodologies.

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12

Hwang, Heejae, and Jongsun Kim. "A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR." Electronics 9, no. 7 (July 9, 2020): 1113. http://dx.doi.org/10.3390/electronics9071113.

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A 100 Gb/s quad-lane SerDes receiver with a phase-interpolator (PI)-based quarter-rate all-digital clock and data recovery (CDR) is presented. The proposed CDR utilizes a multi-phase multiplying delay-locked loop (MDLL) to generate the eight-phase reference clocks, which achieves multi-phase frequency multiplication with a small area and less power consumption. The shared MDLL generates and distributes eight-phase clocks to each CDR. The proposed CDR uses a new initial phase tracker that uses a preamble to achieve a fast lock time of about 12 ns and to provide a constant output data sequence. The CDR utilizes quarter-rate 2x-oversampling architecture, and the PI controller is designed full custom to minimize the loop latency. To improve the dithering jitter performance of the recovered clock, the decimation factor of the CDR can be adjustable. Also, a new continuous-time linear equalizer (CTLE) receiver was adopted to reduce power consumption and achieved a data rate of 25 Gb/s/lane. The proposed SerDes receiver with a digital CDR is implemented in 40 nm CMOS technology. The 100 Gb/s four-channel SerDes receiver (4 CTLEs + 4 CDRs + MDLL) occupies an active area of only 0.351 mm2 and consumes 241.8 mW, which achieves a high energy efficiency of 2.418 pJ/bit.

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13

Aziz, Pervez M., Adam Healey, Cathy Liu, Freeman Zhong, and Alex Zabroda. "SerDes Design and Modeling over 25+ Gb/s Serial Link." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000044–60. http://dx.doi.org/10.4071/isom-2011-ta2-paper1.

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In this paper, signal integrity challenges for high speed serial link at 25 Gb/s, such as lossy channels and noisy environments are discussed. A few solution spaces to address those challenges are investigated, such as advanced equalization schemes, alternative signaling formats and forward error correction. It demonstrates that advanced signal processing enables long reach and extra long reach serial link performance at 25 Gb/s in next generation systems. Modeling methodologies used in SerDes behavioral models to ensure good correlation with transistor level circuit simulation are also discussed.

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14

Gaggatur, J. S., and D. Thulasiraman. "Inductorless CTLE for 20 Gb/s SerDes for 5G backhaul." Electronics Letters 56, no. 5 (March 2020): 225–27. http://dx.doi.org/10.1049/el.2019.3034.

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15

Rogers, M., K. Hayatleh, F. J. Lidgey, and A. Joy. "High-speed low-voltage CMOS line driver for SerDes applications." International Journal of Electronics 100, no. 4 (April 2013): 575–81. http://dx.doi.org/10.1080/00207217.2012.713027.

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16

Vladuță, Roxana, Lidia Dobrescu, Nicolae Militaru, and Dragoș Dobrescu. "High frequency common-mode noise in serdes circuits’ optimized interconnections." Facta universitatis - series: Electronics and Energetics 33, no. 3 (2020): 327–49. http://dx.doi.org/10.2298/fuee2003327v.

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17

Kumawat, Mahesh, Mohit Singh Choudhary, Ravi Kumar, Gaurav Singh, and Santosh Kumar Vishvakarma. "A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application." Journal of Circuits, Systems and Computers 29, no. 07 (September 6, 2019): 2050110. http://dx.doi.org/10.1142/s0218126620501108.

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In the present technology development billions of transistors are fabricated on a single chip, which improves the performance of circuits in terms of high data transmission speed and power consumption. This requirement of data transmission speed is achieved with the help of high-speed transceivers. In this paper, we present a high-speed asynchronous wave-pipelined serializer and deserializer (SerDes) transceiver implemented using current-mode logic (CML). This asynchronous transceiver circuit does not require a clock and therefore it saves large amount of power which is consumed in the phase locked loop (PLL) and frequency synthesizer circuits. Further, the proposed design is built using CML which saves more power. CML circuit operates at relatively higher speed as compared to CMOS circuits which helps the circuit to operate at higher data rate. Compared to conventional CML latch, a novel CML latch is proposed in our design to increase the speed. The circuit is implemented in standard CMOS 65-nm technology. The total power consumed by the serializer and deserializer is 9.32[Formula: see text]mW, which is very less as compared to published related works. The proposed asynchronous SerDes transceiver operates at 18.1-Gbps data transmission rate with low power dissipation.

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18

Vandhana, S., Roji Marjorie, and S. Niranjana. "Design and Implementation of Serializer/Deserializer (SerDes) For triple Speed Ethernet (MAC)." Indian Journal of Public Health Research & Development 8, no. 4 (2017): 1352. http://dx.doi.org/10.5958/0976-5506.2017.00522.8.

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19

Hu, Chunmei, Shuming Chen, Pengcheng Huang, Yao Liu, and Jianjun Chen. "Evaluating the single event sensitivity of dynamic comparator in 5 Gbps SerDes." IEICE Electronics Express 12, no. 23 (2015): 20150860. http://dx.doi.org/10.1587/elex.12.20150860.

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20

Loke, A. L. S., R. K. Barnes, T. T. Wee, M. M. Oshima, C. E. Moore, R. R. Kennedy, and M. J. Gilsdorf. "A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking." IEEE Journal of Solid-State Circuits 41, no. 8 (August 2006): 1894–907. http://dx.doi.org/10.1109/jssc.2006.875289.

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21

Zhou, Mingzhu. "Design and analysis of a bang—bang PLL for 6.25 Gbps SerDes." Journal of Semiconductors 33, no. 12 (December 2012): 125005. http://dx.doi.org/10.1088/1674-4926/33/12/125005.

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22

Zhang, Changchun, Ming Li, Zhigong Wang, Kuiying Yin, Qing Deng, Yufeng Guo, Zhengjun Cao, and Leilei Liu. "Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies." JSTS:Journal of Semiconductor Technology and Science 13, no. 4 (August 31, 2013): 303–17. http://dx.doi.org/10.5573/jsts.2013.13.4.303.

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23

Jaiswal, Nivedita, and Radheshyam Gamad. "Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers." Circuits and Systems 06, no. 03 (2015): 81–92. http://dx.doi.org/10.4236/cs.2015.63009.

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24

Xu, Shi, Zhang Luo, Mingche Lai, Zhengbin Pang, and Renfa Li. "Integrated High-Speed Optical SerDes over 100GBd Based on Optical Time Division Multiplexing." ACM Journal on Emerging Technologies in Computing Systems 14, no. 2 (July 27, 2018): 1–16. http://dx.doi.org/10.1145/3154838.

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25

Lee, Jri, Ping-Chuan Chiang, Pen-Jui Peng, Li-Yang Chen, and Chih-Chi Weng. "Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies." IEEE Journal of Solid-State Circuits 50, no. 9 (September 2015): 2061–73. http://dx.doi.org/10.1109/jssc.2015.2433269.

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26

Wang, Shu, Chang Cai, Bingxu Ning, Ze He, Zhiqin Huang, Lingyan Xu, Mingjie Shen, Liewei Xu, and Gengsheng Chen. "Measurement and evaluation of the Single Event Effects of high-performance SerDes circuits." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 1012 (October 2021): 165618. http://dx.doi.org/10.1016/j.nima.2021.165618.

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27

Song, Shengyu, Jianjun Chen, Hengzhou Yuan, Haiyuan Xing, and Yi Wen. "A low-noise and fast transient response LDO design for high-speed SerDes." Journal of Physics: Conference Series 2187, no. 1 (February 1, 2022): 012006. http://dx.doi.org/10.1088/1742-6596/2187/1/012006.

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Abstract In order to deal with the special needs of high-speed digital-analog hybrid circuits for power supplies, this article has designed a LDO circuit specifically applied to high-speed SerDes. In the design process, a cross-coupled charge pump was used to increase the swing and reduce power supply noise, and to increase the gain and reduce the area overhead, the design of an asymmetric operational amplifier was introduced. At the same time, the use of the cascode structure is also conducive to the frequency stability of the loop and provides sufficient phase margin for the circuit. Through simulation verification, the low-frequency maximum internal noise of this LDO is only 0.96uV/sqrt(Hz), the transient response time when the load changes from low to high is 38ns, the transient response time from high to low is 84ns, the phase margin is 87.3deg, and the PSRR is 56.8dB.

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28

Zang, Yujie. "A Regulator Design for a SerDes PHY of a High Speed Serial Data Interface." Journal of Communications 9, no. 11 (2014): 876–83. http://dx.doi.org/10.12720/jcm.9.11.876-883.

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29

Beukema, T., M. Sorna, K. Selander, S. Zier, B. L. Ji, P. Murfet, J. Mason, et al. "A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization." IEEE Journal of Solid-State Circuits 40, no. 12 (December 2005): 2633–45. http://dx.doi.org/10.1109/jssc.2005.856584.

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30

Zid, Mounir, Alberto Scandurra, Rached Tourki, and Carlo Pistritto. "A high-speed four-phase clock generator for low-power on-chip SerDes applications." Microelectronics Journal 42, no. 9 (September 2011): 1049–56. http://dx.doi.org/10.1016/j.mejo.2011.06.012.

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31

Zhang, Mingke, and Qingsheng Hu. "A 10 Gb/s Equalizer in 0.18m CMOS Technology for High-speed SerDes." International Journal of Control and Automation 7, no. 11 (November 30, 2014): 299–302. http://dx.doi.org/10.14257/ijca.2014.7.11.28.

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32

Zhang, Mingke, and Qingsheng Hu. "A 6.25 Gb/s equalizer in 0.18 μm CMOS technology for high-speed SerDes." Journal of Semiconductors 34, no. 12 (December 2013): 125010. http://dx.doi.org/10.1088/1674-4926/34/12/125010.

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33

Shao, Guowei, Quanyu Sun, and Sun Yi. "Design of domestic serial and parallel interface module." E3S Web of Conferences 248 (2021): 03032. http://dx.doi.org/10.1051/e3sconf/202124803032.

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Domestic serial and parallel interface module is based on domestic high performance FPGA CPCIE module. This type of FPGA has rich logical resources and internal integration of a variety of high-speed interfaces, such as PCIE, high-speed Serdes interface, which can achieve serial port, time system, network and other interfaces design, greatly simplifying the hardware design of the module. The main communication interfaces, PCIE and UART, are realized by the IP core of FPGA, realizing the integration of the main functions on the chip, which greatly improves the flexibility and expansibility of the design.

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34

WANG, Hui, Ying-mei CHEN, Lv-fan YI, and Guan-guo WEN. "Jitter analysis and modeling of a 10 Gbit/s SerDes CDR and jitter attenuation PLL." Journal of China Universities of Posts and Telecommunications 18, no. 6 (December 2011): 122–26. http://dx.doi.org/10.1016/s1005-8885(10)60130-6.

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35

Wei-Zen Chen and Guan-Sheng Huang. "Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 6 (July 2008): 1495–501. http://dx.doi.org/10.1109/tcsi.2008.916507.

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36

Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, and Shi-Yang Sun. "A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 8 (August 2014): 559–63. http://dx.doi.org/10.1109/tcsii.2014.2327451.

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37

Chen, Bichen, Siming Pan, Junda Wang, Shaohui Yong, Muqi Ouyang, and Jun Fan. "Differential Crosstalk Mitigation in the Pin Field Area of SerDes Channel With Trace Routing Guidance." IEEE Transactions on Electromagnetic Compatibility 61, no. 4 (August 2019): 1385–94. http://dx.doi.org/10.1109/temc.2019.2925757.

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38

Krupnik, Yoel, Yevgeny Perelman, Itamar Levin, Yosi Sanhedrai, Roee Eitan, Ahmad Khairi, Yizhak Shifman, et al. "112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels." IEEE Journal of Solid-State Circuits 55, no. 4 (April 2020): 1077–85. http://dx.doi.org/10.1109/jssc.2019.2959511.

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39

Roshan-Zamir, Ashkan, Osama Elhadidy, Hae-Woong Yang, and Samuel Palermo. "A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS." IEEE Journal of Solid-State Circuits 52, no. 9 (September 2017): 2430–47. http://dx.doi.org/10.1109/jssc.2017.2705070.

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40

Zheng, Xuqiang, Chun Zhang, Fangxu Lv, Feng Zhao, Shuai Yuan, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang, and Hanjun Jiang. "A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS." IEEE Journal of Solid-State Circuits 52, no. 11 (November 2017): 2963–78. http://dx.doi.org/10.1109/jssc.2017.2746672.

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41

Lu, Yu-Chun, Henry Wong, Davide Tonietto, Da-Jun Zang, Su-Ping Zhai, and Liang Li. "Full-vector multi-mode fiber modeling for short reach serdes links of 112Gbps and beyond." Optics Express 24, no. 14 (July 8, 2016): 16132. http://dx.doi.org/10.1364/oe.24.016132.

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42

Okushima, Mototsugu, and Junji Tsuruta. "Secondary ESD clamp circuit for CDM protection of over 6Gbit/s SerDes application in 40nm CMOS." Microelectronics Reliability 53, no. 2 (February 2013): 215–20. http://dx.doi.org/10.1016/j.microrel.2012.04.010.

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43

Thulasiraman, Deepanraj, and Javed S. Gaggatur. "A tunable, power efficient active inductor-based 20 Gb/s CTLE in SerDes for 5G applications." Microelectronics Journal 95 (January 2020): 104657. http://dx.doi.org/10.1016/j.mejo.2019.104657.

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44

Armstrong, S. E., B. D. Olson, J. Popp, J. Braatz, T. D. Loveless, W. T. Holman, D. McMorrow, and L. W. Massengill. "Single-Event Transient Error Characterization of a Radiation-Hardened by Design 90 nm SerDes Transmitter Driver." IEEE Transactions on Nuclear Science 56, no. 6 (December 2009): 3463–68. http://dx.doi.org/10.1109/tns.2009.2033924.

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45

YUAN, Hengzhou, Yang GUO, Yao LIU, Bin LIANG, and Qiancheng GUO. "A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25Gb/s-6.25Gb/s SerDes." Chinese Journal of Electronics 27, no. 5 (September 1, 2018): 1009–14. http://dx.doi.org/10.1049/cje.2018.02.003.

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46

Zhang, Hong, Xin Du, Yao Zhang, Liao Gong, and Jun Cheng. "A low-jitter third-order self-biased PLL with adaptive fast-locking scheme for SerDes interfaces." Analog Integrated Circuits and Signal Processing 85, no. 2 (August 4, 2015): 311–21. http://dx.doi.org/10.1007/s10470-015-0615-y.

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47

Chen, Zhang Jin, Guo Hai Zhong, and Zhuo Bi. "A High Speed 8B/10B Encoder/Decoder Design Based on Low Cost FPGA." Advanced Materials Research 462 (February 2012): 361–67. http://dx.doi.org/10.4028/www.scientific.net/amr.462.361.

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A high speed 8B/10B Encoder/Decoder is presented in this paper. The Encoder/Decoder is based on Altera’s low cost FPGA Cyclone family. The Encoder/Decoder includes parallel pipeline structure. The Encoder/Decoder is applied to the Serializer/Deserializer (SERDES) of high-speed serial bus. The Encoder/Decoder is synthesized and simulated by Quartus II 9.1. The synthesis and analysis results show the maximum frequency is more than 359MHz. The timing simulation results show the clock frequency is more than 125 MHz. The single channel data rate of serial bus can get to 1.25Gbps. The proposed Encoder/Decoder can meet the requirements of most high-speed serial bus.

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48

Kim, Jongsun, and Hyungsik Shin. "A Low-power 3.52 Gbps SerDes with a MDLL Frequency Multiplier for High-speed On-chip Networks." JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 18, no. 6 (December 31, 2018): 658–66. http://dx.doi.org/10.5573/jsts.2018.18.6.658.

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49

De Keulenaer, T., G. Torfs, Y. Ban, R. Pierco, R. Vaernewyck, A. Vyncke, Z. Li, et al. "84 Gbit/s SiGe BiCMOS duobinary serial data link including Serialiser/Deserialiser (SERDES) and 5‐tap FFE." Electronics Letters 51, no. 4 (February 2015): 343–45. http://dx.doi.org/10.1049/el.2014.3817.

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50

Nedovic, Nikola, Anders Kristensson, Samir Parikh, Subodh Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, et al. "A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS." IEEE Journal of Solid-State Circuits 45, no. 10 (October 2010): 2016–29. http://dx.doi.org/10.1109/jssc.2010.2057970.

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