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Journal articles on the topic 'SERIAL ASYNCHRONOUS'

Author: Grafiati

Published: 26 October 2023

Last updated: 31 July 2025

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1

Dobkin, Rostislav, Michael Moyal, Avinoam Kolodny, and Ran Ginosar. "Asynchronous Current Mode Serial Communication." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 7 (2010): 1107–17. http://dx.doi.org/10.1109/tvlsi.2009.2020859.

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2

P, Srikanth, and Latha Kodam. "Design of Serial-Serial Multiplier based on the Asynchronous Counter Accumulation." International Journal of Computer Applications Technology and Research 3, no. 4 (2014): 263–66. http://dx.doi.org/10.7753/ijcatr0304.1013.

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3

Tošić, M. B., M. K. Stojčev, D. M. Maksimović, and G. Lj Djordjević. "The asynchronous counterflow pipeline bit-serial multiplier." Journal of Systems Architecture 44, no. 12 (1998): 985–1004. http://dx.doi.org/10.1016/s1383-7621(97)00046-5.

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4

Pambudi, Bimo Langgeng Rilo, and Wahyu Sapto Aji. "Serial Communication Module with Visual Basic and Arduino for Practical Use." Buletin Ilmiah Sarjana Teknik Elektro 3, no. 2 (2021): 130–36. http://dx.doi.org/10.12928/biste.v3i2.1494.

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Interface techniques on computers and instruments cannot be separated from the software contained in computers to communicate. Communication that is commonly used is serial and parallel data. The method used in this development uses the Asynchronous serial data communication method which occurs if the clock on each communication device is not synchronized in reading data and displaying data. serial communication using Visual Basic Software as a medium to read and display serial data from Arduino. The level of accuracy when reading data and displaying data error rate/error 0% with 8 times of te

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5

Ms. Banti Kumari, Ms. Kanika Jindal, and Mr. Amit Bindal. "Design and Implementation of Verilog Based High Speed Low Power UART." International Research Journal on Advanced Engineering Hub (IRJAEH) 2, no. 05 (2024): 1468–77. http://dx.doi.org/10.47392/irjaeh.2024.0203.

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The most crucial component of serial communication is a microcircuit called a universal asynchronous receiver/transmitter (UART). Receive-transmitter asynchronous technology is known as UART, and it is widely used for device-to-device communication protocols. Using asynchronous serial communication at a speed that can be adjusted. A hardware communication technique called UART Asynchronous conditions occur when the output of the transmitting device and the receiving end are not in sync with a clock. In UART, receiving a signal is known as RxD, and transmitting a signal is known as TxD. In comp

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Hariyanto, D., A. C. Nugraha, A. Asmara, and H. Liu. "An Asynchronous Serial Communication Learning Media: Usability Evaluation." Journal of Physics: Conference Series 1413 (November 2019): 012018. http://dx.doi.org/10.1088/1742-6596/1413/1/012018.

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7

Zeki, Semir. "A massively asynchronous, parallel brain." Philosophical Transactions of the Royal Society B: Biological Sciences 370, no. 1668 (2015): 20140174. http://dx.doi.org/10.1098/rstb.2014.0174.

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Whether the visual brain uses a parallel or a serial, hierarchical, strategy to process visual signals, the end result appears to be that different attributes of the visual scene are perceived asynchronously—with colour leading form (orientation) by 40 ms and direction of motion by about 80 ms. Whatever the neural root of this asynchrony, it creates a problem that has not been properly addressed, namely how visual attributes that are perceived asynchronously over brief time windows after stimulus onset are bound together in the longer term to give us a unified experience of the visual world, i

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8

Zhan, Hua Lin, and Xiao Chun Lai. "Multiple Serial Communication Design Based on ADSP-BF561." Advanced Materials Research 846-847 (November 2013): 667–70. http://dx.doi.org/10.4028/www.scientific.net/amr.846-847.667.

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This paper introduces asynchronous serial design and communication implementation by TI Co.,Ltd TL16C554 based on dual core processorADSP-BF561 and uClinux. This paper has accomplished multiple serial accessing using share interrupt scheme which has already been used in a wireless sense network.

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9

Gopal, P. Bala, and K. Hari Kishore. "An FPGA Implementation of On Chip UART Testing with BIST Techniques." International Journal of Reconfigurable and Embedded Systems (IJRES) 5, no. 3 (2016): 176. http://dx.doi.org/10.11591/ijres.v5.i3.pp176-182.

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A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST

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10

BINDU, MADDI. "Design and Implementation of High-Speed Universal Asynchronous Receiver and Transmitter (UART)." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–9. https://doi.org/10.55041/ijsrem40371.

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The Universal Asynchronous Receiver and Transmitter (UART) are described, which is essentially a serial data transfer protocol used in digital circuit applications. The UART transmitter architecture has a baud rate generator, a parity generator, a transmitter finite state machine (FSM), and a parallel in serial out (PISO) register. The UART receiver is composed of a baud rate generator, a negative edge detector, a parity checker, a receiver Finite State Machine (FSM), and a serial in parallel out (SIPO) register. The transmitter and the receiver have the same baud rate generator; therefore, th

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11

Kim, Hyoung Won, Hyo Dal Park, and Taek Lyul Song. "Multisensor Bias Estimation with Serial Fusion for Asynchronous Sensors." Journal of the Korea Institute of Military Science and Technology 15, no. 5 (2012): 676–86. http://dx.doi.org/10.9766/kimst.2012.15.5.676.

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12

KumarMeena, Manoj, and Neelam Rup Prakash. "ARM7TDMI based Low Cost Portable Serial Asynchronous Protocol Analyzer." International Journal of Computer Applications 40, no. 7 (2012): 27–32. http://dx.doi.org/10.5120/4977-7234.

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13

Pan, Deng, Yu Hua, and Yu Xiang. "Research of Transport Stream and PCR Timestamp in the Satellite Digital TV Time Service System." Applied Mechanics and Materials 411-414 (September 2013): 799–802. http://dx.doi.org/10.4028/www.scientific.net/amm.411-414.799.

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The Satellite Digital TV Time Service is based on the DVB-S Satellite Digital TV system, using Program Clock Reference (PCR) in the MPEG-2 frame to capture timestamp and measure delay time. This paper, considering the PCR as the Time Synchronization Flag after researching Transport Stream (TS) frame and Asynchronous Serial Interface (ASI) in Satellite Digital TV system, recovers the asynchronous serial data from TS in Satellite Digital TV by oversampling technology. After that, PCR will be found from the recovered data, and the timestamp will be captured when PCR is detected. Finally, this met

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14

Feng, Xiao Hui, and Chang Li Wang. "Research on Serial Communication in the Permanent Magnet Linear Synchronous Motor Vertical Transportation System." Advanced Materials Research 905 (April 2014): 476–80. http://dx.doi.org/10.4028/www.scientific.net/amr.905.476.

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The serial communication design based on DSP in the permanent magnet linear synchronous motor vertical transportation system is presented in this paper. The control system structure and fundamental are introduced briefly at first. Then, the realization of serial communication between the TMS320VC5402 and PC by asynchronous serial communications chip TL16C550C is introduced in detail. Finally, the design of system hardware interface circuit and software programs are presented. The features of this system include simple programming , good reliability and real-time capability.

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15

Tong, Xiao Rong, and Zhong Biao Sheng. "Design of UART with CRC Check Based on FPGA." Advanced Materials Research 490-495 (March 2012): 1241–45. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.1241.

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In order to realize the accurate serial communication, a simple and practical scheme for URAT design and implementation was put forward based on the analysis of CRC generation algorithm. The reliability of serial communication can be improved by adding CRC into the asynchronous serial communication. The CRC checksum module is achieved with Verilog language on the basis of FPGA and obtained consistence between the results of simulation and theoretical analysis. Therefore, the expected design target was met, and the communication speed and efficiency was improved.

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16

Dore, Ms Aruna. "Design and Implementation of UART using Verilog HDL and FPGA." INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 05 (2025): 1–9. https://doi.org/10.55041/ijsrem47124.

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Abstract - This study presents a hardware-based implementation of Universal Asynchronous Receiver Transmitter (UART) communication on the Nexys A7-100T Field Programmable Gate Array (FPGA) platform using Verilog HDL and Vivado Design Suite. UART serves as a fundamental serial communication protocol, widely adopted due to its simplicity and effectiveness. The work details the design methodology, including clock division, baud rate generation, and serial data transmission, while demonstrating successful communication between FPGA and PC. Experimental results confirm reliable and low-power serial

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17

Meher, Manas Ranjan, Ching Chuen Jong, and Chip-Hong Chang. "A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 10 (2011): 1733–45. http://dx.doi.org/10.1109/tvlsi.2010.2060374.

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18

Zhao, Xue Mei. "Realization of Serial Port Expansion Circuit." Applied Mechanics and Materials 271-272 (December 2012): 1597–601. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.1597.

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This article describes the design of a interface chip with serial port expansion circuit of computer in industrial applications. It is used to connect with 422 and RS232 interfaces. Circuits involved several major chip such as the interface of 422 and RS232 and UART(Universal Asynchronous Receiver Transmitter)16C550 Inside the computer. Paper describes the composition of the hardware circuit, theory and implementation and initialization programming of URAT interface chip. We use interface chip with the FIFO to the circuit, It improves the efficiency of the application software, And it solves t

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19

Dong, Meiting. "A Comparative Analysis of Synchronous USART And Asynchronous UART Communication Protocols." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 567–74. http://dx.doi.org/10.54097/hm6hre11.

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In contemporary applications, the integration of the STM32F103ZET6 microcontroller with various peripherals is indispensable, emphasizing the critical role of serial communication in data transmission between the microcontroller and these peripherals. This study delineates the distinctions between Universal Synchronous Asynchronous Receiver-Transmitter (USART) and Universal Asynchronous Receiver-Transmitter (UART) within the context of USART synchronous communication. The superiority of USART is underscored by its utilization of a uniform clock and identical baud rate for simultaneous and sync

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20

Yintang, Yang, Guan Xuguang, Zhou Duan, and Zhu Zhangming. "A full asynchronous serial transmission converter for network-on-chips." Journal of Semiconductors 31, no. 4 (2010): 045007. http://dx.doi.org/10.1088/1674-4926/31/4/045007.

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21

Jones, Dylan M. "Disruption of Memory for Lip-Read Lists by Irrelevant Speech: Further Support for the Changing State Hypothesis." Quarterly Journal of Experimental Psychology Section A 47, no. 1 (1994): 143–60. http://dx.doi.org/10.1080/14640749408401147.

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Two experiments critically re-examine the finding of Campbell and Dodd (1984, Experiment 2), which suggests that irrelevant speech disrupts the encoding of visual material for serial recall. Support is sought for the competing view that the effect of irrelevant speech is on storage by comparing the effect of a range of acoustic conditions on memory for graphic and lip-read lists. Initially, serial short-term recall of visually presented lists was examined with irrelevant speech that was both asynchronous with the visually presented items and of varied speech content (Experiment 1a). In this ex

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22

Gong, Jiajun, Wenbo Guo, and Weijian Sun. "UART communication protocol frame format explanation and application." Applied and Computational Engineering 14, no. 1 (2023): 47–56. http://dx.doi.org/10.54254/2755-2721/14/20230757.

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Universal Asynchronous Transceiver (UART) is a Universal Serial Data Bus, hardware communication protocol using asynchronous serial communication in a configurable manner rate. In most embedded systems, microcontrollers and computers, UART plays an important communication role as a hardware communication protocol between devices to ensure the efficient transmission of communication data. The understanding and use of the UART protocol is crucial in our design process. In order to better understand. basic principle this protocol and realize the use of URAT, this paper introduces serial communica

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23

S., Devakrupa* Drakshayani Desai. "DESIGN OF I2C-APB PROTOCOL." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 11 (2016): 330–35. https://doi.org/10.5281/zenodo.167006.

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I2C is a two wire, bidirectional serial bus that provides effective data communication between two devices. Problem starts when one module follows different protocol as others and each module has its different bit rate or baud rate of data transfer which can be either asynchronous or synchronous. I2C bus supports many devices and each device is recognized by its unique address. The proposed architecture is a bridge between I2C Master and APB Salve. The data travels from a serial bus (I2C) to parallel bus (APB) to serial (I2C) in sync with the respective domain clock. This forms a bidirectional

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24

Zhang, Hang. "A Systematic Analysis of The UART Transceiver Theory and Application." Highlights in Science, Engineering and Technology 61 (July 30, 2023): 172–79. http://dx.doi.org/10.54097/hset.v61i.10290.

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This article introduces the theoretical foundation and application of Universal Asynchronous Receiver/Transmitter (UART) in four chapters, including the history and structure of UART transceivers, and so on. UART is a kind of communication hardware using serial Asynchronous communication, which has the advantages of simple structure and good stability. It can convert serial data and parallel data to each other and transmit data between devices. It is widely used on various devices. In the 50 years since its invention, it has undergone many improvements and improvements. In the end, UART transc

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25

Zhang, Jie Fei, Peng Fei Zhan, and Gang Zhang. "Ethernet Controller and Serial Interface Conversion Technology Based on FPGA." Applied Mechanics and Materials 423-426 (September 2013): 2671–74. http://dx.doi.org/10.4028/www.scientific.net/amm.423-426.2671.

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The FPGA-based 10/100M Ethernet MAC controller and universal asynchronous serial communication controller are designed and connected on chip in this paper. Such functions as writing data transmitted by the serial interface to the Ethernet controller and sending them to the network, and serially outputting network data received by the Ethernet controller are implemented and interconnection communications between Ethernet and the serial are achieved, possessing great practical values in system test. Modularization design is performed on the whole system with VHDL in this study, whose hardware ap

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26

Park, Geun-Duk, Sam-Kweon Oh, and Byoung-Kuk Kim. "An Interrupt Coalescence Method for Improving Performance of Asynchronous Serial Communication." Journal of the Korea Academia-Industrial cooperation Society 12, no. 3 (2011): 1380–86. http://dx.doi.org/10.5762/kais.2011.12.3.1380.

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27

Kidiyarova-Shevchenko, A. Yu, K. Yu Platov, E. M. Tolkacheva, and I. A. Kataeva. "RSQO asynchronous serial multiplier and spreading codes generator for multiuser detector." IEEE Transactions on Appiled Superconductivity 13, no. 2 (2003): 429–32. http://dx.doi.org/10.1109/tasc.2003.813889.

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28

Kim, Chang Ouk, Ick-Hyun Kwon, and Jun-Geol Baek. "Asynchronous action-reward learning for nonstationary serial supply chain inventory control." Applied Intelligence 28, no. 1 (2007): 1–16. http://dx.doi.org/10.1007/s10489-007-0038-2.

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29

Kim, Chang Ouk, Ick-Hyun Kwon, and Jun-Geol Baek. "Asynchronous action-reward learning for nonstationary serial supply chain inventory control." Applied Intelligence 30, no. 2 (2007): 187. http://dx.doi.org/10.1007/s10489-007-0087-6.

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30

de Vreede, Gert-Jan, Robert O. Briggs, and Roni Reiter-Palmon. "Exploring Asynchronous Brainstorming in Large Groups: A Field Comparison of Serial and Parallel Subgroups." Human Factors: The Journal of the Human Factors and Ergonomics Society 52, no. 2 (2010): 189–202. http://dx.doi.org/10.1177/0018720809354748.

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Objective: The aim of this study was to compare the results of two different modes of using multiple groups (instead of one large group) to identify problems and develop solutions. Background: Many of the complex problems facing organizations today require the use of very large groups or collaborations of groups from multiple organizations. There are many logistical problems associated with the use of such large groups, including the ability to bring everyone together at the same time and location. Methods: A field study involved two different organizations and compared productivity and satisf

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31

Li, Zhangchi. "Design, refinement, and enhancement of FPGA-implemented UART circuitry." Applied and Computational Engineering 37, no. 1 (2024): 259–65. http://dx.doi.org/10.54254/2755-2721/37/20230520.

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This article provides an overview of the universal asynchronous receiver/transmitter, commonly referred to as Universal Asynchronous Receiver/Transmitter (UART). The UART stands as a noteworthy exemplar of a serial communication protocol, facilitating the exchange of data within a serial connection while accommodating full-duplex communication. The architecture of the UART hinges upon three principal constituents: the transmitter, the receiver, and the baud rate generator, the latter essentially a frequency divider. Each of these elements is meticulously crafted using the Verilog hardware desc

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32

Chen, Zai Ping, and Zhi Tong Chen. "Absolute Value Encoder Communication Interface Design Based on SSI Protocol." Applied Mechanics and Materials 441 (December 2013): 932–35. http://dx.doi.org/10.4028/www.scientific.net/amm.441.932.

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In terms of absolute value encoder applications, SSI communication protocol, as an earlier implementation of communication protocol, has been widely used recently. Many companies, including both domestic and overseas, have introduced encoder communication interfaces with the SSI absolute value. In this paper, based on the features of SSI protocol communication, we propose a low cost of SSI protocol communication interface design scheme for the absolute value encoder whose output is asynchronous or parallel. The experiment shows that this kind of communication interface is stable, reliable and

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33

Chen, Wenchong, Hongwei Liu, and Ershi Qi. "Buffer allocation in asynchronous serial production systems with Bernoulli machines during transients." International Journal of Industrial and Systems Engineering 39, no. 2 (2021): 176. http://dx.doi.org/10.1504/ijise.2021.118263.

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34

Calabretta, Nicola, Marco Presi, Giampiero Contestabile, and Ernesto Ciaramella. "All-Optical Asynchronous Serial-to-Parallel Converter Circuit for DPSK Optical Packets." IEEE Photonics Technology Letters 19, no. 10 (2007): 783–85. http://dx.doi.org/10.1109/lpt.2007.895895.

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35

Mourão, Flávio Afonso Gonçalves, André Luiz Vieira Lockmann, Gabriel Perfeito Castro, et al. "Triggering Different Brain States Using Asynchronous Serial Communication to the Rat Amygdala." Cerebral Cortex 26, no. 5 (2015): 1866–77. http://dx.doi.org/10.1093/cercor/bhu313.

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36

Liu, Hongwei, Wenchong Chen, and Ershi Qi. "Buffer allocation in asynchronous serial production systems with Bernoulli machines during transients." International Journal of Industrial and Systems Engineering 1, no. 1 (2020): 1. http://dx.doi.org/10.1504/ijise.2020.10030579.

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37

En, De, Huang He Wei, Na Na Wei, Xiao Long Shi, and Chang Sheng Zhou. "Design of Collecting and Processing System of GPS Information Based on ARM and Linux." Applied Mechanics and Materials 273 (January 2013): 714–17. http://dx.doi.org/10.4028/www.scientific.net/amm.273.714.

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GPS information collecting and processing is an important part of the navigation and positioning system. Through the establishment of cross-compiler environment, using the ARM processor S3C2440A and Linux operating systems as the hardware and software platform and the GS87 is used as GPS receiver module, the NMEA-0183 communications protocol and serial asynchronous communication between the ARM platform and GS87 module are analyzed. Through the serial port programming, GPS information collecting and processing system is realized. By querying the GPRMC statement and the corresponding conversion

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38

Zhang, Zhonghua, Song Chen, Shuyun Wang, Junwu Kan, Jianming Wen, and Can Yang. "Performance evaluation and comparison of a serial–parallel hybrid multichamber piezoelectric pump." Journal of Intelligent Material Systems and Structures 29, no. 9 (2018): 1995–2007. http://dx.doi.org/10.1177/1045389x18758181.

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To improve the output capability of piezoelectric pumps, researchers have made an attempt to combine multiple single-chamber pumps either in series or in parallel. In this article, a serial–parallel hybrid multichamber piezoelectric pump is presented. The novel serial–parallel hybrid multichamber piezoelectric pump structure is characterized by the simultaneous occurrence of serial/parallel forms through a combination of synchronous and asynchronous modes of piezoelectric actuators. Moreover, the pump can be operated in multiple working modes to obtain the desired chamber volume and number thr

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39

Legalov, Alexander I., Ivan V. Matkovskii, Mariya S. Ushakova, and Darya S. Romanova. "Dynamically Changing Parallelism with the Asynchronous Sequential Data Flows." Modeling and Analysis of Information Systems 27, no. 2 (2020): 164–79. http://dx.doi.org/10.18255/1818-1015-2020-2-164-179.

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A statically typed version of the data driven functional parallel computing model is proposed. It enables a representation of dynamically changing parallelism by means of asynchronous serial data flows. We consider the features of the syntax and semantics of the statically typed data driven functional parallel programming language Smile that supports asynchronous sequential flows. Our main idea is to apply the Hoar concept of communicating sequential processes to the computation control on the data readiness. It is assumed that on the data readiness a control signal is emitted to inform the pr

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40

Yang, Hong Cai, and Ming Qing Wu. "NC Processing Network Platform RS-232-C Interface Circuit Design." Advanced Materials Research 529 (June 2012): 29–32. http://dx.doi.org/10.4028/www.scientific.net/amr.529.29.

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RS-232-C and a modem together, the interface can connect all kinds of different types of micro computer, so that they can direct communication. Nowadays more popular FANUC series CNC system, and the machine is equipped with a 25 injection of RS-232-C asynchronous serial communication interface standards, connect the computer and programmer and peripherals. With MAX232 chip design of interface circuit DB9.

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41

Zhuang, Chenyu. "Comparison And Selection of Commonly Used Communication Protocols in Measurement and Control Instruments." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 540–46. http://dx.doi.org/10.54097/em4syb59.

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In the contemporary landscape of economic globalization, the salience of the field of measurement and control has progressively intensified. Simultaneously, the utilization of serial bus technology within instrumentation has witnessed a considerable proliferation. Consequently, the judicious selection of an appropriate serial bus protocol has assumed paramount importance. It is incumbent upon practitioners to consider diverse factors, including the communication principles, performance attributes, and interfacing requirements, when making their choice, to ensure the efficacious and stable oper

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42

Swathi, Prabhu, H. R. Unnathi, B. R. Chethan, R. Tejaswini, and A. O. Vaishnavi. "Review on multi bit flip-flop enhanced shift register: A low power solution for UART." i-manager’s Journal on Electrical Engineering 17, no. 2 (2023): 35. http://dx.doi.org/10.26634/jee.17.2.20432.

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This paper details the Verilog HDL- based design of UART modules. Developing UART with a shift register utilizing multibit flip-flops proves to be pragmatic strategy for contemporary VLSI circuits. This work supports not only asynchronous and serial communication but also aligns with essential objectives of minimizing power consumption and reducing overall circuit area. Such integration enhances data transmission efficiency while meeting crucial design considerations in modern electronics

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43

Chen, Ding. "Design and Innovation of Asynchronous Serial Communication Interface Conversion System of Field Bus." Journal of Physics: Conference Series 1792, no. 1 (2021): 012069. http://dx.doi.org/10.1088/1742-6596/1792/1/012069.

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44

ONIZAWA, Naoya, Takahiro HANYU, and Vincent C. GAUDET. "High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving." IEICE Transactions on Electronics E92-C, no. 6 (2009): 867–74. http://dx.doi.org/10.1587/transele.e92.c.867.

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45

Ito, M., K. Kawasaki, N. Yoshikawa, A. Fujimaki, H. Terai, and S. Yorozu. "20 GHz Operation of Bit-Serial Handshaking Systems Using Asynchronous SFQ Logic Circuits." IEEE Transactions on Appiled Superconductivity 15, no. 2 (2005): 255–58. http://dx.doi.org/10.1109/tasc.2005.849773.

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46

Mizuno, Masaaki, and Mikhail Nesterenko. "A transformation of self-stabilizing serial model programs for asynchronous parallel computing environments." Information Processing Letters 66, no. 6 (1998): 285–90. http://dx.doi.org/10.1016/s0020-0190(98)00069-6.

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47

HARIYAMA, M., S. ISHIHARA, and M. KAMEYAMA. "Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture." IEICE Transactions on Electronics E91-C, no. 9 (2008): 1419–26. http://dx.doi.org/10.1093/ietele/e91-c.9.1419.

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48

Ridley, Dennis, and Pierre Ngnepieba. "Antithetic Power Transformation in Monte Carlo Simulation: Correcting Hidden Errors in the Response Variable." Mathematics 11, no. 9 (2023): 2097. http://dx.doi.org/10.3390/math11092097.

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Monte Carlo simulation is performed with uniformly distributed U(0,1) pseudo-random numbers. Because the numbers are generated from a mathematical formula, they will contain some serial correlation, even if very small. This serial correlation becomes embedded in the correlation structure of the response variable. The response variable becomes an asynchronous time series. This leads to hidden errors in the response variable. The purpose of this paper is to illustrate how this happens and how it can be corrected. The method is demonstrated for the case of a simple queue for which the time in the

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Huang, Jian, Wu Wang, Yuzhu Wang, et al. "Performance Evaluation and Optimization of the Weather Research and Forecasting (WRF) Model Based on Kunpeng 920." Applied Sciences 13, no. 17 (2023): 9800. http://dx.doi.org/10.3390/app13179800.

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Abstract:

The Weather Research and Forecasting (WRF) model is a mesoscale numerical weather prediction system, which is widely used in major high-performance server platforms. This study focuses on the performance evaluation and optimization of WRF on Huawei’s self-developed kunpeng 920 processor platform, aiming to improve the operational efficiency of WRF. The results of the study show that the scalability of WRF on kunpeng 920 processor is well performed; the performance of WRF on kunpeng 920 processor is improved by 32.6% after invoking the Fast Math Library and Domain Decomposition Core Tile Divisi

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ARENDT, DUSTIN, and YANG CAO. "EFFECTIVE GPU ACCELERATION OF LARGE SCALE, ASYNCHRONOUS SIMULATIONS ON GRAPHS." Advances in Complex Systems 15, no. 08 (2012): 1250035. http://dx.doi.org/10.1142/s021952591250035x.

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The recent emergence of GPGPU programming has resulted in a number of very efficient, but ultimately ad-hoc implementations of GPU accelerated simulations of complex systems. Because developing applications for the GPU is still a difficult and time consuming task, efficient GPU parallelizations of general purpose modeling frameworks are very useful. The dimer automaton is a stochastic modeling and simulation framework with a good balance of robustness, generality, and simplicity with capacity to model a wide range of phenomena. A major advantage of dimer automata is the ease in which they can

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