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Ellis, David Lambert. "The reliability and efficiency of serial digital data in industrial communications." Thesis, Liverpool John Moores University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.247334.
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Lazarou, John. "Serial communications between personal computer and Unix." Virtual Press, 1989. http://liblink.bsu.edu/uhtbin/catkey/722455.
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A system is developed which facilitates communication between a Personal Computer and a Mainframe, and can do both directions, and lets the user execute Unix shell commands while the file transfer is in process. This communication system consists of two programs, one named "Thesis.EXE" that runs on a DOS based machine, and one named named "COMMGREEK" that runs on a Unix based machine.Department of Computer Science
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Nasser, Jamil. "Implementation of modern communication interfaces in systems with existing serial interface : EMBEDDED SYSTEMS, OIL MONITORING." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177805.
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Today’s robotics technology is often extremely user and location dependable, meaning that only a specific user using a specific hardware or software interface in a specific location can access that technique and alter it. This thesis focuses on an oil-monitoring system called Orilink, with those exact constraints. Orilink is only accessible through a specific computer using a serial port located in a special place. It is neither accessible from elsewhere nor through the cloud. This thesis removes that constraint and enables the access to Orilink independently of the user’s location or software / hardware interface.
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Baca, Dawnielle C. "DATA ACQUISITION, ANALYSIS, AND SIMULATION SYSTEM (DAAS)." International Foundation for Telemetering, 1994. http://hdl.handle.net/10150/608561.
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International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, CaliforniaThe Data Acquisition, Analysis, and Simulation System (DAAS) is a computer system designed to allow data sources on spacecraft in the Flight System Testbed (FST) to be monitored, analyzed, and simulated. This system will be used primarily by personnel in the Flight System Testbed, flight project designers, and test engineers to investigate new technology that may prove useful across many flight projects. Furthermore, it will be used to test various spacecraft design possibilities during prototyping. The basic capabilities of the DAAS involve unobtrusively monitoring various information sources on a developing spacecraft. This system also provides the capability to generate simulated data in appropriate formats at a given data rate, and to inject this data onto the communication line or bus, using the necessary communication protocol. The DAAS involves Serial RS232/RS422, Ethernet, and MIL-STD-1553 communication protocols, as well as LabVIEW software, VME hardware, and SunOS/UNIX operating systems.
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Guo, Fei. "Development of the real-time data acquisition system for Philips Patient Monitor." Case Western Reserve University School of Graduate Studies / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1405963966.
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Tan, Ronson K. "Design and analysis of an integrated-optical serial-to-parallel converter for high-data-rate communications." Diss., Georgia Institute of Technology, 1993. http://hdl.handle.net/1853/13382.
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Assaad, Maher. "Design and modeling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications." Thesis, University of Glasgow, 2009. http://theses.gla.ac.uk/707/.
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Abstract This thesis describes the design and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The proposed design was implemented and fabricated using the 130 nm CMOS technology offered by UMC (United Microelectronics Corporation). Different PLL-based CDR circuits topologies were investigated in terms of architecture and speed. Based on the investigation, we proposed a new concept of quarter-rate (i.e. the clocking speed in the circuit is 2.5 GHz for 10 Gb/s data rate) and dual-loop topology which consists of phase-locked and frequency-locked loop. The frequency-locked loop (FLL) operates independently from the phase-locked loop (PLL), and has a highly-desired feature that once the proper frequency has been acquired, the FLL is automatically disabled and the PLL will take over to adjust the clock edges approximately in the middle of the incoming data bits for proper sampling. Another important feature of the proposed quarter-rate concept is the inherent 1-to-4 demultiplexing of the input serial data stream. A new quarter-rate phase detector based on the non-linear early-late phase detector concept has been used to achieve the multi-Giga bit/s speed and to eliminate the need of the front-end data pre-processing (edge detecting) units usually associated with the conventional CDR circuits. An eight-stage differential ring oscillator running at 2.5 GHz frequency center was used for the voltage-controlled oscillator (VCO) to generate low-jitter multi-phase clock signals. The transistor level simulation results demonstrated excellent performances in term of locking speed and power consumption. In order to verify the accuracy of the proposed quarter-rate concept, a clockless asynchronous serial link incorporating the proposed concept and communicating two chips at 10 Gb/s has been modelled at gate level using the Verilog-A language and time-domain simulated.
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Zaklouta, Ahmadmunthar. "High-Speed Communication Scheme in OSI Layer 2 Research and Implementation." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254398.
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This thesis is part of a project at Bombardier’s Object Controller System. This system acts as a communication interface for several sub-systems that control the railway traffic. Therefore, part of the safety and availability of railway transportation is dependent on the performance and reliability of this system especially the digital communication system that handles the board-to-board communication. Thus, Bombardier has implemented new high-speed LVDS channels to use instead of the implemented RS-485 channels to improve the board-to-board communication performance in the Object Controller System but they lack a transceiver. This thesis work explores possible transceiver solutions that achieve Bombardier requirements. Reusability is very important for Bombardier for safety compliance and certification. Therefore, the investigation was carried out by looking into what is currently implemented and then was carried on by looking into transceivers that used in highspeed communication and check their suitability and compliance for the FPGA and the requirements. This exploration results in three experiments for different transceiver architecture. The first experiment exploits the currently implemented transceiver architecture and it is not suitable for high-speed data rate due to a limitation in the buffer. The second experiment overcomes the buffer limitation by using a clock domain crossing buffer and results in a 100-time faster system. The third experiment aimed to achieve a higher data rate by using a clock and data recovery transceiver and results in a promising solution but needs some enhancements. For testing, a verification methodology following the one-way stress test architecture has been developed using VHDL for simulation and for in-chip testing and the results were verified using ChipScope logic analyzer from Xilinx. In addition, a thermal test for the solution from the second experiment has been performed.Denna avhandling är en del av ett projekt på Bombardiers Object Controller System. Detta system fungerar som ett kommunikationsgränssnitt för flera delsystem som styr järnvägstrafiken. Därför är en del av säkerheten och tillgängligheten av järnvägstransporten beroende av systemets prestanda och tillförlitlighet, särskilt det digitala kommunikationssystemet som hanterar kommunikationen ombord. Bombardier har sålunda implementerat nya höghastighets LVDS-kanaler för att använda istället för de implementerade RS-485-kanalerna för att förbättra kommunikationsprestandan ombord i objektkontrollen, men de saknar en transceiver. Denna avhandling arbetar med att undersöka möjliga transceiverlösningar som uppnår Bombardier-krav. Återanvändbarhet är mycket viktigt för Bombardier för säkerhetsöverensstämmelse och certifiering. Undersökningen genomfördes därför genom att undersöka vad som för närvarande implementeras och sedan genomföras genom att titta på transceivers som används i höghastighetskommunikation och kontrollera deras lämplighet och överensstämmelse för FPGA och kraven. Denna undersökning resulterar i tre experiment för olika transceiverarkitektur. Det första experimentet utnyttjar den nuvarande implementerade transceiverarkitekturen. Den är inte lämplig för höghastighetsdatakommunikation på grund av en begränsning i bufferten. Det andra experimentet övervinns buffertbegränsningen genom att använda en klockdomänöverföringsbuffert vilket resulterar i ett 100-timmars snabbare system. Det tredje experimentet syftade till att uppnå en högre datahastighet genom att använda en klockoch dataåterställningstransceiver vilket resulterar i en lovande lösning men behöver vissa förbättringar. För testning har en verifieringsmetod som följer envägsstresstestarkitekturen utvecklats med hjälp av VHDL för simulering och för inchip-testning. Resultaten verifierades med hjälp av ChipScope logic analyzer från Xilinx. Dessutom har ett termiskt test för lösningen från det andra experimentet utförts.
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Zošiak, Dušan. "Analýza USB rozhraní." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217865.
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Tato práce je zaměřena na zpracování a analýzu USB komunikačního protokolu a implementace jeho jednotlivých částí do FPGA obvodu s využitím programovacího jazyka VHDL. Ve finální podobě by měla práce představovat souhrnný a ucelený dokument popisující principy USB rozhraní a jeho komunikace doplněných praktickým návrhem v jazyce VHDL, který by byl schopen převést data do USB.
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Engstrand, Johan. "A 3D-printed Fat-IBC-enabled prosthetic arm : Communication protocol and data representation." Thesis, Uppsala universitet, Fasta tillståndets elektronik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-420051.
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The aim of this thesis is to optimize the design of the Fat-IBC-based communication of a novel neuroprosthetic system in which a brain-machine interface is used to control a prosthetic arm. Fat-based intra-body communication (Fat-IBC) uses the fat tissue inside the body of the bearer as a transmission medium for low-power microwaves. Future projects will use the communication system and investigate ways to control the prosthetic arm directly from the brain. The finished system was able to individually control all movable joints of multiple prosthesis prototypes using information that was received wirelessly through Fat-IBC. Simultaneous transmission in the other direction was possible, with the control data then being replaced by sensor readings from the prosthesis. All data packets were encoded with the COBS/R algorithm and the wireless communication was handled by Digi Xbee 3 radio modules using the IEEE 802.15.4 protocol at a frequency of 2.45 GHz. The Fat-IBC communication was evaluated with the help of so-called "phantoms" which emulated the conditions of the human body fat channel. During said testing, packet loss measurements were performed for various combinations of packet sizes and time intervals between packets. The packet loss measurements showed that the typical amount of transmitted data could be handled well by the fat channel test setup. Although the transmission system was found to be well-functioning in its current state, increasing the packet size to achieve a higher granularity of the movement was perceived to be viable considering the findings from the packet loss measurements.
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Valent, Adam. "Jednosměrná sériová komunikace laserem na větší vzdálenost." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2021. http://www.nusl.cz/ntk/nusl-442524.
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The subject of this thesis is the construction of one-way communication device. This device consists of the transmitter and the receiver, both of which are connected to its respective computer via USB interface. This device allows sending UTF-8 characters or files from one computer to another. Both computers are running a graphical user interface program. The core of a transmitter is a digital signal modulating laser diode. The receiver is made of photovoltaic panel with a resonance circuit and an amplifier. Communication between the electronics and the computer is driven by microcontrollers. Received messages are verified with one of multiple error detection algorithms, which can be selected by user in the utility program.
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Rahmatdoustbeilankouh, Bahram. "Communication link and code conversion between Vehicle and smartphone for low speed semi-autonomous maneuvering." Thesis, Mittuniversitetet, Avdelningen för informations- och kommunikationssystem, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-26588.
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Something that has recently gained popularity in the leading car manufacturing companies is the integration of an auto-reverse assistance system to improve the customer experience. The undeniable spread of smartphones and their significant role in human life in recent years, gave rise to the idea of designing an application to be used for reverse driving. As a result, the car company Volvo proposed an idea for this project: to implement an Android based application to facilitate reverse navigation in their trucks. From a technical point of view, the most crucial obstacle that should be addressed is implementing a secure and reliable communication link between the smartphone and the truck's control centre. Hence, the primary goal of this thesis work is to provide a secure channel to transmit data and computing reliability of the com-munication link. Another objective of this project is to define a solution for auto-converting path plan function, currently developed in Matlab, to run on Android devices. In addition, this solution should enable the developer to modify the path plan function in Matlab without having to consider Android programming. The differential method has been proposed for transferring secure data transfer using Bluetooth technol-ogy. This solution not only increases the security of the communication link but also improves transmission time. Another objective has been reached by developing a middleware function using C programming language and Android Native Development Kite (NDK) between An-droid and Matlab. The result of these solutions provides a reliable communication link and runs the developed path plan function in Android phone.
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Hudec, David. "Generátor M2M dat bezdrátového protokolu Wireless M-BUS v SmartGrid." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2018. http://www.nusl.cz/ntk/nusl-376975.
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V rámci této práce byl vytvořen popis bezdrátového komunikačního protokolu Wireless M-Bus, zaměřující se zejména na datovou část tohoto protokolu, strukturu jeho informačních polí, režimy komunikace a další specifika linkové a aplikační vrstvy. Na základě tohoto výzkumu byl vytvořen softwarový nástroj v jazyce Java, sloužící jako generátor dat zmíněného protokolu. Pomocí grafického i textového uživatelského rozhraní program umožňuje uživateli vytvořit Wireless M-Bus telegramy s velmi vysokou úrovní detailu a ty následně s využitím některého z podporovaných hardwarových zařízení periodicky odesílat do Wireless M-Bus sítě. Dále byla navržena dvě kompletní řešení, využívající buď samotného bezdrátového IQRF modulu nebo jeho spojení s řídicí deskou UniPi Neuron. Oba návrhy byly zrealizovány, otestovány a jsou v práci detailně popsány.
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Andrade, Ricardo de. "Sistemas de comunicação CAN FD: modelamento por software e análise temporal." Universidade de São Paulo, 2014. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-06082015-111553/.
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O CAN (Controller Area Network) é um padrão no barramento de comunicação, amplamente difundido em aplicações industriais, particularmente em sistemas automotivos. Atualmente, um dos principais problemas no ramo automotivo é que esse barramento está com muitas mensagens no barramento, resultado da incorporação incremental de sistemas eletrônicos em automóveis, visto que há uma exigência maior de conectividade devido às exigências da sociedade e mercado. Como alternativa, vem sendo desenvolvida uma nova rede de comunicação, conhecida como CAN with Flexible Data-Rate (CAN-FD), que é um barramento com velocidade de transmissão de informação mais alta e maior capacidade de transporte de dados. Este projeto tem por objetivo principal explorar as funcionalidades da rede CAN-FD, através de simulações do trânsito de mensagens numa rede CAN-FD usando os dados de uma rede real CAN, e verificando a previsibilidade de ambas no âmbito de um protocolo que possa atender à demanda de sistemas complexos. A comparação é executada a partir de um conjunto de mensagens adicionadas na rede, para verificar os limites de transmissão de cada uma das redes, e os respectivos tempos de atraso das mensagens. Como um segundo estudo de caso, uma rede de controle em malha fechada foi desenvolvida, conectada a um barramento CAN e um barramento CAN-FD. Essa técnica de controle permitiu eliminar os ruídos que interferem no controle, e checar o limite em que o protocolo de comunicação consegue manter em uma malha de controle funcionando. Os resultados mostraram que é possível transmitir uma imensa quantidade de dados com o menor uso do busload (quantidade de mensagens transmitidas) no veículo através do uso do barramento CAN-FD, porém ainda não foi lançado no mercado um controlador do CAN-FD para realizar essa tarefa. Por outro lado, os dois protocolos, CAN-FD e CAN, tem suas previsibilidades comprometidas pois não conseguem enviar a mensagem quando o barramento está superior a 98,86% de carga.The CAN (Controller Area Network) is a standard in the communication bus, widespread in industrial applications, particularly in automotive systems. Currently, one of the main problems in the automotive industry is that this bus is with many messages on the bus, the result of incremental incorporation of electronic systems in automobiles, since there is a greater demand for connectivity due to the demands of society and the market. Alternatively, it has been developed a new communications network, known as CAN with Flexible Data-Rate (CAN-FD), which is a bus with transmission speeds higher and higher capacity data transport information. This project\'s main objective is to explore the features of the network CAN-FD, through simulations of the traffic of messages on a CAN network FD using data from a real CAN network, and verifying the predictability both in the context of a protocol that can meet the demand complex systems. The comparison is performed from a set of messages added to the network to verify the boundaries of each of the transmission networks and the respective delay times of the messages. As a second case study, a network of closed-loop control was developed, connected to a CAN bus and CAN bus FD. This control technique has eliminated the noises that interfere with the control and check the extent that the communication protocol can keep a control loop running. The results showed that it is possible to transmit a huge amount of data with the lowest usage busload (amount of transmitted messages) to the vehicle through the use of CAN bus FD, but not yet released to market a CAN controller FD to accomplish this task . Moreover, both protocols, CAN-FD and CAN has its predictability compromised because they are unable to send the message when the bus is more than 98.86% load.
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Smith, Stewart Gresty. "Serial-data computation in VLSI." Thesis, University of Edinburgh, 1987. http://hdl.handle.net/1842/11922.
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Staake, Thorsten R. "IP traffic statistics : a Markovian approach." Link to electronic thesis, 2002. http://www.wpi.edu/Pubs/ETD/Available/etd-0429102-123525.
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Sharma, Neena. "SERIAL PROTOCOL BRIDGE." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1352403332.
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Reinwald, Carl. "Augmenting Serial Streaming Telemetry with iNET Data Delivery." International Foundation for Telemetering, 2009. http://hdl.handle.net/10150/605967.
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ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, NevadaIncorporating network-based telemetry components into a flight test article creates new types of network-based data flows between a test article and a telemetry ground station. The emerging integrated Network Enhanced Telemetry (iNET) Standard defines new, network-based data delivery protocols which can produce various network data flows. Augmenting existing Serial Streaming Telemetry (SST) data flows with these network-based data flows is crucial to enhancing current flight test capabilities. This paper briefly introduces the network protocols referenced in the iNET Standard and then identifies the various data flows generated by network-based components which comply with the iNET Standard. Several combinations of SST and TmNS data flows are presented and the enhanced telemetry capabilities provided by each combination are identified. Identifying time intervals of unused telemetry network bandwidth explicitly for reallocation to other test articles is also addressed.
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Mattam, Swaroop. "A Synthesizable VHDL Model of the Serial Communication Interface and Synchronous Serial Interface of Motorola DSP56002." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7411.
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The design and implementation of a synthesizable model of the Serial Communication Interface and Synchronous Serial Interface, which constitutes the Port C of Motorola DSP56002 is presented in this report. They serves as a full duplex serial interface to other DSPs, processors, codecs, digital-to-analog and analog-to-digital converters and other transducers. The SCI block is able to handle a data rate of 5Mbps in Synchronous mode and 625Kbps in asynchronous mode for a 40MHz clock. It supports five word formats including a multidrop mode for multiprocessor systems. SSI provides a data rate of 10Mbps for the same 40 MHz clock. The design includes a programmable on-chip or external baud rate generator/interrupt timer for the SCI and a clock generator and frame Sync generator for the SSI.
The thesis focus on arriving at a full functional description of individual blocks included with Port C from the data sheets and product users manual. From this operational description a behavioural model was developed. The structure and implementation is based on the Motorola DSP56002 with additional support for a variable data-width. The model is written completely in behavioural VHDL with a top-down approach and the model was verified and validated.
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Darken, Patrick Fitzgerald. "Testing for Changes in Trend in Water Quality Data." Diss., Virginia Tech, 1999. http://hdl.handle.net/10919/28936.
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Time Series of water quality variables typically possess many of several characteristics which complicate analysis. Of interest to researchers is often the trend over time of the water quality variable. However, sometimes water quality variable levels appear to increase or decrease monotonically for a period of time then switch direction after some intervention affects the factors which have a causal relationship with the level of the variable. Naturally, when analyzed for trend as a whole, these time series usually do not provide significant results. The problem of testing for a change in trend is addressed, and a method for perfoming this test based on a test of equivalence of two modified Kendall's Tau nonparametric correlation coefficients (neither necessarily equal to zero) is presented. The test is made valid for use with serially correlated data by use of a new bootstrap method titled the effective sample size bootstrap. Further issues involved in applying this test to water quality variables are also addressed.Ph. D.
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Herbert, Malcolm James. "Computer-based serial section reconstruction of Earth Science data." Thesis, University of South Wales, 1995. https://pure.southwales.ac.uk/en/studentthesis/computerbased-serial-section-reconstruction-of-earth-science-data(411bdf61-1f0a-4533-b767-75a9c96abea0).html.
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This thesis documents a research project that has used computer graphics techniques to reconstruct a set of three-dimensional surfaces from a set of two-dimensional sectional drawings. The work has concentrated on the successful reconstruction of palaeontological specimens, such as brachiopods and early land plants. The reconstruction process is based around a two-stage system. First, the underlying topology of each object is determined automatically using the CorresGrow algorithm, which calculates the correspondence between adjacent sections, many of which have complex contour relationships. Unlike previous solutions, CorresGrow can locate solutions for objects that have multiple, disjoint components. The second stage triangulates the three-dimensional surface using the information provided by the correspondence algorithm. Depending on the similarity in shape of a pair of adjacent contours, the algorithm uses either the original contour vertices or those from the convex hull to perform the surface construction. The other aspects of the project work have looked at the implications of using computer graphics techniques for palaeontological reconstruction. This effects the way in which the data are sampled and digitised so that it is suitable for reconstruction. Using computer graphics also means that the reconstructed models can be used for more than visualisation, in areas such as evolutionary and temporal modelling.
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Nakane, Takanori. "Data processing pipeline for serial femtosecond crystallography at SACLA." Kyoto University, 2017. http://hdl.handle.net/2433/217997.
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Eriksson, Jens, and Kristian Nilsson. "Implementation of a Serial Communication Interface for a Signal Processor." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2029.
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The purpose of this thesis was to implement a serial communication port model for a digital signal processor. It is a behavioral model, developed using VHDL, that is instruction comparisable to the Motorola digital signal processor DSP 56002. It supports five different data transfer modes and provides a programmable baud rate generator.
This report starts out by giving a description of the external port, port C, the pin control logic and general purpose functionality. Then a more detailed description of the three pin dedicated serial communication interface is presented, the different operating modes and the baud rate generator are described.
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Badarinarayana, Terikere. "Logical simulation of communication subsystem for Universal Serial Bus (USB)." FIU Digital Commons, 2003. http://digitalcommons.fiu.edu/etd/1363.
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The primary purpose of this thesis was to design a logical simulation of a communication sub block to be used in the effective communication of digital data between the host and the peripheral devices. The module designed is a Serial interface engine in the Universal Serial Bus that effectively controls the flow of data for communication between the host and the peripheral devices with the emphasis on the study of timing and control signals, considering the practical aspects of them.
In this study an attempt was made to realize data communication in the hardware using the Verilog Hardware Description language, which is supported by most popular logic synthesis tools. Various techniques like Cyclic Redundancy Checks, bit-stuffing and Non Return to Zero are implemented in the design to provide enhanced performance of the module.
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Collins, Richard Paul. "Serial digital multiplexing of transducer data for intrinsically safe applications." Thesis, University of Southampton, 1990. https://eprints.soton.ac.uk/420619/.
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The galvanic isolation of fibre optic transmission offers a distinct advantage in the design of a telemetry system to meet intrinsic safety requirements. So far the usage of fibre optics in instrumentation systems has been largely confined to the implementation of point to point links due to the difficulties encountered in tapping into an optical fibre. Recent developments in the use of intelligence within instrumentation systems, however, have generally tended to concentrate on the concept of multiplexed signal paths. The aim of the work here has been to realise an intrinsically safe fibre optic multi-drop bus utilising an unbroken fibre as the transmission path. The technique employed involves the modulation of light within the fibre using an acoustic wave to vary the characteristics of a multi- mode fibre resulting in a differential phase modulation of the propagating modes. Since the system is unidirectional the use of two-way protocols is precluded and instead the method adopted uses the technique of allowing collisions of data to occur on the basis that they can be detected and the corrupted data can be subsequently ignored.
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Škrob, Robin. "Digitalizace snímaní rozložení optické intenzity." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217685.
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This Master’s thesis solves a design and construction of device for gathering and transfer of data into computer. The device should replace graph plotter, by which is measured the optical intensity of a laser beam. From this characteristic it is possible to determine other parameters of the laser beam, such as halfwidth of the beam, angle of divergence and Rayleigh length. The described device - “data gatherer” - measures two voltage values – voltage detected on photodiode and voltage detected on distance moved by photodiode. Measured values of voltage are processed and sent through a serial line into the computer. A pre-amplifier is connected to the control part for both channels of measured values with possibility of amplification. Computer application, which performs graphic interpretation of the measured values, serves as user control peripheral. The product of this project is compact device operating under OS Windows with graphic output.
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Ribler, Randy L. "Visualizing Categorical Time Series Data with Applications to Computer and Communications Network Traces." Diss., Virginia Tech, 1997. http://hdl.handle.net/10919/30314.
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Visualization tools allow scientists to comprehend very large data sets and to discover relationships which are otherwise difficult to detect. Unfortunately, not all types of data can be visualized easily using existing tools. In particular, long sequences of nonnumeric data cannot be visualized adequately. Examples of this type of data include trace files of computer performance information, the nucleotides in a genetic sequence, a record of stocks traded over a period of years, and the sequence of words in this document. The term categorical time series is defined and used to describe this family of data.
When visualizations designed for numerical time series are applied to categorical time series, the distortions which result from the arbitrary conversion of unordered categorical values to totally ordered numerical values can be profound. Examples of this phenomenon are presented and explained.
Several new, general purpose techniques for visualizing categorical time series data have been developed as part of this work and have been incorporated into the Chitra perfor- mance analysis and visualization system. All of these new visualizations can be produced in O(n) time. The new visualizations for categorical time series provide general purpose techniques for visualizing aspects of categorical data which are commonly of interest. These include periodicity, stationarity, cross-correlation, autocorrelation, and the detection of recurring patterns.
The effective use of these visualizations is demonstrated in a number of application domains, including performance analysis, World Wide Web traffic analysis, network routing simulations, document comparison, pattern detection, and the analysis of the performance of genetic algorithms.Ph. D.
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Fan, Yongquan. "Accelerating jitter and BER qualifications of high speed serial communication interfaces." Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=86531.
Full textAbstract:
High-Speed Serial Interface (HSSI) devices have witnessed an increased use in communications. As a measure of how often bit errors happen, Bit Error Rate (BER) performance is of paramount importance in any communication interface. The bit errors in HSSIs are in large part due to jitter. This thesis investigates the topic of accelerating the jitter and BER testing and characterization [1].The thesis first proposes a new algorithm, suitable for extrapolating the receiver jitter tolerance performance from higher BER regions down to the 10-12 level or lower [2]. This algorithm enables us to perform the jitter tolerance characterization and production test more than 1000 times faster [3]. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms [4] while the test usually takes seconds. All the receiver and transmitter testing schemes have been successfully used on Automatic Test Equipment (ATE) to qualify millions of HSSIs with speed up to 6 Gigabits per second (Gbps).
The thesis also presents an external loopback-based testing scheme, where a novel jitter injection technique is proposed using the state-of-the-art phase delay lines. The scheme can be applied to test HSSIs with data rate up to 12.5 Gbps. It is also suitable for multi-lane HSSI testing with a lower cost than pure ATE solutions. By using high-speed relays, we combine the proposed ATE based approaches and the loopback approach along with an FPGA-based BER tester to provide a more versatile scheme for HSSI post-silicon validation, testing and debugging [5]. In addition, we further explore the unparallel advantages of our digital Gaussian noise generator in low BER evaluation [6].
Les interfaces sérielles à haute vitesse (interfaces HSSI) ont connu une utilisation accrue dans les télécommunications. Le taux d'erreur sur les bits (BER), mesure de la fréquence des erreurs, est d'une importance cruciale dans les interfaces modernes de télécommunication. Cette thèse traite de l'accélération de la caractérisation du vacillement et des tests BER.
Cette thèse propose tout d'abord un nouvel algorithme, approprié pour l'extrapolation de la performance de la tolérance au vacillement d'un récepteur pour un taux d'erreur sur les bits (BER) à un niveau de 10-12 ou moins. Cet algorithme permet de caractériser la tolérance au vacillement dans les tests de production plus de 1000 fois plus rapidement. Ensuite, une conception de transmetteur à sous-échantillonnage est présenté. Cette conception permet d'extraire précisément le vacillement du transmetteur et de compléter les tests de ce dernier en moins de 100 ms alors que ces tests durent normalement plusieurs secondes. Toutes les méthodes de test de récepteurs et de transmetteurs ont été utilisées avec succès sur un équipement d'éssai automatique (ATE) pour qualifier des millions d'interfaces HSSI à des vitesses allant jusqu'à 6 gigabits par seconde (6 Gbps).
Cette thèse présente aussi une conception de test en bouclage où une nouvelle méthode d'injection de vacillement est proposée en utilisant des lignes de délai de phase. Cette méthode peut être appliquée pour tester des interfaces HSSI avec un taux de transfer allant jusqu'à 12.5 Gbps. Elle permet aussi de tester des interface HSSI multi-lignes à un coût moindre qu'une solution utilisant un ATE. En utilisant des relais à haute vitesse, les approches sur ATE et par test en bouclage peuvent être combinées en incorporant un testeur de BER sur circuit intégré prédiffusé programmable (FPGA), ce qui permet une méthode de tests HSSI polyvalente pour la validation post-fabrication, les tests et le débogage. Finalement, nous explorons les avantages de notre générateur de bruit Gaussien dans l'évaluation de BER à bas niveau.
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Fahmy, A. "Data encryption of communication data links." Thesis, University of Kent, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.385199.
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Ahmad, Saif. "A temporal pattern identification and summarization method for complex time serial data." Thesis, University of Surrey, 2007. http://epubs.surrey.ac.uk/843297/.
Full textAbstract:
Most real-world time series data is produced by complex systems. For example, the economy is a social system which produces time series of stocks, bonds, and foreign exchange rates whereas the human body is a biological system which produces time series of heart rate variations, brain activity, and rate of blood circulation. Complex systems exhibit great variety and complexity and so does the time series emanating from these systems. However, universal principles and tools seem to govern our understanding of highly complex phenomena, processes, and dynamics. It has been argued that one of the universal properties of complex systems and time series produced by complex systems is 'scaling'. The multiscale wavelet analysis shows promise to systematically elucidate complex dynamics in time series data at various timescales. In this research we investigate whether the wavelet analysis can be used as a universal tool to study the universal property of scaling in complex systems. We have developed and evaluated a wavelet time series analysis framework for automatically assessing the state and behaviour of complex systems such as the economy and the human body. Our results are good and support the hypothesis that 'scaling' is indeed a universal property of complex systems and that the wavelet analysis can be used as a universal tool to study it. We conclude that a system based on universal principles (e.g. 'scaling') and tools (e.g. wavelet analysis) is not only robust but also renders itself useful in diverse environments. Key words: Complex systems, scaling, time series analysis, wavelet analysis.
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Heath, Doug, Marty Polluconi, and Flora Samad. "LEVERAGING INTERNET PROTOCOL (IP) NETWORKS TO TRANSPORT MULTI-RATE SERIAL DATA STREAMS." International Foundation for Telemetering, 2006. http://hdl.handle.net/10150/603937.
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ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, CaliforniaAs the rates and numbers of serial telemetry data streams increase, the cost of timely, efficient and robust distribution of those streams increases faster. Without alternatives to traditional pointto- point serial distribution, the complexity of the infrastructure will soon overwhelm potential benefits of the increased stream counts and rates. Utilization of multiplexing algorithms in Field- Programmable Gate Arrays (FPGA), coupled with universally available Internet Protocol (IP) switching technology, provides a low-latency, time-data correlated multi-stream distribution solution. This implementation has yielded zero error IP transport and regeneration of multiple serial streams, maintaining stream to stream skew of less than 10 nsec, with end-to-end latency contribution of less than 15 msec. Adoption of this technique as a drop-in solution can greatly reduce the costs and complexities of maintaining pace with the changing serial telemetry community.
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Gunasekaren, Shankar. "A synthesizable verilog model of serial protocol engine for USB 1.1 device." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10182.
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USB has become a popular interface for exchanging data between PC’s and peripherals. An increasing number of portable peripherals are using the USB interface to communicate with the PC.The design and implementation of a synthesizable model of the USB 1.1 protocol engine is presented in this report The PHY is compatible with the USB 1.1 transceiver macrocell interface (UTMI) specification and the simulation test confirmed the successful operation of circuits for both full speed (12 Mbps) and low speed (1.5 Mbps) data transmission. the model is written completely in behavioral verilog with a top down approach and the model was verified and validated.
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Bilgic, Kemal Onder. "Aerial Acoustic Data Communication." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614651/index.pdf.
Full textAbstract:
Spectrum has been a scarce commodity in RF communication. Acoustic data communication
is an alternative to RF communication where data is transmitted through sound waves.
In this thesis, several different aspects of acoustic data communication are investigated. A
physical test setup is built where the data communication spectrum extends up to 40 kHz.
Impulse response of the acoustic channel is considered in a laboratory environment. Acoustic
spectrum beyond the hearing limit between 25 kHz to 35 kHz is found as a suitable band for
the developed setup. Distance and multipath components are important factors, determining
the communication accuracy. The physical layer for the communication system is built by
taking RF Pager system as a reference. This system is also modified to improve the performance.
Dierent modulation techniques are used in order to evaluate their performances
for acoustic channels. BFSK, BPSK, QPSK, GMSK, OFDM, DSSS and FHSS techniques
are implemented for comparison. Total and effective bit rate are considered for the overall
performance evaluation of differentt modulation techniques. Several experiments are done in
laboratory environment where there are several multipath components. As the distance between
the transmitter and receiver is increased, path loss and multipath increases. It is shown
that certain modulation techniques are more robust to multipath and are better candidates for acoustic communication. While acoustic environment is inefficient in terms of power, it is
still a good candidate for communication in short distances.
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Link, Jeffrey P. "Design of a serial communication protocol and bus interface chip for tactile communications." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1999. http://handle.dtic.mil/100.2/ADA362194.
Full textAbstract:
Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 1999.Thesis advisor(s): Douglas J. Fouts. "March 1999". Includes bibliographical references (p. 285). Also available online.
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Cheng, Shanfeng. "Design of CMOS integrated phase-locked loops for multi-gigabits serial data links." Texas A&M University, 2006. http://hdl.handle.net/1969.1/4954.
Full textAbstract:
High-speed serial data links are quickly gaining in popularity and replacing the
conventional parallel data links in recent years when the data rate of communication
exceeds one gigabits per second. Compared with parallel data links, serial data links are
able to achieve higher data rate and longer transfer distance. This dissertation is focused on
the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks
used in multi-gigabits serial data link transceivers.
Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are
modeled and analyzed. The steady-state behavior of BPLLs is derived with combined
discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs
are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC-
192, the mainstream standard for optical serial data links, is presented. The CDR is based
on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked
loop based on a quad-level phase detector and a linear frequency-locked loop based on a
linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in
0.18 üm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter
generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance
exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential
divide-by-eight injection-locked frequency divider with low power dissipation is presented.
The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It
has a maximum operating frequency of 18 GHz. The ratio of locking range over center
frequency is up to 50%. The prototype chip is implemented in 0.18 üm CMOS technology
and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques
of fully differential charge pumps are discussed. Techniques are proposed to minimize the
nonidealities associated with a fully differential charge pump, including differential
mismatch, output current variation, low-speed glitches and high-speed glitches. The
performance improvement brought by the techniques is verified with simulations of
schematics designed in 0.35 üm CMOS technology.
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Giannuzzi, Fabio <1986>. "General-Purpose Data Acquisition Cards Based on FPGAs and High Speed Serial Protocols." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2016. http://amsdottorato.unibo.it/7519/.
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This thesis exhibits the results of my PhD Apprenticeship Program, carried out at the “Marposs S.p.a.” firm, in the electronic research division, and at the Department of Physics and Astronomy of the Bologna University, in the INFN's electronics laboratories of the ATLAS group.
During these three years of research, I worked on the development and realization of electronic boards dedicated to flexible data acquisition, designed to be applied in several contexts, that need to share high performance FPGAs and high-speed serial communications. The thesis describes the successful application of high-speed configurable electronic devices to two different fields, firstly developed in the particle physics scenario, and then the industrial measurement of mechanical pieces, reaching the main goal of the PhD Apprenticeship Program.
The common denominator is the development of high speed electronics based on FPGAs for demanding data acquisition and data processing applications.
The thesis describes the contribution to the luminosity monitor of LHC at CERN and illustrates a multi-camera system developed for automatic inspection of mechanical pieces made by a machine tool.
The Apprenticeship Program allowed me to continue my academic course in parallel with my working activity, giving me the opportunity to finalize the project started during my internship and thesis for my master degree.
It also allowed me to achieve a higher level in education and training in two different contexts of excellence, i.e. the industrial company and the academic research, where I concretely learned the best technical knowledge. The chance of bringing together two distant worlds was the most enthusiastic aspect of this PhD research. The world of industry and academic research face similar problems but with different points of view and goals. I had the opportunity to explore pure academic research, and also to apply the knowledge acquired in these years to the industrial research.
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Robinson, J. A. "Low data-rate visual communication." Thesis, University of Essex, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.354010.
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Park, Hyoung-June. "Formalization, data abstraction, and communication." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/69376.
Full textAbstract:
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Architecture, 1997.Includes bibliographical references (leaves 109-111).
Shape Grammar introduces the algorithm that stimulates the development of form and its meaning in the design process. Since Shape Grammar provides a way of representing form and its meaning as sets of mathematical terms, which are shapes and the different algebra, Shape Grammar has been anticipated for developing an architect's design idea with a computer-aided system. However, its application has been limited in the theoretical analysis of the historical precedents in architecture. Thus, a study of the practical application of Shape Grammar is needed in order to make creative design, in the actual design process, using a CAD system, possible. Through the experimentation with "making follY," this thesis introduces a model for the application of Shape Grammar to the architectural design process. It presents theoretical foundations, describes the methods of formalization, data abstraction, and communication with Shape Grammar in making designs, and illustrates the process of making folly as the result of this thesis. The approach is derived from the study of the different definitions of architectural form and the observation that architects explore formal ideas by producing sequences of drawings, which are schema(s). This thesis investigates possible methods of formalization and data-abstraction based upon schema(s) in the architectural design. Also, this thesis proposes the framework for a prototype computer system that efficiently supports the communication between different computational tools. This communication is established by encoding the design process as the result of the data abstraction, which is composed of shapes as mathematical means, and formalizing the architect's design knowledge according to certain compositional rules. Then, an experiment with "Folly"l design is performed, based upon the suggested methods for the application of Shape Grammar. In conclusion, based upon the results of the experimentation, the initial territory, spatial block, and spatial components in the combination between different algebra are proposed as design methods for the application of Shape Grammar in the making of a creative design. Also, existing problems in the making of practical software are introduced.
by Park, Hyoung-June.
M.S.
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Yoneki, Eiko. "ECCO : data centric asynchronous communication." Thesis, University of Cambridge, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.612757.
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Rudraraju, VRS Raju. "Ultrasonic Data Communication through Petroleum." University of Akron / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=akron1271703312.
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Hoyt, Matthew Ray. "Automatic Tagging of Communication Data." Thesis, University of North Texas, 2012. https://digital.library.unt.edu/ark:/67531/metadc149611/.
Full textAbstract:
Globally distributed software teams are widespread throughout industry. But finding reliable methods that can properly assess a team's activities is a real challenge. Methods such as surveys and manual coding of activities are too time consuming and are often unreliable. Recent advances in information retrieval and linguistics, however, suggest that automated and/or semi-automated text classification algorithms could be an effective way of finding differences in the communication patterns among individuals and groups. Communication among group members is frequent and generates a significant amount of data. Thus having a web-based tool that can automatically analyze the communication patterns among global software teams could lead to a better understanding of group performance. The goal of this thesis, therefore, is to compare automatic and semi-automatic measures of communication and evaluate their effectiveness in classifying different types of group activities that occur within a global software development project. In order to achieve this goal, we developed a web-based component that can be used to help clean and classify communication activities. The component was then used to compare different automated text classification techniques on various group activities to determine their effectiveness in correctly classifying data from a global software development team project.
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Acharya, Debopam Kumar Vijay. "Data in your space a data staging and push pull based location dependent wireless data dissemination system /." Diss., UMK access, 2006.
Find full textAbstract:
Thesis (Ph. D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2006."A dissertation in computer science and informatics and telecommunications and computer networking." Advisor: Vijay Kumar. Typescript. Vita. Title from "catalog record" of the print edition Description based on contents viewed Jan. 26, 2007. Includes bibliographical references (leaves 115-120). Online version of the print edition.
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Bien, Franklin Young-Jae. "Reconfigurable equalization for 10-Gb/sec serial data links in a 0.18-μm CMOS technology." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14026.
Full textAbstract:
The objective of the proposed research is to realize a 10-Gb/sec serial data link over band-limited channels, such as backplanes, multi-mode fiber, and copper-based cables that were originally designed for data rates less than 1Gb/sec. This is achieved using electrical equalization implemented in an integrated circuit (IC). To successfully compensate for various band-limited channels at the targeted data rate with a single equalizer IC, a reconfigurable equalizer topology is proposed.
In order to realize the proposed goal, various channels are characterized of their forward transmission frequency response. Based on the measured channel data, system simulations are performed to identify the required specifications for IC implementation. This provides information such as optimal number of taps, fractionally-spaced tap delay, and tap coefficients for the proposed IC. With the obtained system requirements, IC building blocks are designed and fabricated in a 0.18- and #956;m CMOS technology.
The fully-integrated reconfigurable CMOS equalizer provides a single-chip solution for compensating various band-limited channels. This enables 10-Gb/sec serial data transmission achieving signal integrity beyond their designed specifications.
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Liu, Xinyang. "Data acquisition via RS-232 and universal serial bus from a field programmable gate array." Thesis, Monterey, California : Naval Postgraduate School, 2009. http://edocs.nps.edu/npspubs/scholarly/theses/2009/Dec/09Dec%5FLiu_Xingyang.pdf.
Full textAbstract:
Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2009.Thesis Advisor: Julian, Alexander L. Second Reader: Cristi, Roberto. "December 2009." Description based on title screen as viewed on January 27, 2010. Author(s) subject terms: RS-232, USB, FPGA. Includes bibliographical references (p. 51-52). Also available in print.
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Odirile, Shumie T. "Mareledi: An Audience-Reception Study of an HIV/AIDS Entertainment-Education Serial Television Drama in Botswana." Ohio University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1461322756.
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McGinty, Nigel, and nigel mcginty@defence gov au. "Reduced Complexity Equalization for Data Communication." The Australian National University. Research School of Information Sciences and Engineering, 1998. http://thesis.anu.edu.au./public/adt-ANU20050602.122741.
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Optimal decision directed equalization techniques for time dispersive communication channels are often too complex to implement. This thesis considers reduced complexity decision directed equalization that lowers complexity demands yet retains close to optimal performance. The first part of this dissertation consists of three reduced complexity algorithms based on the Viterbi Algorithm (VA) which are: the Parallel Trellis VA (PTVA); Time Reverse Reduced State Sequence Estimation (TR-RSSE); and Forward-Backward State Sequence Detection (FBSSD). The second part of the thesis considers structural modifications of the Decision Feedback Equalizer (DFE), which is a special derivative of the VA, specifically, optimal vector quantization for fractionally spaced DFEs, and extended stability regions for baud spaced DFEs using passivity analysis are investigated.¶
For a special class of sparse channels the VA can be decomposed over a number of independent parallel trellises. This decomposition will be called the Parallel Trellis Viterbi Algorithm and can have lower complexity than the VA yet it retains optimal performance. By relaxing strict sparseness constraints on the channel a sub-optimal approach is proposed which keeps complexity low and obtains good performance.¶
Reduced State Sequence Estimation (RSSE) is a popular technique to reduce complexity. However, its deficiency can be the inability to adequately equalize non-minimum phase channels. For channels that have energy peaks in the tail of the impulse response (post-cursor dominant) RSSE's complexity must be close to the VA or performance will be poor. Using a property of the VA which makes it invariant to channel reversal, TR-RSSE is proposed to extend application of RSSE to post-cursor dominant channels.¶
To further extend the class of channels suitable for RSSE type processing, FBSSD is suggested. This uses a two pass processing method, and is suited to channels that have low energy pre and post-cursor. The first pass generates preliminary estimates used in the second pass to aid the decision process. FBSSD can range from RSSE to TR-RSSE depending on parameter settings.¶
The DFE is obtained when the complexity of RSSE is minimized. Two characterizing properties of the DFE, which are addressed in this thesis, are feedback and quantization. A novel fractionally spaced (FS) DFE structure is presented which allows the quantizer to be generalized relative to the quantizer used in conventional FS-DFEs. The quantizer can be designed according to a maximum a posteriori criterion which takes into account a priori statistical knowledge of error occurrences. A radically different quantizer can be obtained using this technique which can result in significant performance improvements.¶
Due to the feedback nature of the DFE a form of stability can be considered. After a decision error occurs, a stable DFE will, after some finite time and in the absence of noise, operate error free. Passivity analysis provides sufficient conditions to determine a class of channels which insures a DFE will be stable. Under conditions of short channels and small modulation alphabets, it is proposed that conventional passivity analysis can be extended to account for varying operator gains, leading to weaker sufficient conditions for stability (larger class of channels).
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Yang, Yuping. "Personalized redirection of communication and data." Thesis, Heriot-Watt University, 2004. http://hdl.handle.net/10399/315.
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Stetenfeldt, Andreas. "Data communication for near shore applications." Thesis, Uppsala universitet, Elektricitetslära, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-330936.
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The wave energy conversion concept developed at Uppsala University is based on a buoy at sea level that is connected to a linear generator on the sea bed. The movements of the buoy riding the waves gets converted into electricity by the reciprocal movements of the translator inside the generator. To be able to compensate the negative impact of water level variations on power production, which is especially important at sites with high tidal range, a sea level compensation system to be placed on the buoy was developed. During development, the system used cellphone technology to communicate, which can be power demanding and is dependent on adequate cellphone reception. Since future wave power parks could be localized up to 10 km offshore, in rural areas of developing countries, a new approach is needed for communication with the sea level compensation system that is not dependent on cellphone reception at sea. In this report, a review of the regulations for radio communication and radio equipment in Sweden, Spain, Nigeria, Ghana and India is presented together with research of different possibilities of communication. Moreover, a new system for sending commands and receiving telemetry have been developed and have been tested for basic functionality, range and power efficiency. Due to differences in the countries regulations and uncertainties about conditions at the future sites of deployment, the programs in the system are to be easily adapted to function with different radios depending on the country of interest and the conditions at the site. Hence, a system layout have been proposed rather than a specific communication solution. The experimental setup developed has been tested over land with license free radios, over a range of 10 km in the vicinity of Uppsala. In the test, 100% of the transmitted commands were received and acknowledged within three attempts. The new control system for the buoys reduced the energy consumption from the previous development system by 90%.
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Bestepe, Firat. "Microcontroller-based Multiport Communication System For Digital Electricity Meters." Master's thesis, METU, 2004. http://etd.lib.metu.edu.tr/upload/12605765/index.pdf.
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This thesis explains the design of a microcontroller-based device, which provides an efficient and practical alternative for the remote reading of digital electricity meters over Public Switch Telephone Network (PSTN). As an alternative application, a system is constructed providing file transfer capability to the PC connected to the port of implemented device in addition to remote reading of digital electricity meters. This thesis also provides detailed explanations about
the basics of serial asynchronous communication over modem for PICs (peripheral interface controllers) together with description of each component included by the constructed system, which can be used in energy metering sector commonly.
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Yih-Horng, Lin, and 林奕宏. "An Oversampling Data Recovery Receiver for Serial Link Communications." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/54153654508551040100.
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碩士輔仁大學
電子工程學系
91
This thesis investigates an oversampling architecture for high-speed data recovery in serial link communications, which it provides another alternative in addition to the conventional clock/data extraction approach. By taking advantage of the All-Digital Phase-Locked Loop (ADPLL) receiver with the oversampling technique and digital signal algorithms, we can simplify data recovery processes. The receiver comprises a four-time data oversampler to sample received bits, and a parallel byte-level architecture to reduce the complexity of the system clock configuration. According to the communication protocol, the detection of a sampled datum can generate control signals for all of the circuit blocks. The majority voting method and aligner mechanism overcome the clock asynchronous problems. The collective shifter and register file block solve frequency deviation between transmitter and receiver. Finally, adopting parallel processing skill accomplishes NRZI (Non-Return-to-Zero Inverted) decoding procedure which is popular in the state-of-the-art high-speed serial link. The regular architecture is suitable for the integrated circuit implementation. Moreover, the oversampling receiver does increase the data drift tolerance from the cell-based design flow and the CPLD (Complex Programmable Logic Device) emulation. It conforms to the demand in high-speed communications.