Academic literature on the topic 'Set-Associative'
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Journal articles on the topic "Set-Associative"
Hwang, Yuan-Shin, and Jia-Jhe Li. "Snug set-associative caches." ACM Transactions on Architecture and Code Optimization 4, no. 1 (March 2007): 6. http://dx.doi.org/10.1145/1216544.1216549.
Full textKang, J., S. Lee, and I. Lee. "Way-tracking set-associative caches." Electronics Letters 46, no. 22 (2010): 1497. http://dx.doi.org/10.1049/el.2010.8526.
Full textSubha, S. "An Energy Efficient Set Associative Cache Algorithm." International Journal of Computer Applications 68, no. 14 (April 18, 2013): 12–15. http://dx.doi.org/10.5120/11646-7137.
Full textHarper, J. S., D. J. Kerbyson, and G. R. Nudd. "Analytical modeling of set-associative cache behavior." IEEE Transactions on Computers 48, no. 10 (1999): 1009–24. http://dx.doi.org/10.1109/12.805152.
Full textMarjan Gusev, and Sasko Ristov. "Performance Gains and Drawbacks using Set Associative Cache." Journal of Next Generation Information Technology 3, no. 3 (August 31, 2012): 87–98. http://dx.doi.org/10.4156/jnit.vol3.issue3.9.
Full textSugumar, Rabin A., and Santosh G. Abraham. "Set-associative cache simulation using generalized binomial trees." ACM Transactions on Computer Systems 13, no. 1 (February 1995): 32–56. http://dx.doi.org/10.1145/200912.200918.
Full textFraguela, Basilio B., Ramón Doallo, and Emilio L. Zapata. "Modeling set associative caches behavior for irregular computations." ACM SIGMETRICS Performance Evaluation Review 26, no. 1 (June 1998): 192–201. http://dx.doi.org/10.1145/277858.277910.
Full textKoh, Cheng-Kok, Weng-Fai Wong, Yiran Chen, and Hai Li. "Tolerating process variations in large, set-associative caches." ACM Transactions on Architecture and Code Optimization 6, no. 2 (June 2009): 1–34. http://dx.doi.org/10.1145/1543753.1543757.
Full textYAKTINE, UMAYMA S. "ASSOCIATIVE AND SET LEARNING IN SEVERELY SUBNORMAL PATIENTS." Journal of Intellectual Disability Research 9, no. 2 (June 28, 2008): 83–88. http://dx.doi.org/10.1111/j.1365-2788.1965.tb00824.x.
Full textCalagos, M., and Y. Chu. "Hybrid scheme for low-power set associative caches." Electronics Letters 48, no. 14 (2012): 819. http://dx.doi.org/10.1049/el.2012.1434.
Full textDissertations / Theses on the topic "Set-Associative"
Simons, Brad, and Brad Simons. "Set-Associative History-Aided Adaptive Replacement for On-Chip Caches." Thesis, The University of Arizona, 2016. http://hdl.handle.net/10150/621128.
Full textRivera, Roberto Rafael. "On properties of completely flexible loops." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/28841.
Full textGUPTA, GAURAV. "DESIGN AND ANALYSIS OF A LOW POWER SET-ASSOCIATIVE CACHE USING PARTIAL TAG COMPARISON." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1140818310.
Full textNagpal, Radhika. "Store Buffers : implementing single cycle store instructions in write-through, write-back and set associative caches." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36678.
Full textIncludes bibliographical references (p. 87).
This thesis proposes a new mechanism, called Store Buffers, for implementing single cycle store instructions in a pipelined processor. Single cycle store instructions are difficult to implement because in most cases the tag check must be performed before the data can be written into the data cache. Store buffers allow a store instruction to read the cache tag as it. passes through the pipe while keeping the store instruction data buffered in a backup register until the data cache is free. This strategy guarantees single cycle store execution without increasing the hit access time or degrading the performance of the data cache for simple direct-mapped caches, as well as for more complex set associative and write-back caches. As larger caches are incorporated on-chip, the speed of store instructions becomes an increasingly important part of the overall performance. The first part of the thesis describes the design and implementation of store buffers in write through, write-back, direct-mapped and set associative caches. The second part describes the implementation and simulation of store buffers in a 6-stage pipeline with a direct mapped write-through pipelined cache. The performance of this method is compared to other cache write techniques. Preliminary results show that store buffers perform better than other store strategies under high IO latencies and cache thrashing. With as few as three buffers, they significantly reduce the number of cycles per instruction.
by Radhika Nagpal.
B.S.and M.S.
Eng, Stefan. "Heuristisk profilbaserad optimering av instruktionscache i en online Just-In-Time kompilator." Thesis, Linköping University, Department of Computer and Information Science, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2452.
Full textThis master’s thesis examines the possibility to heuristically optimise instruction cache performance in a Just-In-Time (JIT) compiler.
Programs that do not fit inside the cache all at once may suffer from cache misses as a result of frequently executed code segments competing for the same cache lines. A new heuristic algorithm LHCPA was created to place frequently executed code segments to avoid cache conflicts between them, reducing the overall cache misses and reducing the performance bottlenecks. Set-associative caches are taken into consideration and not only direct mapped caches.
In Ahead-Of-Time compilers (AOT), the problem with frequent cache misses is often avoided by using call graphs derived from profiling and more or less complex algorithms to estimate the performance for different placements approaches. This often results in heavy computation during compilation which is not accepted in a JIT compiler.
A case study is presented on an Alpha processor and an at Ericsson developed JIT Compiler. The results of the case study shows that cache performance can be improved using this technique but also that a lot of other factors influence the result of the cache performance. Such examples are whether the cache is set-associative or not; and especially the size of the cache highly influence the cache performance.
Ponnala, Kalyan. "DESIGN AND IMPLEMENTATION OF THE INSTRUCTION SET ARCHITECTURE FOR DATA LARS." UKnowledge, 2010. http://uknowledge.uky.edu/gradschool_theses/58.
Full textLi, Sy-Yuan, and 李斯元. "Set-Associative Load-Store Caches." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/01136642695130656933.
Full text國立臺灣海洋大學
資訊工程學系
95
The conventional load/store queue (LSQ) is a CAM structure where a dynamically-scheduled processor stores all in-flight memory instructions and conducts fully associative, age-prioritized searches to maintain dependencies and perform forwarding. LSQ is neither efficient since previous studies have shown that dependency violations are infrequent, nor scalable due to the complexity of the CAM. This paper presents an efficient and scalable alternative to the LSQ, called the set-associative load/store cache (LSC), that replaces the CAM with a set-associative tag array. It is analogous to substituting a set-associative cache for a fully associative cache, since the tag bit cell of a fully-associative array is a CAM. As it has been observed that set-associative caches can significantly reduce tag comparisons while approximating the miss rates of fully associative caches, LSC can substantially lessen the search bandwidth demand without incurring noticeable performance degradation due to stalls caused by set conflicts. Experimental results of SPECint2000 benchmarks show that both a 32-entry and a 128-entry 4-way set-associative LSC can significantly reduce the search bandwidth demand with no visible performance penalties, while a 128-entry L0 LSC can improve the average execution times by 3%.
Wu, Dong-Hua, and 吳東樺. "SALSC: Set-Associative Load/Store Caches." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/72199186710102839427.
Full text國立臺灣科技大學
資訊工程系
98
The conventional load/store queue (LSQ) is a CAM structure where a dynamically-scheduled processor stores all in-flight memory instructions and conducts fully associative, ordering-logic searches to maintain dependencies and perform forwarding. LSQ is neither efficient since previous studies have shown that dependency violations are infrequent, nor scalable due to the complexity of the CAM. This paper presents an efficient and scalable alternative to the LSQ, called the set-associative load/store cache (SALSC), that replaces the CAM with a set-associative tag array. It is analogous to substituting a set-associative cache for a fully associative cache, since the tag bit cell of a fully-associative array is a CAM. As it has been observed that set-associative caches can significantly reduce tag comparisons while approximating the miss rates of fully associative caches, SALSC can substantially lessen the search bandwidth demand without incurring noticeable performance degradation due to stalls caused by set conflicts. Furthermore, an SALSC can be viewed as a set-associative cache integrated with an age logic, and hence it is a natural and straightforward extension to treat an SALSC as an L0 cache by buffering data of memory references in the entries. Experimental results of SPECint2000 benchmarks show that both a 32-entry and a 128-entry 4-way SALSC can significantly reduce the search bandwidth demand with no visible performance penalties, while a 128-entry L0 SALSC can improve the average execution times by 0.22%.
張延任. "Efficient Simulation Alogorithm for Set-Associative Victim Cache Memory." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/81639848375032088617.
Full text中原大學
資訊工程學系
85
Trace-driven simulation is the most commonly used technique for evaluating the behavior of a cache memory system. Prior to this investigation, all simulation algorithms were aimed at the conventional cache architecture without any extra device. This paper presents 1) more efficient and easier one-pass algorithm for simulating alternative all-associativity (i.e. direct-mapped and set-associative) cache than early ones, 2) new and powerful one-pass algorithm for simulating alternative all-associativity caches with a victim cache of different entry member, and 3) uses those simulation results to compare set-associative caches and direct-mapped caches with a small victim cache from various aspect. First, we propose a more efficient algorithm, called hash-like RM simulation, for simulating alternative caches with the same block size, and using the LRU replacement policy, with a single pass through an address trace. This algorithm facilitates more rapid simulation of alternative caches by reducing the average search depth in fully stack. And further, we develop a powerful algorithm, victim one-pass simulation, for simulating alternative caches with a victim cache (buffer) of different entry number in one pass. Since the behavior of victim cache is detrimental to one-pass simulation, this algorithm is more complicated than those for simulating memory system without victim cache. Finally, our experimental data provide evidence that adding a victim cache is worthless for direct-mapped instruction caches with size more than 32K, but 64K direct-mapped data caches with a 4-6 entries victim cache can compete in miss ratios with those of 64K 2-way set-associative caches and have the more superior average memory access time.
Ting, Chih-Hui, and 丁之暉. "Sequential Way-Access Set-Associative Cache Architecture for Low Power." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/96132699768891504787.
Full textBooks on the topic "Set-Associative"
García, Miguel Cabrera, and Ángel Rodríguez Palacios. Non-Associative Normed Algebras 2 Volume Hardback Set. Cambridge University Press, 2018.
Find full textHardy, Duncan. The Age of Imperial Reform, c. 1486–1521. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198827252.003.0013.
Full textHenderson, Andrea. Algebra. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198809982.003.0003.
Full textBook chapters on the topic "Set-Associative"
Doallo, Ramón, Basilio B. Fraguela, and Emilio L. Zapata. "Set Associative Cache Behavior Optimization⋆." In Euro-Par’99 Parallel Processing, 229–38. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/3-540-48311-x_28.
Full textVolna, Eva, and Martin Kotyrba. "Guaranteed Training Set for Associative Networks." In Recent Advances in Soft Computing, 136–46. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-58088-3_13.
Full textSanders, Peter. "Accessing Multiple Sequences Through Set Associative Caches." In Automata, Languages and Programming, 655–64. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/3-540-48523-6_62.
Full textKannan, Megalingam Rajesh, K. B. Deepu, Joseph P. Iype, Ravishankar Parthasarathy, and Popuri Gautham. "Power Consumption Analysis of Direct, Set Associative and Phased Set Associative Cache Organizations in Alpha AXP 21064 Processor." In Communications in Computer and Information Science, 114–19. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-12214-9_20.
Full textHarper, John S., Darren J. Kerbyson, and Graham R. Nudd. "Efficient analytical modelling of multi-level set-associative caches." In High-Performance Computing and Networking, 473–82. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/bfb0100608.
Full textHu, Zhigang, Stefanos Kaxiras, and Margaret Martonosi. "Improving Power Efficiency with an Asymmetric Set-Associative Cache." In High Performance Memory Systems, 79–96. New York, NY: Springer New York, 2004. http://dx.doi.org/10.1007/978-1-4419-8987-1_6.
Full textKeramidas, Georgios, Polychronis Xekalakis, and Stefanos Kaxiras. "Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches." In Transactions on High-Performance Embedded Architectures and Compilers II, 4–22. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-00904-4_2.
Full textFujii, Seiichiro, and Toshinori Sato. "Non-uniform Set-Associative Caches for Power-Aware Embedded Processors." In Embedded and Ubiquitous Computing, 217–26. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30121-9_21.
Full textKeramidas, Georgios, Polychronis Xekalakis, and Stefanos Kaxiras. "Applying Decay to Reduce Dynamic Power in Set-Associative Caches." In High Performance Embedded Architectures and Compilers, 38–53. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-69338-3_4.
Full textYun, SangKyun. "Hardware-Based IP Lookup Using n-Way Set Associative Memory and LPM Comparator." In Lecture Notes in Computer Science, 406–14. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11796435_41.
Full textConference papers on the topic "Set-Associative"
Li, Jia-Jhe, and Yuan-Shin Hwang. "Snug set-associative caches." In the 2005 international symposium. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1077603.1077687.
Full textSubha, S. "A Set Associative Cache Architecture." In 2010 Seventh International Conference on Information Technology: New Generations. IEEE, 2010. http://dx.doi.org/10.1109/itng.2010.130.
Full textJanraj, C. J., T. Venkata Kalyan, Tripti Warrier, and Madhu Mutyam. "Way Sharing Set Associative Cache Architecture." In 2012 25th International Conference on VLSI Design. IEEE, 2012. http://dx.doi.org/10.1109/vlsid.2012.79.
Full textRodda, Sireesha, and M. Shashi. "A Rough Set Based Associative Classifier." In International Conference on Computational Intelligence and Multimedia Applications (ICCIMA 2007). IEEE, 2007. http://dx.doi.org/10.1109/iccima.2007.297.
Full textLiang, Yun, and Tulika Mitra. "Improved procedure placement for set associative caches." In the 2010 international conference. New York, New York, USA: ACM Press, 2010. http://dx.doi.org/10.1145/1878921.1878944.
Full textSubha, S. "A Set Associative Cache Model with Energy Saving." In 2008 Fifth International Conference on Information Technology: New Generations (ITNG). IEEE, 2008. http://dx.doi.org/10.1109/itng.2008.46.
Full textFraguela, Basilio B., Ramón Doallo, and Emilio L. Zapata. "Modeling set associative caches behavior for irregular computations." In the 1998 ACM SIGMETRICS joint international conference. New York, New York, USA: ACM Press, 1998. http://dx.doi.org/10.1145/277851.277910.
Full textHanna, Michel, Socrates Demetriades, Sangyeun Cho, and Rami Melhem. "Progressive hashing for packet processing using set associative memory." In the 5th ACM/IEEE Symposium. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1882486.1882521.
Full textRashid, Syed Aftab, Geoffrey Nelissen, and Eduardo Tovar. "Bounding Cache Persistence Reload Overheads for Set-Associative Caches." In 2020 IEEE 26th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). IEEE, 2020. http://dx.doi.org/10.1109/rtcsa50079.2020.9203583.
Full textMegalingam, Rajesh Kannan, K. B. Deepu, Iype P. Joseph, and Vandana Vikram. "Phased set associative cache design for reduced power consumption." In 2009 2nd IEEE International Conference on Computer Science and Information Technology. IEEE, 2009. http://dx.doi.org/10.1109/iccsit.2009.5234663.
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