Log in

Relevant bibliographies by topics / Set of instructions / Dissertations / Theses

To see the other types of publications on this topic, follow the link: Set of instructions.

Dissertations / Theses on the topic 'Set of instructions'

Author: Grafiati

Published: 28 May 2022

Last updated: 30 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 dissertations / theses for your research on the topic 'Set of instructions.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.

1

Necsulescu, Philip I. "Automatic Generation of Hardware for Custom Instructions." Thèse, Université d'Ottawa / University of Ottawa, 2011. http://hdl.handle.net/10393/20153.

Full text

Abstract:

The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. The framework and algorithms to generate the hardware from an Intermediate Representation (IR) of the C code is needed. This dissertation presents the conceiving, design, and development of a module that generates the hardware for custom instructions identified by specialized SHIRA components without the need for any user interaction. The module is programmed in Java and takes a Data Flow Graph (DFG) as an

APA, Harvard, Vancouver, ISO, and other styles

2

Nagpal, Radhika. "Store Buffers : implementing single cycle store instructions in write-through, write-back and set associative caches." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36678.

Full text

Abstract:

Thesis (B.S. and M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.<br>Includes bibliographical references (p. 87).<br>This thesis proposes a new mechanism, called Store Buffers, for implementing single cycle store instructions in a pipelined processor. Single cycle store instructions are difficult to implement because in most cases the tag check must be performed before the data can be written into the data cache. Store buffers allow a store instruction to read the cache tag as it. passes through the pipe while keeping the store instructi

APA, Harvard, Vancouver, ISO, and other styles

3

Schneider, Nicole. "Parameters: Suites of unique abstract prints generated through the use of a limited set of form-making instructions." Kent State University / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=kent1334282036.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Zmily, Ahmad Darweesh. "Block-aware instruction set architecture /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Schoepke, Olaf S. "Dense instruction set computer architecture." Thesis, University of Bath, 1992. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.332540.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Shi, Xiaomu. "Certification of an Instruction Set Simulator." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00937524.

Full text

Abstract:

Cette thèse expose nos travaux de certification d'une partie d'un programme C/C++ nommé SimSoC (Simulation of System on Chip), qui simule le comportement d'archi- tectures basées sur des processeurs tels que ARM, PowerPC, MIPS ou SH4. Un simulateur de System on Chip peut être utilisé pour developper le logiciel d'un système embarqué spécifique, afin de raccourcir les phases des développement et de test, en particulier quand la vitesse de simulation est réaliste (environ 100 millions d'instructions par seconde par cœur dans le cas de SimSoC). Les réductions de temps et de coût de développement

APA, Harvard, Vancouver, ISO, and other styles

7

Wright, Stephen. "Formal construction of Instruction Set Architectures." Thesis, University of Bristol, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.508307.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Bennett, Richard Vincent. "Increasing the efficacy of automated instruction set extension." Thesis, University of Edinburgh, 2011. http://hdl.handle.net/1842/5789.

Full text

Abstract:

The use of Instruction Set Extension (ISE) in customising embedded processors for a specific application has been studied extensively in recent years. The addition of a set of complex arithmetic instructions to a baseline core has proven to be a cost-effective means of meeting design performance requirements. This thesis proposes and evaluates a reconfigurable ISE implementation called “Configurable Flow Accelerators” (CFAs), a number of refinements to an existing Automated ISE (AISE) algorithm called “ISEGEN”, and the effects of source form on AISE. The CFA is demonstrated repeatedly to be a

APA, Harvard, Vancouver, ISO, and other styles

9

Lee, Vinson 1978. "Instruction set and simulation framework for transactional memory." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/87369.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Moreira, João Carlos Peralta. "An instruction set simulator for VLIW DSP architectures." Master's thesis, Universidade de Aveiro, 2015. http://hdl.handle.net/10773/18675.

Full text

Abstract:

Engenharia Eletrónica e Telecomunicações<br>Dissertação apresentada a Universidade de Aveiro para cumprimento dos requisitos necessários a obtenção do grau de Mestre em Engenharia Eletrónica e Telecomunicações, realizada sob a orientação científica do Professor Doutor Manuel Bernardo Salvador Cunha, Professor Auxiliar do Departamento de Eletrónica, Telecomunicações e Informática da Universidade de Aveiro e Doutor Mohamed Bamakhrama, Hardware Tools Engineer na equipa "Processor and Compiler Tools" no grupo "Imaging and Camera Technologies", Intel Eindhoven, Países Baixos.<br>Dissertation presen

APA, Harvard, Vancouver, ISO, and other styles

11

Kim, Jang Dae. "An instruction-set process calculus for synchronous hardware composition." Related electronic resource: Current Research at SU : database of SU dissertations, recent titles available full text, 2002. http://wwwlib.umi.com/cr/syr/main.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Saghir, Mazen A. R. "Application-specific instruction-set architectures for embedded DSP applications." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0021/NQ53899.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Glökler, Tilman Meyr Heinrich. "Design of energy-efficient application-specific instruction set processors /." Boston, Mass. [u.a.] : Kluwer Acad. Publ, 2004. http://www.loc.gov/catdir/enhancements/fy0820/2004041376-d.html.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Dittmann, Gero [Verfasser]. "On Instruction-Set Generation for Specialized Processors / Gero Dittmann." Aachen : Shaker, 2006. http://d-nb.info/1170532837/34.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Zuluaga, Marcela. "Efficient design-space exploration of custom instruction-set extensions." Thesis, University of Edinburgh, 2010. http://hdl.handle.net/1842/4630.

Full text

Abstract:

Customization of processors with instruction set extensions (ISEs) is a technique that improves performance through parallelization with a reasonable area overhead, in exchange for additional design effort. This thesis presents a collection of novel techniques that reduce the design effort and cost of generating ISEs by advancing automation and reconfigurability. In addition, these techniques maximize the perfomance gained as a function of the additional commited resources. Including ISEs into a processor design implies development at many levels. Most prior works on ISEs solve separate stages

APA, Harvard, Vancouver, ISO, and other styles

16

Pajak, Dominic. "Specification of microprocessor instruction set architectures : ARM case study." Thesis, University of Leeds, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.422038.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Rockers, Daniel M. "A Revised Instruction Set for the Booklet Category Test." Thesis, University of North Texas, 1996. https://digital.library.unt.edu/ark:/67531/metadc278025/.

Full text

Abstract:

Eighty-eight (N = 88) non-brain-injured adults were tested with one of two versions of the Booklet Category Test (BCT). Forty-four (N = 44) individuals were tested with the standard version of the BCT, and forty-four (N = 44) were tested with a revised BCT in which between-subtest cueing was removed, called the Noncued Category Test (NCT). The results of this study indicate that removal of cueing instructions changes the Category test significantly. Subjects administered the NCT scored significantly more errors than those who were administered the standard Category test. While BCT scores corre

APA, Harvard, Vancouver, ISO, and other styles

18

Bauer, Heiner. "Dynamic instruction set extension of microprocessors with embedded FPGAs." Master's thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-222858.

Full text

Abstract:

Increasingly complex applications and recent shifts in technology scaling have created a large demand for microprocessors which can perform tasks more quickly and more energy efficient. Conventional microarchitectures exploit multiple levels of parallelism to increase instruction throughput and use application specific instruction sets or hardware accelerators to increase energy efficiency. Reconfigurable microprocessors adopt the same principle of providing application specific hardware, however, with the significant advantage of post-fabrication flexibility. Not only does this offer similar

APA, Harvard, Vancouver, ISO, and other styles

19

Andersson, Olof, and Karl Bengtsson. "Adapting an FPGA-optimized microprocessor to the MIPS32 instruction set." Thesis, Linköping University, Computer Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-54680.

Full text

Abstract:

<p>Nowadays, FPGAs are large enough to host entire system-on-chip designs, wherein a soft core processor is often an integral part. High performance of the processor is always desirable, so there is an interest in finding faster solutions.This report aims to describe the work and results performed by Karl Bengtson and Olof Andersson at ISY. The task was to continue the development of a soft core microprocessor, originally created by Andreas Ehliar. The first step was to decide a more widely adopted instruction set for the processor. The choice fell upon the MIPS32 instruction set. The main wor

APA, Harvard, Vancouver, ISO, and other styles

20

Mapes, Glenn. "An instruction set simulator for the 8086 16-bit microprocessor." Virtual Press, 1985. http://liblink.bsu.edu/uhtbin/catkey/416976.

Full text

Abstract:

The intent of this thesis is to show the usefulness simulating of an instruction set in software and to demonstrate the feasibility of doing so by providing the framework of a simulation program.The design of new computer architectures and computer based control systems is a trial and error process. Normal design practice is to design and build a prototype of the new system and then evaluate the performance of the prototype. Designing complex systems in this manner is very time consuming and expensive; using a software program to simulate the operation of the new system can help solve certain

APA, Harvard, Vancouver, ISO, and other styles

21

Williams, Fleur Liane. "The impact of instruction set orthogonality on compiler code generation." Thesis, University of Hertfordshire, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.252688.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Seeds, Michael A. "THE ATIS INSTRUCTION SET FOR COMMUNICATION WITH ROBOTIC ASTRONOMICAL TELESCOPES." International Foundation for Telemetering, 1997. http://hdl.handle.net/10150/607396.

Full text

Abstract:

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada<br>Astronomers now communicate over Internet with robotic astronomical telescopes using a specially designed instruction set. ATIS, Automatic Telescope Instruction Set, is designed to communicate specific, technical instructions to a robotic telescope, facilitate data retrieval and analysis, support a wide range of data formats, and also convey preference information that describe the astronomers general needs for data acquisition. Over a dozen telescopes now us

APA, Harvard, Vancouver, ISO, and other styles

23

Wagstaff, Harry. "From high level architecture descriptions to fast instruction set simulators." Thesis, University of Edinburgh, 2015. http://hdl.handle.net/1842/14162.

Full text

Abstract:

As computer systems become increasingly complex and diverse, so too do the architectures they implement. This leads to an increase in complexity in the tools used to design new hardware and software. One particularly important tool in hardware and software design is the Instruction Set Simulator, which is used to prototype new architectures and hardware features, verify hardware, and test and debug software. Many Architecture Description Languages exist which facilitate the description of new architectural or hardware features, and generate a tools such as simulators. However, these typically

APA, Harvard, Vancouver, ISO, and other styles

24

Min, Byoung Woo. "Adding the modal mu-calculus to the instruction-set process calculus." Related electronic resource: Current Research at SU : database of SU dissertations, recent titles available full text, 2005. http://wwwlib.umi.com/cr/syr/main.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Radhakrishnan, Swarnalatha Computer Science &amp Engineering Faculty of Engineering UNSW. "Heterogeneous multi-pipeline application specific instruction-set processor design and implementation." Awarded by:University of New South Wales. Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/29161.

Full text

Abstract:

Embedded systems are becoming ubiquitous, primarily due to the fast evolution of digital electronic devices. The design of modern embedded systems requires systems to exhibit, high performance and reliability, yet have short design time and low cost. Application Specific Instruction set processors (ASIPs) are widely used in embedded system since they are economical to use, flexible, and reusable (thus saves design time). During the last decade research work on ASIPs have been carried out in mainly for single pipelined processors. Improving performance in processors is possible by exploring

APA, Harvard, Vancouver, ISO, and other styles

26

Ponnala, Kalyan. "DESIGN AND IMPLEMENTATION OF THE INSTRUCTION SET ARCHITECTURE FOR DATA LARS." UKnowledge, 2010. http://uknowledge.uky.edu/gradschool_theses/58.

Full text

Abstract:

The ideal memory system assumed by most programmers is one which has high capacity, yet allows any word to be accessed instantaneously. To make the hardware approximate this performance, an increasingly complex memory hierarchy, using caches and techniques like automatic prefetch, has evolved. However, as the gap between processor and memory speeds continues to widen, these programmer-visible mechanisms are becoming inadequate. Part of the recent increase in processor performance has been due to the introduction of programmer/compiler-visible SWAR (SIMD Within A Register) parallel processing o

APA, Harvard, Vancouver, ISO, and other styles

27

Rawat, Hemendra Kumar. "Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak." Thesis, Virginia Tech, 2016. http://hdl.handle.net/10919/72857.

Full text

Abstract:

Recent processor architectures such as Intel Westmere (and later) and ARMv8 include instruction-level support for the Advanced Encryption Standard (AES), for the Secure Hashing Standard (SHA-1, SHA2) and for carry-less multiplication. These crypto-instructions are optimized for a single algorithm and provide significant performance improvements over software written using general-purpose instruction set. However, today's secure systems and protocols do not rely on just one, but a suite of many cryptographic applications that are expected to work in a correct and reliable manner. In this work,

APA, Harvard, Vancouver, ISO, and other styles

28

Chatterjee, Aakriti. "Development of an RSA Algorithm using Reduced RISC V instruction Set." University of Cincinnati / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1617104502129937.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Montcalm, Michael R. "Scheduling Algorithms for Instruction Set Extended Symmetrical Homogeneous Multiprocessor Systems-on-Chip." Thèse, Université d'Ottawa / University of Ottawa, 2011. http://hdl.handle.net/10393/20056.

Full text

Abstract:

Embedded system designers face multiple challenges in fulfilling the runtime requirements of programs. Effective scheduling of programs is required to extract as much parallelism as possible. These scheduling algorithms must also improve speedup after instruction-set extensions have occurred. Scheduling of dynamic code at run time is made more difficult when the static components of the program are scheduled inefficiently. This research aims to optimize a program’s static code at compile time. This is achieved with four algorithms designed to schedule code at the task and instruction level. Ad

APA, Harvard, Vancouver, ISO, and other styles

30

Vogt, Timo. "A reconfigurable application-specific instruction-set processor for trellis-based channel decoding /." Kaiserslautern : Techn. Univ. Kaiserslautern, 2008. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=016537958&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Shee, Seng Lin Computer Science &amp Engineering Faculty of Engineering UNSW. "ADAPT : architectural and design exploration for application specific instruction-set processor technologies." Awarded by:University of New South Wales, 2007. http://handle.unsw.edu.au/1959.4/35404.

Full text

Abstract:

This thesis presents design automation methodologies for extensible processor platforms in application specific domains. The work presents first a single processor approach for customization; a methodology that can rapidly create different processor configurations by the removal of unused instructions sets from the architecture. A profile directed approach is used to identify frequently used instructions and to eliminate unused opcodes from the available instruction pool. A coprocessor approach is next explored to create an SoC (System-on-Chip) to speedup the application while reducing energy

APA, Harvard, Vancouver, ISO, and other styles

32

Curtis, Bryce Allen. "A special instruction set multiple chip computer for DSP : architecture and compiler design." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15736.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Sohl, Joar. "Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories." Doctoral thesis, Linköpings universitet, Datorteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-113702.

Full text

Abstract:

Modern signal processing systems require more and more processing capacity as times goes on. Previously, large increases in speed and power efficiency have come from process technology improvements. However, lately the gain from process improvements have been greatly reduced. Currently, the way forward for high-performance systems is to use specialized hardware and/or parallel designs. Application Specific Integrated Circuits (ASICs) have long been used to accelerate the processing of tasks that are too computationally heavy for more general processors. The problem with ASICs is that they are

APA, Harvard, Vancouver, ISO, and other styles

34

Afuah, Allan Nembo. "Strategic adoption of innovation--the case of reduced instruction set computer (RISC) technology." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/11613.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Degenbaev, Ulan [Verfasser], and Wolfgang J. [Akademischer Betreuer] Paul. "Formal specification of the x86 instruction set architecture / Ulan Degenbaev. Betreuer: Wolfgang J. Paul." Saarbrücken : Saarländische Universitäts- und Landesbibliothek, 2012. http://d-nb.info/105227885X/34.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Johnston, Erin. "Shared instruction-set extensions for soft multiprocessor systems implemented on field-programmable gate arrays." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43695.

Full text

Abstract:

Soft-core embedded systems implemented on FPGAs offer a high level of flexibility. Application specific customizations can be added in the form of extensions to the processor’s regular instruction-set. These custom instructions benefit run-time performance, but come at the cost of increased resource usage. Reducing the overall FPGA area required to implement a system will decrease static power consumption and allow a smaller, cheaper device to be used. There is a constant effort to reduce area and power consumption while maintaining performance benefits attained through customizations. This th

APA, Harvard, Vancouver, ISO, and other styles

37

Lim, Wei Ming. "Design of application specific instruction set processors for the domain of GF(2'm)." Thesis, University of Sheffield, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.412439.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Zheng, Yi Hong, and 鄭一鴻. "Optimal instruction set design." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/37593217098049161237.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Yu-Ru, Yang. "Instruction Set Extension for Interpolation." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0016-1303200709302045.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Yang, Yu-Ru, and 楊侑儒. "Instruction Set Extension for Interpolation." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/65039211993127491600.

Full text

Abstract:

碩士<br>國立清華大學<br>資訊工程學系<br>94<br>H.264/AVC is the state-of-the-art video coding standard. One of the basic implementation issues of H.264 standard isthat its computational complexity is very high. By the profiling result, we focus on the interpolation procedure which consumes up to 22% of the execution time. In this thesis, we propose a number of new instructions for interpolation and hardware architecture to support these new instructions. The experimental result shows that by these new instructions, computation time is reduced 30% in average.

APA, Harvard, Vancouver, ISO, and other styles

41

Yo-Ray, Lee. "Instruction Set Extension For Deblocking Filter." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0016-1303200709264754.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

"Reducing a complex instruction set computer." Chinese University of Hong Kong, 1988. http://library.cuhk.edu.hk/record=b5885967.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Tseng, Cheng-Pin, and 曾成濱. "Instruction Set Extension Exploration on VLIW." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/00656234462118202289.

Full text

Abstract:

碩士<br>逢甲大學<br>資訊工程所<br>97<br>Both Instruction Set Extension(ISE) on base processor and VLIW architectures are two of the most popular methodology to achieve the required computing power in embedded system design. Selecting operations on critical path as ISE as well as scheduling parallel operations on a multiple-issue architecture can obtain the better performance with efficient hardware utilization. However, manually explore ISE may be very complex and time cost. This thesis presents an automatic design flow for ISE exploration on VLIW architectures using a Force-Directed Scheduli

APA, Harvard, Vancouver, ISO, and other styles

44

Lee, Yo-Ray, and 李岳叡. "Instruction Set Extension For Deblocking Filter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/91596609321006376554.

Full text

Abstract:

碩士<br>國立清華大學<br>資訊工程學系<br>94<br>H.264/AVC is a new codec standard for video. A traditional DSP architecture is not e±cient enough for this new standard. The pro¯ling results show that Deblocking Filter consumes up to 33% running time of H.264 decoder. In this thesis, we focus on designing new instructions to speed up Deblocking Filter. Based on a standard Star¯sh DSP, we propose novel instructions and architecture for Deblocking Filter. In experiment result, we show that 28.5% improvement in computation time is achieved on Filter Processing part of Deblocking Filter by our new instructions.

APA, Harvard, Vancouver, ISO, and other styles

45

Wang, Yi-Chieh, and 王繹傑. "Instruction Set Extension for Java Bytecode." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/41889087975284590298.

Full text

Abstract:

碩士<br>國立成功大學<br>工程科學系碩博士班<br>97<br>This thesis is to define a subset of Java bytecodes that are suitable for instruction set extension as the basis of CPU executing Java bytecode directly. The first step is to analyze the usage of each Java bytecode from benchmark programs, and then identify the bytecodes suitable for instruction set extension. These experiments are performed on the open-source Java Virtual Machine, the JamVM and GNU Classpath. These experiments collect the usage of Java bytecodes of the DaCapo benchmark suite. We implemented a profiler inside the JVM to help tracing and analy

APA, Harvard, Vancouver, ISO, and other styles

46

(10645670), Christopher M. Wright. "EMULATION FOR MULTIPLE INSTRUCTION SET ARCHITECTURES." Thesis, 2021.

Find full text

Abstract:

<p>System emulation and firmware re-hosting are popular techniques to answer various security and performance related questions, such as, does a firmware contain security vulnerabilities or meet timing requirements when run on a specific hardware platform. While this motivation for emulation and binary analysis has previously been explored and reported, starting to work or research in the field is difficult. Further, doing the actual firmware re-hosting for various Instruction Set Architectures(ISA) is usually time consuming and difficult, and at times may seem impossible. To this end, I provi

APA, Harvard, Vancouver, ISO, and other styles

47

Akkaş, Ahmet. "Instruction set enhancements for reliable computations /." Diss., 2001. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3036247.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

Κάργας, Χρήστος. "Energy efficient instruction decoding in application: Specific instruction - set processors." Thesis, 2012. http://hdl.handle.net/10889/6295.

Full text

Abstract:

With commercial processor design tools, a designer can quickly design a C- programmable ASIP for a specific application domain. There are several such ASIPs available for both wireless (UWB baseband processing), encryption, and biomedical processing (particularly for ECG beat detection). In traditional CPUs and DSPs the impact of the instruction-set definition and the complexity of the instruction decoder can be substantial, especially in terms of power consumption. Fully orthogonal VLIW processors, do not incur the cost of an instruction decoder that severely. Instead the instruction w

APA, Harvard, Vancouver, ISO, and other styles

49

FENG, QI-DE, and 馮啟德. "A Stacly of Multi-Operation Instruction Set." Thesis, 1991. http://ndltd.ncl.edu.tw/handle/52823992284393489238.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Veselá, Jaroslava. "Disciplinace poddaných na základě nástrojů vrchnostenské správy na sklonku 16. a v první polovině 17. století." Master's thesis, 2019. http://www.nusl.cz/ntk/nusl-404643.

Full text

Abstract:

(in English): This Master's work attempts to analyze the selected documents of dominion's administration, which were being published by the office workers of the dominion's management during the period from the end of the 16th to the half of the 17th century, and through the metody of comparison it tries to find out the official form of the manor's leading methods and the communication between the owner of domain and his subordinate inhabitants.

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!