To see the other types of publications on this topic, follow the link: Shaker architecture.
Dissertations / Theses on the topic 'Shaker architecture'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'Shaker architecture.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Hadi, Shadan. "MYOSIN-XVA IS KEY MOLECULE IN ESTABLISHING THE ARCHITECTURE OF MECHANOSENSORY STEREOCILIA BUNDLES OF THE INNER EAR HAIR CELLS." UKnowledge, 2018. https://uknowledge.uky.edu/medsci_etds/9.
Full textAbstract:
Development of hair cell stereocilia bundles involves three stages: elongation, thickening, and supernumerary stereocilia retraction. Although Myo-XVa is known to be essential for stereocilia elongation, its role in retraction/thickening remains unknown. We quantified stereocilia numbers/diameters in shaker-2 mice (Myo15sh2) that have deficiencies in “long” and “short” isoforms of myosin-XVa, and in mice lacking only the “long” myosin-XVa isoform (Myo15ΔN). Our data showed that myosin-XVa is largely not involved in the developmental retraction of supernumerary stereocilia. In normal development, the diameters of the first (tallest)/second row stereocilia within a bundle are equal and grow simultaneously. The diameter of the third row stereocilia increases together with that of taller stereocilia until P1-2 and then either decreases almost two-fold in inner hair cells (IHCs) or stays the same in outer hair cells (OHCs), resulting in a prominent diameter gradation in IHCs and less prominent in OHCs. Sh2 mutation abolishes this gradation in IHCs/OHCs. Stereocilia of all rows grow in diameters nearly equally in Myo15sh2/sh2 IHCs and OHCs. Conversely, ΔN mutation does not affect normal stereocilia diameter gradation until ~P8. Therefore, myosin-XVa “short” isoform is essential for developmental thinning of third row stereocilia, which causes diameter gradation within a hair bundle.
2
Yousuf, Kamran. "Time controlled network traffic shaper." Thesis, Blekinge Tekniska Högskola, Sektionen för datavetenskap och kommunikation, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-2170.
Full textAbstract:
Network performance metrics such as delay variations and packet loss influence the performance of the network. As a consequence, the performance of applications on the network is also affected as most of the networked applications existing today are very much sensitive to the network performance. Therefore it is of utmost importance to test the intensity of such network level disturbances on the performance of applications. A network traffic shaper/emulator shapes the network traffic in terms of these performance metrics to test such applications in a controlled environment. Most of the traffic shapers existing today give the instantaneous step transition in delay and packet loss on network. In this work, we present time-controlled network traffic shaper, a tool that facilitates testing and experimentation of network traffic through emulation. It focuses on time variant behavior of the traffic shaper. A linear transition of delay and packet loss that is varying with respect to time may fits much better to the real network scenarios instead of an instantaneous step transition in delay and packet loss. This work illustrates the emulation capabilities of time-controlled network traffic shaper and presents its design architecture. Several approaches are analyzed to do the task and one of them is followed to develop the desired architecture of the shaper. The shaper is implemented in a small scenario and is tested to see whether the desired output is achieved or not. The shortfalls in the design of the shaper are also discussed. Results are presented that show the output from the shaper in graphical form. Although the current implementation of the shaper does not provide linear or exponential output but this can be achieved by implementing a configuration setting that is comprised of small transition values that are varying with respect to very small step sizes of time e.g. transitions on milli seconds or micro seconds. The current implementation of the shaper configuration provides the output with a transition of one milli second on every next second.kami1219@gmail.com
3
Lidstone, Patrick. "A dynamically reconfigurable parallel processing architecture." Thesis, University of Exeter, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.307286.
Full text
4
Narravula, Harsha V. Katsinis Constantine. "Performance of parallel algorithms on a broadcast-based architecture /." Philadelphia, Pa. : Drexel University, 2003. http://dspace.library.drexel.edu/handle/1860/254.
Full text
5
Costa, Celsio Maciel da. "Environnement d'éxécution parallèle : conception et architecture." Grenoble 1, 1993. http://tel.archives-ouvertes.fr/tel-00005132.
Full textAbstract:
"la 4e de couverture indique :L'objectif de cette thèse est l'étude d'un environnement d'exécution pour machines parallèles sans mémoire commune. Elle comprend la définition d'un modèle de programme parallèle, base sur l'échange de message offrant une forme restreinte de mémoire partagée. La communication est indirecte, via des portes ; les processus utilisent les barrières pour la synchronisation. Les entités du système, processus, portes et barrières, sont créées dynamiquement, et placées sur un processeur quelconque du réseau de processeurs de façon expliciteNous proposons une implantation de ce modèle comme la mise en œuvre systématique d'une architecture client/ serveur. Cette implantation a été effectuée sur une machine Supernode. La base est un Micro Noyau Parallèle, ou le composant principal est un mécanisme d'appel de procédure à distance minimal"
6
Tillenius, Martin. "Scientific Computing on Multicore Architectures." Doctoral thesis, Uppsala universitet, Avdelningen för beräkningsvetenskap, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-221241.
Full textAbstract:
Computer simulations are an indispensable tool for scientists to gain new insights about nature. Simulations of natural phenomena are usually large, and limited by the available computer resources. By using the computer resources more efficiently, larger and more detailed simulations can be performed, and more information can be extracted to help advance human knowledge. The topic of this thesis is how to make best use of modern computers for scientific computations. The challenge here is the high level of parallelism that is required to fully utilize the multicore processors in these systems. Starting from the basics, the primitives for synchronizing between threads are investigated. Hardware transactional memory is a new construct for this, which is evaluated for a new use of importance for scientific software: atomic updates of floating point values. The evaluation includes experiments on real hardware and comparisons against standard methods. Higher level programming models for shared memory parallelism are then considered. The state of the art for efficient use of multicore systems is dynamically scheduled task-based systems, where tasks can depend on data. In such systems, the software is divided up into many small tasks that are scheduled asynchronously according to their data dependencies. This enables a high level of parallelism, and avoids global barriers. A new system for managing task dependencies is developed in this thesis, based on data versioning. The system is implemented as a reusable software library, and shown to be as efficient or more efficient than other shared-memory task-based systems in experimental comparisons. The developed runtime system is then extended to distributed memory machines, and used for implementing a parallel version of a software for global climate simulations. By running the optimized and parallelized version on eight servers, an equally sized problem can be solved over 100 times faster than in the original sequential version. The parallel version also allowed significantly larger problems to be solved, previously unreachable due to memory constraints.UPMARC
eSSENCE
7
Zeffer, Håkan. "Towards Low-Complexity Scalable Shared-Memory Architectures." Doctoral thesis, Uppsala University, Department of Information Technology, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-7135.
Full textAbstract:
Plentiful research has addressed low-complexity software-based shared-memory systems since the idea was first introduced more than two decades ago. However, software-coherent systems have not been very successful in the commercial marketplace. We believe there are two main reasons for this: lack of performance and/or lack of binary compatibility.
This thesis studies multiple aspects of how to design future binary-compatible high-performance scalable shared-memory servers while keeping the hardware complexity at a minimum. It starts with a software-based distributed shared-memory system relying on no specific hardware support and gradually moves towards architectures with simple hardware support.
The evaluation is made in a modern chip-multiprocessor environment with both high-performance compute workloads and commercial applications. It shows that implementing the coherence-violation detection in hardware while solving the interchip coherence in software allows for high-performing binary-compatible systems with very low hardware complexity. Our second-generation hardware-software hybrid performs on par with, and often better than, traditional hardware-only designs.
Based on our results, we conclude that it is not only possible to design simple systems while maintaining performance and the binary-compatibility envelope, it is often possible to get better performance than in traditional and more complex designs.
We also explore two new techniques for evaluating a new shared-memory design throughout this work: adjustable simulation fidelity and statistical multiprocessor cache modeling.
8
Habel, Rachid. "Programmation haute performance pour architectures hybrides." Thesis, Paris, ENMP, 2014. http://www.theses.fr/2014ENMP0025/document.
Full textAbstract:
Les architectures parallèles hybrides constituées d'un grand nombre de noeuds de calcul multi-coeurs/GPU connectés en réseau offrent des performances théoriques très élevées, de l'ordre de quelque dizaines de TeraFlops. Mais la programmation efficace de ces machines reste un défi à cause de la complexité de l'architecture et de la multiplication des modèles de programmation utilisés. L'objectif de cette thèse est d'améliorer la programmation des applications scientifiques denses sur les architectures parallèles hybrides selon trois axes: réduction des temps d'exécution, traitement de données de très grande taille et facilité de programmation. Nous avons pour cela proposé un modèle de programmation à base de directives appelé DSTEP pour exprimer à la fois la distribution des données et des calculs. Dans ce modèle, plusieurs types de distribution de données sont exprimables de façon unifiée à l'aide d'une directive "dstep distribute" et une réplication de certains éléments distribués peut être exprimée par un "halo". La directive "dstep gridify" exprime à la fois la distribution des calculs ainsi que leurs contraintes d'ordonnancement. Nous avons ensuite défini un modèle de distribution et montré la correction de la transformation de code du domaine séquentiel au domaine distribué. À partir du modèle de distribution, nous avons dérivé un schéma de compilation pour la transformation de programmes annotés de directives DSTEP en des programmes parallèles hybrides. Nous avons implémenté notre solution sous la forme d'un compilateur intégré à la plateforme de compilation PIPS ainsi qu'une bibliothèque fournissant les fonctionnalités du support d'exécution, notamment les communications. Notre solution a été validée sur des programmes de calcul scientifiques standards tirés des NAS Parallel Benchmarks et des Polybenchs ainsi que sur une application industrielleClusters of multicore/GPU nodes connected with a fast network offer very high therotical peak performances, reaching tens of TeraFlops. Unfortunately, the efficient programing of such architectures remains challenging because of their complexity and the diversity of the existing programming models. The purpose of this thesis is to improve the programmability of dense scientific applications on hybrid architectures in three ways: reducing the execution times, processing larger data sets and reducing the programming effort. We propose DSTEP, a directive-based programming model expressing both data and computation distribution. A large set of distribution types are unified in a "dstep distribute" directive and the replication of some distributed elements can be expressed using a "halo". The "dstep gridify" directive expresses both the computation distribution and the schedule constraints of loop iterations. We define a distribution model and demonstrate the correctness of the code transformation from the sequential domain to the parallel domain. From the distribution model, we derive a generic compilation scheme transforming DSTEP annotated input programs into parallel hybrid ones. We have implemented such a tool as a compiler integrated to the PIPS compilation workbench together with a library offering the runtime functionality, especially the communication. Our solution is validated on scientific programs from the NAS Parallel Benchmarks and the PolyBenchs as well as on an industrial signal procesing application
9
Mohamed, Khalid. "Breaking The Boxdaylight shaping architecture." Thesis, KTH, Ljusdesign, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-280074.
Full textAbstract:
It is well-known that daylight is a fundamental element to experiencean architectural space. In spite of that, there are limitedresources that consider how to form that space based ondaylight. This paper constitutes ‘Breaking the Box’ as a newconcept, which can be taken by architects, lighting designersand urban planners in parallel to their daylight design techniquesas a tool in design practice.‘Breaking the Box’ has its origin in the destruction of the boxconcept, a design method of the modern architecture pioneerFrank Lloyd Wright. Thus, it is an attempt to develop Wright’stheory in relation to daylight. The paper investigates severalqualitative and quantitative sub-tools in case studies andexperimental models, exploring a variety of configurations inspatial relationships and form to assess different characteristicsof daylight in residential environments.The aim of the study is to understand and control the penetrationof daylight qualities – considering both diffused skylightand direct sunlight – within a space in different latitudes.Thus, preserving the view and making the quality of daylightthe founding element shaping architecture by breaking thebox. The study revealed a strong relationship between daylightqualities and architectural form. As a result, it is evidencethat daylight does shape architecture. When it comes to incorporatingdaylight, form does not follow function but formand function are one.
10
Leyhe, Meryl. "Shared, not Vacant Spaces." Thesis, KTH, Arkitektur, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-289605.
Full textAbstract:
For my thesis project, I have chosen to explore the exaptation of a vacant office building doomed to be demolished in Stockholm into a residential tower. This project’s focus is the investigation of the reusability of our existing built environment in a sustainable way together with diverse collective living concepts and a comparison of the value added from a deconstruction, reuse and an environmentally sound concept versus a full demolition and subsequent new construction.The paramount challenges we are facing are the changing climate and limitation of natural resources. We have to address this issue by rethinking our societal and habitational models; the way we live, how we inhabit space, how do we use resources and consume goods and especially how do we design and build our cities.
11
Qin, Xiaohan. "On the use and performance of communication primitives in software controlled cache-coherent cluster architectures /." Thesis, Connect to this title online; UW restricted, 1997. http://hdl.handle.net/1773/6925.
Full text
12
Moretó, Planas Miquel. "Improving cache Behavior in CMP architectures throug cache partitioning techniques." Doctoral thesis, Universitat Politècnica de Catalunya, 2010. http://hdl.handle.net/10803/6021.
Full textAbstract:
The evolution of microprocessor design in the last few decades has changed significantly, moving from simple inorder single core architectures to superscalar and vector architectures in order to extract the maximum available instruction level parallelism. Executing several instructions from the same thread in parallel allows significantly improving the performance of an application. However, there is only a limited amount of parallelism available in each thread, because of data and control dependences. Furthermore, designing a high performance, single, monolithic processor has become very complex due to power and chip latencies constraints. These limitations have motivated the use of thread level parallelism (TLP) as a common strategy for improving processor performance. Multithreaded processors allow executing different threads at the same time, sharing some hardware resources. There are several flavors of multithreaded processors that exploit the TLP, such as chip multiprocessors (CMP), coarse grain multithreading, fine grain multithreading, simultaneous multithreading (SMT), and combinations of them.To improve cost and power efficiency, the computer industry has adopted multicore chips. In particular, CMP architectures have become the most common design decision (combined sometimes with multithreaded cores). Firstly, CMPs reduce design costs and average power consumption by promoting design re-use and simpler processor cores. For example, it is less complex to design a chip with many small, simple cores than a chip with fewer, larger, monolithic cores.
Furthermore, simpler cores have less power hungry centralized hardware structures. Secondly, CMPs reduce costs by improving hardware resource utilization. On a multicore chip, co-scheduled threads can share costly microarchitecture resources that would otherwise be underutilized. Higher resource utilization improves aggregate performance and enables lower cost design alternatives.
One of the resources that impacts most on the final performance of an application is the cache hierarchy. Caches store data recently used by the applications in order to take advantage of temporal and spatial locality of applications. Caches provide fast access to data, improving the performance of applications. Caches with low latencies have to be small, which prompts the design of a cache hierarchy organized into several levels of cache.
In CMPs, the cache hierarchy is normally organized in a first level (L1) of instruction and data caches private to each core. A last level of cache (LLC) is normally shared among different cores in the processor (L2, L3 or both). Shared caches increase resource utilization and system performance. Large caches improve performance and efficiency by increasing the probability that each application can access data from a closer level of the cache hierarchy. It also allows an application to make use of the entire cache if needed.
A second advantage of having a shared cache in a CMP design has to do with the cache coherency. In parallel applications, different threads share the same data and keep a local copy of this data in their cache. With multiple processors, it is possible for one processor to change the data, leaving another processor's cache with outdated data. Cache coherency protocol monitors changes to data and ensures that all processor caches have the most recent data. When the parallel application executes on the same physical chip, the cache coherency circuitry can operate at the speed of on-chip communications, rather than having to use the much slower between-chip communication, as is required with discrete processors on separate chips. These coherence protocols are simpler to design with a unified and shared level of cache onchip.
Due to the advantages that multicore architectures offer, chip vendors use CMP architectures in current high performance, network, real-time and embedded systems. Several of these commercial processors have a level of the cache hierarchy shared by different cores. For example, the Sun UltraSPARC T2 has a 16-way 4MB L2 cache shared by 8 cores each one up to 8-way SMT. Other processors like the Intel Core 2 family also share up to a 12MB 24-way L2 cache. In contrast, the AMD K10 family has a private L2 cache per core and a shared L3 cache, with up to a 6MB 64-way L3 cache.
As the long-term trend of increasing integration continues, the number of cores per chip is also projected to increase with each successive technology generation. Some significant studies have shown that processors with hundreds of cores per chip will appear in the market in the following years. The manycore era has already begun. Although this era provides many opportunities, it also presents many challenges. In particular, higher hardware resource sharing among concurrently executing threads can cause individual thread's performance to become unpredictable and might lead to violations of the individual applications' performance requirements. Current resource management mechanisms and policies are no longer adequate for future multicore systems.
Some applications present low re-use of their data and pollute caches with data streams, such as multimedia, communications or streaming applications, or have many compulsory misses that cannot be solved by assigning more cache space to the application. Traditional eviction policies such as Least Recently Used (LRU), pseudo LRU or random are demand-driven, that is, they tend to give more space to the application that has more accesses to the cache hierarchy.
When no direct control over shared resources is exercised (the last level cache in this case), it is possible that a particular thread allocates most of the shared resources, degrading other threads performance. As a consequence, high resource sharing and resource utilization can cause systems to become unstable and violate individual applications' requirements. If we want to provide a Quality of Service (QoS) to applications, we need to enhance the control over shared resources and enrich the collaboration between the OS and the architecture.
In this thesis, we propose software and hardware mechanisms to improve cache sharing in CMP architectures. We make use of a holistic approach, coordinating targets of software and hardware to improve system aggregate performance and provide QoS to applications. We make use of explicit resource allocation techniques to control the shared cache in a CMP architecture, with resource allocation targets driven by hardware and software mechanisms.
The main contributions of this thesis are the following:
- We have characterized different single- and multithreaded applications and classified workloads with a systematic method to better understand and explain the cache sharing effects on a CMP architecture. We have made a special effort in studying previous cache partitioning techniques for CMP architectures, in order to acquire the insight to propose improved mechanisms.
- In CMP architectures with out-of-order processors, cache misses can be served in parallel and share the miss penalty to access main memory. We take this fact into account to propose new cache partitioning algorithms guided by the memory-level parallelism (MLP) of each application. With these algorithms, the system performance is improved (in terms of throughput and fairness) without significantly increasing the hardware required by previous proposals.
- Driving cache partition decisions with indirect indicators of performance such as misses, MLP or data re-use may lead to suboptimal cache partitions. Ideally, the appropriate metric to drive cache partitions should be the target metric to optimize, which is normally related to IPC. Thus, we have developed a hardware mechanism, OPACU, which is able to obtain at run-time accurate predictions of the performance of an application when running with different cache assignments.
- Using performance predictions, we have introduced a new framework to manage shared caches in CMP architectures, FlexDCP, which allows the OS to optimize different IPC-related target metrics like throughput or fairness and provide QoS to applications. FlexDCP allows an enhanced coordination between the hardware and the software layers, which leads to improved system performance and flexibility.
- Next, we have made use of performance estimations to reduce the load imbalance problem in parallel applications. We have built a run-time mechanism that detects parallel applications sensitive to cache allocation and, in these situations, the load imbalance is reduced by assigning more cache space to the slowest threads. This mechanism, helps reducing the long optimization time in terms of man-years of effort devoted to large-scale parallel applications.
- Finally, we have stated the main characteristics that future multicore processors with thousands of cores should have. An enhanced coordination between the software and hardware layers has been proposed to better manage the shared resources in these architectures.
13
Diener, Matthias. "Automatic task and data mapping in shared memory architectures." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/131871.
Full textAbstract:
Arquiteturas paralelas modernas têm hierarquias de memória complexas, que consistem de vários níveis de memórias cache privadas e compartilhadas, bem como Non-Uniform Memory Access (NUMA) devido a múltiplos controladores de memória por sistema. Um dos grandes desafios dessas arquiteturas é melhorar a localidade e o balanceamento de acessos à memória de tal forma que a latência média de acesso à memória é reduzida. Dessa forma, o desempenho e a eficiência energética de aplicações paralelas podem ser melhorados. Os acessos podem ser melhorados de duas maneiras: (1) processos que acessam dados compartilhados (comunicação entre processos) podem ser alocados em unidades de execução próximas na hierarquia de memória, a fim de melhorar o uso das caches. Esta técnica é chamada de mapeamento de processos. (2) Mapear as páginas de memória que cada processo acessa ao nó NUMA que ele está sendo executado, assim, pode-se reduzir o número de acessos a memórias remotas em arquiteturas NUMA. Essa técnica é conhecida como mapeamento de dados. Para melhores resultados, os mapeamentos de processos e dados precisam ser realizados de forma integrada. Trabalhos anteriores nesta área executam os mapeamentos separadamente, o que limita os ganhos que podem ser alcançados. Além disso, a maioria dos mecanismos anteriores exigem operações caras, como traços de acessos à memória, para realizar o mapeamento, além de exigirem mudanças no hardware ou na aplicação paralela. Estes mecanismos não podem ser considerados soluções genéricas para o problema de mapeamento. Nesta tese, fazemos duas contribuições principais para o problema de mapeamento. Em primeiro lugar, nós introduzimos um conjunto de métricas e uma metodologia para analisar aplicações paralelas, a fim de determinar a sua adequação para um melhor mapeamento e avaliar os possíveis ganhos que podem ser alcançados através desse mapeamento otimizado. Em segundo lugar, propomos um mecanismo que executa o mapeamento de processos e dados online. Este mecanismo funciona no nível do sistema operacional e não requer alterações no hardware, os códigos fonte ou bibliotecas. Uma extensa avaliação com múltiplos conjuntos de carga de trabalho paralelos mostram consideráveis melhorias em desempenho e eficiência energética.Reducing the cost of memory accesses, both in terms of performance and energy consumption, is a major challenge in shared-memory architectures. Modern systems have deep and complex memory hierarchies with multiple cache levels and memory controllers, leading to a Non-Uniform Memory Access (NUMA) behavior. In such systems, there are two ways to improve the memory affinity: First, by mapping tasks that share data (communicate) to cores with a shared cache, cache usage and communication performance are improved. Second, by mapping memory pages to memory controllers that perform the most accesses to them and are not overloaded, the average cost of accesses is reduced. We call these two techniques task mapping and data mapping, respectively. For optimal results, task and data mapping need to be performed in an integrated way. Previous work in this area performs the mapping only separately, which limits the gains that can be achieved. Furthermore, most previous mechanisms require expensive operations, such as communication or memory access traces, to perform the mapping, require changes to the hardware or to the parallel application, or use a simple static mapping. These mechanisms can not be considered generic solutions for the mapping problem. In this thesis, we make two contributions to the mapping problem. First, we introduce a set of metrics and a methodology to analyze parallel applications in order to determine their suitability for an improved mapping and to evaluate the possible gains that can be achieved using an optimized mapping. Second, we propose two automatic mechanisms that perform task mapping and combined task/data mapping, respectively, during the execution of a parallel application. These mechanisms work on the operating system level and require no changes to the hardware, the applications themselves or their runtime libraries. An extensive evaluation with parallel applications from multiple benchmark suites as well as real scientific applications shows substantial performance and energy efficiency improvements that are significantly higher than simple mechanisms and previous work, while maintaining a low overhead.
14
Abi-Farraj, Firas. "Contributions aux architectures de contrôle partagé pour la télémanipulation avancée." Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S120/document.
Full textAbstract:
Bien que la pleine autonomie dans des environnements inconnus soit encore loin, les architectures de contrôle partagé où l'humain et un contrôleur autonome travaillent ensemble pour atteindre un objectif commun peuvent constituer un « terrain intermédiaire » pragmatique. Dans cette thèse, nous avons abordé les différents problèmes des algorithmes de contrôle partagé pour les applications de saisie et de manipulation. En particulier, le travail s'inscrit dans le projet H2020 Romans dont l'objectif est d'automatiser le tri et la ségrégation des déchets nucléaires en développant des architectures de contrôle partagées permettant à un opérateur humain de manipuler facilement les objets d'intérêt. La thèse propose des architectures de contrôle partagé différentes pour manipulation à double bras avec un équilibre opérateur / autonomie différent en fonction de la tâche à accomplir. Au lieu de travailler uniquement sur le contrôle instantané du manipulateur, nous proposons des architectures qui prennent en compte automatiquement les tâches de pré-saisie et de post-saisie permettant à l'opérateur de se concentrer uniquement sur la tâche à accomplir. La thèse propose également une architecture de contrôle partagée pour contrôler un humanoïde à deux bras où l'utilisateur est informé de la stabilité de l'humanoïde grâce à un retour haptique. En plus, un nouvel algorithme d'équilibrage permettant un contrôle optimal de l'humanoïde lors de l'interaction avec l'environnement est également proposéWhile full autonomy in unknown environments is still in far reach, shared-control architectures where the human and an autonomous controller work together to achieve a common objective may be a pragmatic "middle-ground". In this thesis, we have tackled the different issues of shared-control architectures for grasping and sorting applications. In particular, the work is framed in the H2020 RoMaNS project whose goal is to automatize the sort and segregation of nuclear waste by developing shared control architectures allowing a human operator to easily manipulate the objects of interest. The thesis proposes several shared-control architectures for dual-arm manipulation with different operator/autonomy balance depending on the task at hand. While most of the approaches provide an instantaneous interface, we also propose architectures which automatically account for the pre-grasp and post-grasp trajectories allowing the operator to focus only on the task at hand (ex., grasping). The thesis also proposes a shared control architecture for controlling a force-controlled humanoid robot in which the user is informed about the stability of the humanoid through haptic feedback. A new balancing algorithm allowing for the optimal control of the humanoid under high interaction forces is also proposed
15
Naeem, Abdul. "Architecture Support and Scalability Analysis of Memory Consistency Models in Network-on-Chip based Systems." Doctoral thesis, KTH, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-117700.
Full textAbstract:
The shared memory systems should support parallelization at the computation (multi-core), communication (Network-on-Chip, NoC) and memory architecture levels to exploit the potential performance benefits. These parallel systems supporting shared memory abstraction both in the general purpose and application specific domains are confronting the critical issue of memory consistency. The memory consistency issue arises due to the unconstrained memory operations which leads to the unexpected behavior of shared memory systems. The memory consistency models enforce ordering constraints on the memory operations for the expected behavior of the shared memory systems. The intuitive Sequential Consistency (SC) model enforces strict ordering constraints on the memory operations and does not take advantage of the system optimizations both in the hardware and software. Alternatively, the relaxed memory consistency models relax the ordering constraints on the memory operations and exploit these optimizations to enhance the system performance at the reasonable cost. The purpose of this thesis is twofold. First, the novel architecture supports are provided for the different memory consistency models like: SC, Total Store Ordering (TSO), Partial Store Ordering (PSO), Weak Consistency (WC), Release Consistency (RC) and Protected Release Consistency (PRC) in the NoC-based multi-core (McNoC) systems. The PRC model is proposed as an extension of the RC model which provides additional reordering and relaxation in the memory operations. Second, the scalability analysis of these memory consistency models is performed in the McNoC systems. The architecture supports for these different memory consistency models are provided in the McNoC platforms. Each configurable McNoC platform uses a packet-switched 2-D mesh NoC with deflection routing policy, distributed shared memory (DSM), distributed locks and customized processor interface. The memory consistency models/protocols are implemented in the customized processor interfaces which are developed to integrate the processors with the rest of the system. The realization schemes for the memory consistency models are based on a transaction counter and an an an address ddress ddress ddress ddress ddress ddress stack tacktack-based based based based based based novel approaches.approaches.approaches.approaches. approaches.approaches.approaches.approaches.approaches.approaches. The transaction counter is used in each node of the network to keep track of the outstanding memory operations issued by a processor in the system. The address stack is used in each node of the network to keep track of the addresses of the outstanding memory operations issued by a processor in the system. These hardware structures are used in the processor interface to enforce the required global orders under these different memory consistency models. The realization scheme of the PRC model in addition also uses acquire counter for further classification of the data operations as unprotected and protected operations. The scalability analysis of these different memory consistency models is performed on the basis of different workloads which are developed and mapped on the various sized networks. The scalability study is conducted in the McNoC systems with 1 to 64-cores with various applications using different problem sizes and traffic patterns. The performance metrics like execution time, performance, speedup, overhead and efficiency are evaluated as a function of the network size. The experiments are conducted both with the synthetic and application workloads. The experimental results under different application workloads show that the average execution time under the relaxed memory consistency models decreases relative to the SC model. The specific numbers are highly sensitive to the application and depend on how well it matches to the architectures. This study shows the performance improvement under the relaxed memory consistency models over the SC model that is dependent on the computation-to-communication ratio, traffic patterns, data-to-synchronization ratio and the problem size. The performance improvement of the PRC and RC models over the SC model tends to be higher than 50% as observed in the experiments, when the system is further scaled up.QC 20130204
16
Kaci, Ania. "Conception d'une architecture extensible pour le calcul massivement parallèle." Thesis, Paris Est, 2016. http://www.theses.fr/2016PESC1044.
Full textAbstract:
En réponse à la demande croissante de performance par une grande variété d’applications (exemples : modélisation financière, simulation sub-atomique, bio-informatique, etc.), les systèmes informatiques se complexifient et augmentent en taille (nombre de composants de calcul, mémoire et capacité de stockage). L’accroissement de la complexité de ces systèmes se traduit par une évolution de leur architecture vers une hétérogénéité des technologies de calcul et des modèles de programmation. La gestion harmonieuse de cette hétérogénéité, l’optimisation des ressources et la minimisation de la consommation constituent des défis techniques majeurs dans la conception des futurs systèmes informatiques.Cette thèse s’adresse à un domaine de cette complexité en se focalisant sur les sous-systèmes à mémoire partagée où l’ensemble des processeurs partagent un espace d’adressage commun. Les travaux porteront essentiellement sur l’implémentation d’un protocole de cohérence de cache et de consistance mémoire, sur une architecture extensible et sur la méthodologie de validation de cette implémentation.Dans notre approche, nous avons retenu les processeurs 64-bits d’ARM et des co-processeurs génériques (GPU, DSP, etc.) comme composants de calcul, les protocoles de mémoire partagée AMBA/ACE et AMBA/ACE-Lite ainsi que l’architecture associée « CoreLink CCN » comme solution de départ. La généralisation et la paramètrisation de cette architecture ainsi que sa validation dans l’environnement de simulation Gem5 constituent l’épine dorsale de cette thèse.Les résultats obtenus à la fin de la thèse, tendent à démontrer l’atteinte des objectifs fixésIn response to the growing demand for performance by a wide variety of applications (eg, financial modeling, sub-atomic simulation, bioinformatics, etc.), computer systems become more complex and increase in size (number of computing components, memory and storage capacity). The increased complexity of these systems results in a change in their architecture towards a heterogeneous computing technologies and programming models. The harmonious management of this heterogeneity, resource optimization and minimization of consumption are major technical challenges in the design of future computer systems.This thesis addresses a field of this complexity by focusing on shared memory subsystems where all processors share a common address space. Work will focus on the implementation of a cache coherence and memory consistency on an extensible architecture and methodology for validation of this implementation.In our approach, we selected processors 64-bit ARM and generic co-processor (GPU, DSP, etc.) as components of computing, shared memory protocols AMBA / ACE and AMBA / ACE-Lite and associated architecture "CoreLink CCN" as a starting solution. Generalization and parameterization of this architecture and its validation in the simulation environment GEM5 are the backbone of this thesis.The results at the end of the thesis, tend to demonstrate the achievement of objectives
17
Haji, Rasouli Aso. "The cone shaped settlement of Kandovan: A continuation of building traditions." Thesis, Queensland University of Technology, 2018. https://eprints.qut.edu.au/121354/1/Aso_Haji%20Rasouli_Thesis.pdf.
Full textAbstract:
The 850-year-old settlement of Kandovan, Iran, is the last example of an inhabited cone-shaped architecture that has maintained its socio-cultural cohesion. However, with the arrival of mass tourism during the 21st century, this status quo has become increasingly untenable due to significant changes to its socio-cultural context. The findings of this study showed that these changes have resulted in substantial modifications to its architecture. It is expected that the results of this study will provide a foundation for the future management and preservation of this unique settlement.
18
Sommer, Renee. "Fiber reinforced polymer (FRP) pultruded shape structural connections." Kansas State University, 2011. http://hdl.handle.net/2097/13123.
Full textAbstract:
Master of ScienceDepartment of Architectural Engineering and Construction Science
Kimberly Waggle Kramer
This report discusses the two main types of structural connections used for fiber reinforced polymer (FRP) pultruded shapes, which are mechanical and bonded connections. The most common types of mechanical and bonded connections for FRP pultruded shapes are bolted and adhesively bonded joints respectively, and the advantages and disadvantages of each are discussed. Bolted connections are the most common type of connection used for FRP pultruded shapes and are therefore the focus of this report. Limit states and critical stresses for FRP bolted connections are explained along with the appropriate material properties that are needed to determine them. A simplified mechanics approach to determining the stresses in the FRP material and connection is presented along with a design procedure for FRP connections. A design example is given for a simple beam-to-column shear connection using three materials: FRP pultruded shapes, W-flange steel shapes, and wood sawn lumber in which the beam-to-column shear connection is compared. It is found that the FRP connection is comparable to the steel and wood connections, and all three are able to meet the requirements for the loading conditions given with reasonable results. Possible uses for FRP that would be more ideal than using steel or wood members are presented and areas that still need to be developed or require further research are discussed.
19
Govindaswamy, Kirthilakshmi. "An API for adaptive loop scheduling in shared address space architectures." Master's thesis, Mississippi State : Mississippi State University, 2003. http://sun.library.msstate.edu/ETD-db/theses/available/etd-07082003-122028/restricted/kirthi%5Fthesis.pdf.
Full text
20
Gullström, Charlie. "Presence Design : Mediated Spaces Extending Architecture." Doctoral thesis, KTH, Arkitektur, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-24448.
Full textAbstract:
This thesis is a contribution to design-led research and addresses a readership in the fields of architecture as well as in media and communications. In juxtaposing the tools of the designer (e.g. drafting, prototyping, visual/textual/spatial forms of montage) with those of architectural theory, this thesis seeks to extend the disciplinary boundaries of architecture by observing its assimilation of other media practices. Its primary contribution is to architectural design and theory, and its aims are twofold: Firstly, this thesis applies the concepts of virtual and mediated space to architecture, proposing an extended architectural practice that assimilates the concept of remote presence. Through realized design examples as well as through the history and theory of related concepts, the thesis explores what designing mediated spaces and designing for presence entails for the practicing architect. As a fusion of architecture and media technology, video-mediated spaces facilitate collaborative practices across spatial extensions while simultaneously fostering novel and environmentally sustainable modes of communication. The impact of presence design on workplace design is examined. As an extended practice also calls for an extended discourse, a preliminary conceptual toolbox is proposed. Concepts are adapted from related visual practices and tested on design prototypes, which arise from the author’s extensive experience in designing work and learning spaces. Secondly, this thesis outlines presence design as a transdisciplinary aesthetic practice and discusses the potential contribution of architects to a currently heterogeneous research field, which spans media space research, cognitive science, (tele)presence research, interaction design, ubiquitous computing, second-order cybernetics, and computer-supported collaborative work. In spite of such diversity, design and artistic practices are insufficiently represented in the field. This thesis argues that presence research and its discourse is characterised by sharp disciplinary boundaries and thereby identifies a conceptual gap: presence research typically fails to integrate aesthetic concepts that can be drawn from architecture and related visual practices. It is an important purpose of this thesis to synthesize such concepts into a coherent discourse. Finally, the thesis argues that remote presence through the proposed synthesis of architectural and technical design creates a significantly expanded potential for knowledge sharing across time and space, with potential to expand the practice and theory of architecture itself. The author’s design-led research shows that mediated spaces can provide sufficient audiovisual information about the remote space(s) and other person(s), allowing the subtleties of nonverbal communication to inform the interaction. Further, in designing for presence, certain spatial features have an effect on the user’s ability to experience a mediated spatial extension, which in turn, facilitates mediated presence. These spatial features play an important role in the process through which trust is negotiated, and hence has an impact on knowledge sharing. Mediated presence cannot be ensured by design, but by acknowledging the role of spatial design in mediated spaces, the presence designer can monitor and, in effect, seek to reduce the ‘friction’ that otherwise may inhibit the experience of mediated presence. The notion of ‘friction’ is borrowed from a context of knowledge sharing in collaborative work practices. My expanded use of the term ‘design friction’ is used to identify spatial design features which, unaddressed, may be said to impose friction and thus inhibit and impact negatively on the experience of presence. A conceptual tool-box for presence design is proposed, consisting of the following design concepts: mediated gaze, spatial montage, active spectatorship, mutual gaze, shared mediated space, offscreen space, lateral and peripheral awareness, framing and transparency. With their origins in related visual practices these emerge from the evolution of the concept of presence across a range of visual cultures, illuminating the centrality of presence design in design practice, be it in the construction of virtual pictorial space in Renaissance art or the generative design experiments of prototypical presence designers, such as Cedric Price, Gordon Pask and numerous researchers at MIT Media Lab, Stanford Institute and Xerox PARC.QC 20100909
21
Gustavsson, Ebba. "Kultur & Kongress : Ett gestaltningsförslag till ett nytt Kulturhus i Eskilstuna utifrån möjligheter för samnyttjande av lokaler." Thesis, Luleå tekniska universitet, Arkitektur och vatten, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-70181.
Full textAbstract:
As the population increases, the pressure on urban development is increasing. One of the strategies to meet this challenge, is by densification. But in order to provide the city sufficient community service, the municipality has to try innovative solutions. A potential solution is the utilization of premises and resources, and flexible use. Considering this, the municipality in Eskilstuna has recently launched a project to investigate opportunities for a Culture House in combination with a Congress Hall. The idea is that the needs will be co-located and utilized. The purpose of this work is to develop a program plan for the project in Eskilstuna, based on a given location and providing activities. The program plan should be partly based on an investigation of which activities that are able to share premises. The frames for the real project are not yet set, which means that this work is to be considered as a hypothesis. The methodology for the work can be described as a qualitative and combined methodology. The main structure consists of the literature Idea Work, supported by complementary methods for data collection and site analysis. Based on the investigation, the central location and its extensive content, a large volume was created that should be integrated and illustrative at the same time. The internal structure should satisfy the individual needs of the business, the need for shared utilization, and the existing movement in the neighborhood. The entrances and the passage on the first floor of the building consists of a high-ceiling atrium, which will give a public and transparent feeling. The organic form will contribute to the visualization in the rectilinear city and the verticality will give height in the façade. The vertical divisions have a rhythm that will reflect the musical content inside the building. The program schedule is preliminary and not detailed, but gives an initial picture of how a cultural house in combination with Congress can take place at the chosen site. Further studies need to be done, both in the study of utilization and the design. The conclusion is that opportunities for shared exploitation exist within the framework studied. However, the project has been complex. The study of shared exploitation combined with the extensive content of the cultural center makes the detail level low. There is also a general limitation in the form of support and strategies in the field of program work in co- operation projects with shared premises, which would be interesting to look at in continued work.I takt med att befolkningen ökar, ökar trycket på utvecklingen av städerna. En av stretegierna för att möta detta är förtätning. Men för att en tät stad ska kunna erbjuda tillräcklig samhällsservice krävs att kommunen testar innovativa lösningar. En potentiell lösning är samnyttjande av lokaler och resurser. I ljuset av detta har Eskilstuna Kommun nyligen startat ett projekt där möjligheter för ett Kulturhus i kombination med kongresshall ska utredas. Tanken är att behoven ska samlokaliseras och samnyttjas. Detta arbete syftar till att ta fram en programskiss för projektet i Eskilstuna, utifrån en given plats och givna verksamheter. Programskissen ska delvis präglas av en utredning om vilka verksamheter som har möjlighet att samnyttja lokaler. Ramarna för det verkliga projektet är ännu inte satta, vilket gör att detta arbete är att betrakta som en hypotes. Metodiken för arbetet kan beskrivas som en kvalitativ och kombinerad metodik. Huvudstrukturen utgörs av litteraturen Idea Work, som stöttas av kompletterande metoder vid insamling av data och vid platsanalyser. Utifrån utredningen, den centrala placeringen och dess omfattande innehåll skapades en stor volym som ska vara integrerad och åskådlig på samma gång. Den inre strukturen ska tillfredsställa verksamheters enskilda behov, samnyttjandets behov, samt den befintliga rörelsen i kvarteret. Stråket på byggnadens första plan utgörs av ett atrium med högt i tak, som ska ge en publik och transparent känsla. Den organiska formen ska bidra till åskådligheten i den rätlinjiga staden och vertikaliteten ska ge spänst åt fasaden. De vertikala indelningarna har en rytm som ska återspegla husets musikaliska innehåll. Programskissen är preliminär och inte detaljerad, men ger en initial bild av hur ett kulturhus i kombination med kongress kan ta form på den utvalda platsen. Vidare studier behöver göras, både inom studien om samnyttjandet samt gestaltningen. Slutsatsen blir att möjligheter till samnyttjande finns, inom de ramar som studerats. Projektet har dock varit komplext. Studien om samnyttjandet i kombination med kulturhusets omfattande innehåll gör att detaljnivån är låg. Det finns också en begränsning i form av stöd och strategier i frågan om programarbete vid samnyttjansprojekt, vilket skulle vara intressant att titta på i ett fortsatt arbete.
22
Zhang, Zimo. "Effect Of Chain End Functional And Chain Architecture On Surface Segregation." University of Akron / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=akron1498513871263316.
Full text
23
Nicholas, Paul, and not supplied. "Approaches to Interdependency: early design exploration across architectural and engineering domains." RMIT University. Architecture and Design, 2008. http://adt.lib.rmit.edu.au/adt/public/adt-VIT20081204.151243.
Full textAbstract:
While 3D digital design tools have extended the reach of architectural and engineering designers within their own domains, restrictions on the use of the tools and an approach to practice whereby the architect designs (synthesises) and the engineer solves (analyses) - in that order ¡V have limited the opportunities for interdependent modes of interaction between the two disciplines during the early design phase. While it is suggested that 3D digital design tools can facilitate a more integrated approach to design exploration, this idea remains largely untested in practice. The central proposition of my research is that that 3D digital tools can enable interdependencies between crucial aspects of architectural and engineering design exploration during the early design phase which, before the entry of the computer, were otherwise impossible to affect. I define interdependency as a productive form of practice enabled by mutual and lateral dependence. Interdependent parties use problem solving processes that meet not only their own respective goals, but also those of others, by constructively engaging difference across their boundaries to actively search for solutions that go beyond the limits of singular domains. Developed through practice-based project work undertaken during my 3 year postgraduate internship within the Melbourne Australia office of the engineering firm Arup, my research explores new and improved linkages between early design exploration, analysis and making. The principal contribution of my research is to explore this problem from within the context, conditi ons and pressures of live practice. To test the research proposition this dissertation engages firstly with available literature from the fields of organisation theory and design, secondly with information gathered from experts in the field principally via interview, and lastly with processes of testing through practice-based (as opposed to university-based) project work. The dissertation is organized as follows: The Introductory Chapter outlines the central hypothesis, the current state of the discourse, and my motivations for conducting this research. I summarise the structure of my research, and the opportunities and limitations that have framed its ambitions. Chapter Two, Approach to Research and Method, details the constraints and possibilities of the Embedded Research within Architectural Practice context, within which this work has been undertaken, and describes the Melbourne office of Arup, the practice with whom I have been embedded. These contexts have led to the selection of a particular set of ethnographic research instruments, being the use of semi-structured interviews and the undertaking of practice-based studies as a participant-observer. These modes of testing are explained, and the constraints, limitations and requirements associated with them described. Within Chapter Three, Factors for Separation and Integration in Architectural and Engineering Design, I examine selected design literature to detail several factors impacting upon the historic and contemporary relationship between architects and engineers, and to introduce the problem towards which this thesis is addressed. I describe a process of specialisation that has led architects and engineers to see different aspects of a common problem, detail the historical factors for separation, the current relationship between domains and the emerging idea of increased integration during the early design phase. The aim of this section is primarily contextual - to introduce the characters and to understand why their interaction can be difficult - and investigation occurs through the concepts of specialisation and disciplinary roles. Chapter Four, Unravelling Interdependency, establishes an understanding of interdependency through the concept of collaboration. While I differentiate interdependency from collaboration because of the inconsistent manner in which the latter term is employed, the concept of collaboration is useful to initialise my understanding of interdependency because it, as opposed to the closely linked processes of cooperation and coordination, is recognised as being characterised by interdependency, and in fact is a viewed as a response specific to wider conditions of interdependency. From the literature, I identify four sites of intersection crucial to an understanding of interdependency; these are differing perceptions, shared and creative problem solving, communication and trust. These themes, which correlate with my practice experience at Arup Melbourne, are developed to introduce the concepts and vocabulary underlying my research. Chapter Five, Intersections & Interdependency between Architects and Engineers, grounds these four sites of intersection within contemporary issues of digital architectural and engineering practice. Each site is developed firstly through reference to design literature and secondly through the experiences and understandings of senior Arup practitioners as captured through my interviews. The views and experiences of these practitioners are used to locate digital limits to, and potential solutions for, interdependent design exploration between architects and engineers as they are experienced within and by practice. Through this combination of design literature and grounded experience, I extend: * the understanding of differing perceptions through reference to problems associated with digital information transfer. * the understanding of joint and creative problem solving by connecting it to the notion of performance-based design. * the understanding of communication by focussing it upon the idea of back propagating design information. * the understanding of trust by connecting it to the management and reduction of perceived complexity and risk. Chapter Six, Testing through Projects, details the project studies undertaken within this research. These studies are grouped into three discourses, characterized as Design(Arch)Design(Eng), Design|Analysis and Design|Making. As suggested by the concurrency operator that separates the two terms that constitute each of the three labels, each discourse tests how architectural and engineering explorations might execute in parallel. The section Design(Arch)|Design(Eng) reports projects that use a common language of geometry to link architectural and engineering design ideas through geometric interpretation. The section Design|Analysis reports projects in which analytical tools have been used generatively to actively guide and synthesise design exploration. The final section, Design|Making, reports projects in which the architectural and engineering design processes are synthesised around the procurement of fabrication information. Conclusions are then drawn and discussed in Chapter Seven. In evaluating the research I discuss how 3D digital design tools have enabled alternative approaches that resolve issues associated with differing perceptions, establishing common meanings, communication and trust. I summarise how these approaches have enabled increased interdependency in architect engineer interaction. Lastly, I draw together the impacts of intersecting 3D digital aspects of architectural and engineering design exploration during the early design phase, and indicate those aspects that require further analysis and research.
24
Means, Daniel Eric. "Identification of Physical Changes to a Steel Frame." DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/246.
Full textAbstract:
The thesis utilized physical testing and computer modeling to determine the feasibility of identifying a change to the mass or stiffness of a steel frame. Physical testing was performed using an accelerometer, linear shaker, and arbitrary function generator. Two methods of laboratory testing were developed: ambient vibration testing (AVT) and forced vibration testing (FVT). AVT was able to preliminarily identify the natural frequencies and mode shapes of the frame. FVT was able to precisely identify four distinct natural frequencies, mode shapes, and damping ratios. The baseline frame then underwent two physical changes: the addition of mass to its roof, and the addition of braces along one of its sides. FVT was used again to determine the natural frequencies, mode shapes, and damping ratios of the newly changed structure.
An ETABS computer model was developed to represent the frame. This baseline model produced natural frequencies and mode shapes that closely matched the values determined by FVT. The mass and stiffness of this baseline model were then changed multiple times through the addition of mass and braces at various locations on the model. The frequencies and mode shapes were recorded for each change.
Two methods were developed to identify the changes to the steel frame. The first method was able to determine which one of the models best represented a single change to the structure (adding mass to its roof). The second method was able to determine the combination of models that best represented the two concurrent changes to the structure (adding mass to its roof and braces to its sides). Both methods utilized the percent differences of each altered computer model relative to the original, and each method satisfactorily identified its respective physical alteration.
25
González, Bautista David. "Architecture fonctionnelle pour la planification des trajectoires des véhicules automatisés dans des environnements complexes." Thesis, Paris Sciences et Lettres (ComUE), 2017. http://www.theses.fr/2017PSLEM002/document.
Full textAbstract:
Un des buts de la recherche et du développement des systèmes de transport intelligents est d'augmenter le confort et la sécurité des passagers, tout en réduisant la consommation d'énergie, la pollution de l'air et le temps de déplacement. L'introduction de voitures complètement autonomes sur la voie publique nécessite la résolution d'un certain nombre de problèmes techniques et en particulier de disposer de modules de planification de trajectoire robustes. Ce travail de thèse s'inscrit dans ce cadre. Il propose une architecture modulaire pour la planification de trajectoire d'un véhicule autonome. La méthode permet de générer des trajectoires constituées de courbes interpolées adaptées à des environnements complexes comme des virages, des ronds-points, etc., tout en garantissant la sécurité et le confort des passagers. La prise en compte de l'incertitude des systèmes de perception, des limites physiques du véhicule, de la disposition des routes et des règles de circulation est aussi assurée dans le calcul de la trajectoire. L'algorithme est capable de modifier en temps réel la trajectoire prédéfinie de façon à éviter les collisions. Le calcul de la nouvelle trajectoire maintient les accélérations latérales à leur minimum, assurant ainsi le confort du passager. L'approche proposée a été évaluée et validée dans des environnements simulés et sur des véhicules réels. Cette méthode permet d'éviter les obstacles statiques et dynamiques repérés par le système de perception.Un système d'aide à la conduite pour le contrôle partagé basé sur cette architecture est introduit. Il prend en compte l'arbitrage, la surveillance et le partage de la conduite tout en maintenant le conducteur dans la boucle de contrôle. Il laisse le conducteur agir tant qu'il n'y a pas de danger et interagit avec le conducteur dans le cas contraire. L'algorithme se décompose donc en deux processus : 1) évaluation du risque et, s'il y a un risque avéré 2) partage du contrôle à l'aide de signaux haptiques via le volant.La méthode de planification de trajectoire présentée dans cette thèse est modulaire et générique. Elle peut être intégrée facilement dans toute architecture d'un véhicule autonomeDevelopments in the Intelligent Transportation Systems (ITS) field show promising results at increasing passengers comfort and safety, while decreasing energy consumption, emissions and travel time. In road transportation, the appearance of automated vehicles is significantly aiding drivers by reducing some driving-associated tedious tasks. However, there is still a long way to go before making the transition between automated vehicles (i.e. vehicles with some automated features) and autonomous vehicles on public roads (i.e. fully autonomous driving), specially from the motion planning point of view. With this in mind, the present PhD thesis proposes the design of a generic modular architecture for automated vehicles motion planning. It implements and improves curve interpolation techniques in the motion planning literature by including comfort as the main design parameter, addressing complex environments such as turns, intersections and roundabouts. It will be able to generate suitable trajectories that consider measurements' incertitude from the perception system, vehicle’s physical limits, the road layout and traffic rules. In case future collision states are detected, the proposed approach is able to change---in real-time---the current trajectory and avoid the obstacle in front. It permits to avoid obstacles in conflict with the current trajectory of the ego-vehicle, considering comfort limits and developing a new trajectory that keeps lateral accelerations at its minimum. The proposed approach is tested in simulated and real urban environments, including turns and two-lane roundabouts with different radii. Static and dynamic obstacles are considered as to face and interact with other road actors, avoiding collisions when detected. The functional architecture is also tested in shared control and arbitration applications, focusing in keeping the driver in the control loop to addition the system's supervision over drivers’ knowledge and skills in the driving task. The control sharing advanced driver assistance system (ADAS) is proposed in two steps: 1) risk assessment of the situation in hand, based on the optimal trajectory and driving boundaries identified by the motion planning architecture and; 2) control sharing via haptic signals sent to the driver through the steering wheel. The approach demonstrates the modularity of the functional architecture as it proposes a general solution for some of today's unsolved challenges in the automated driving field
26
Heshmati, Elnaz. "A Modular Shared Home : Approaching affordable housing through sharing habits and modularity." Thesis, Umeå universitet, Arkitekthögskolan vid Umeå universitet, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-173531.
Full textAbstract:
The world’s population is increasing and every day, more people are coming to the cities. People are constantly relocating their houses for meeting their needs. As societies are growing and mobility in cities is raising, cities would face challenges like accommodating the population inexpensively and providing good quality of life and stable social and environmental infrastructure for them. However, due to the fixed regulated and unadaptable construction market, the architecture doesn’t meet the changing needs of inhabitants, therefore, every day the housing market is more unaffordable because of the high demand for housing developments, lands scarce, etc. Architecture needs to be flexible to adjust itself to the current market. Since most of the relocations and high demands for building new housing projects occur when built spaces fail to meet their occupants’ growing needs. This thesis tries to find an alternative framework for designing a flexible one whereby architecture is shaped by the user’s needs and can adjust itself in a long period. This thesis also works on designing an environment that responds to the social, economic, and environmental needs of residents as one united community. Therefore, it uses a shared living idea as an affordable alternative for making houses cheaper and creating a more stable social environment for inhabitants. The content of this thesis is categorized upon the following narrative. Firstly, this thesis is trying to deepen its understanding of the matter of shared living and its possible advantages and disadvantages for producing stable social and economical infrastructure. For this purpose, it analyses a notion of shared living and shared economy through studying successful case studies. Secondly, by studying and utilizing metabolic design criteria, the thesis will form an understanding of a more sustainable approach toward architecture and built environment to design an affordable housing system that provides high quality of life for inhabitants through responding to their needs. Thirdly, the thesis will frame its design strategy based on shared living perspective and metabolic design criteria. The thesis then will illustrate its steps and methods to achieve flexible architecture through designing its module, structure, and material. Lastly, it will discuss its findings on how the shared living approach and metabolic philosophy can aid architects to design more sustainable housing units that can meet their resident’s needs through a long period and make strong social, economic, and environmental infrastructure.
27
Chakraborty, Sourav. "High Performance and Scalable Cooperative Communication Middleware for Next Generation Architectures." The Ohio State University, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1563484522149971.
Full text
28
Staub, Nicolas. "Models, algorithms and architectures for cooperative manipulation with aerial and ground robots." Thesis, Toulouse 3, 2018. http://www.theses.fr/2018TOU30169/document.
Full textAbstract:
Les dernières années ont vu le développement de recherches portant sur l'interaction physique entre les robots aériens et leur environnement, accompagné de l'apparition de nombreux nouveaux systèmes mécaniques et approches de régulation. La communauté centrée autour de la robotique aérienne observe actuellement un déplacement de paradigmes des approches classiques de guidage, de navigation et de régulation vers des tâches moins triviales, telle le développement de l'interaction physique entre robots aériens et leur environnement. Ceci correspond à une extension des tâches dites de manipulation, du sol vers les airs. Cette thèse contribue au domaine de la manipulation aérienne en proposant un nouveau concept appelé MAGMaS, pour " Multiple Aerial Ground Manipulator System ". Les motivations qui ont conduites à l'association de manipulateurs terrestres et aériens pour effectuer des tâches de manipulation coopérative, résident dans une volonté d'exploiter leurs particularités respectives. Les manipulateurs terrestres apportant leur importante force et les manipulateurs aériens apportant leur vaste espace de travail. La première contribution de cette thèse présente une modélisation rigoureuse des MAGMaS. Les propriétés du système ainsi que ses possibles extensions sont discutées. Les méthodes de planning, d'estimation et de régulation nécessaire à l'exploitation des MAGMaS pour des tâches de manipulation collaborative sont dérivées. Ce travail propose d'exploiter les redondances des MAGMaS grâce à un algorithme optimal d'allocation de forces entre les manipulateurs. De plus, une méthode générale d'estimation de forces pour robots aériens est introduite. Toutes les techniques et les algorithmes présentés dans cette thèse sont intégrés dans une architecture globale, utilisée à la fois pour la simulation et la validation expérimentale. Cette architecture est en outre augmentée par l'addition d'une structure de télé-présence, afin de permettre l'opération à distances des MAGMaS. L'architecture générale est validée par une démonstration de levage de barre, qui est une application représentative des potentiels usages des MAGMaS. Une autre contribution relative au développement des MAGMaS consiste en une étude exploratoire de la flexibilité dans les objets manipulés par un MAGMaS. Un modèle du phénomène vibratoire est dérivé afin de mettre en exergue ses propriétés en termes de contrôle. La dernière contribution de cette thèse consiste en une étude exploratoire sur l'usage des actionneurs à raideur variable dans les robots aériens, dotant ces systèmes d'une compliance mécanique intrinsèque et de capacité de stockage d'énergie. Les fondements théoriques sont associés à la synthèse d'un contrôleur non-linéaire. L'approche proposée est validée par le biais d'expériences reposant sur l'intégration d'un actionneur à raideur variable léger sur un robot aérienIn recent years, the subject of physical interaction for aerial robots has been a popular research area with many new mechanical designs and control approaches being proposed. The aerial robotics community is currently observing a paradigm shift from classic guidance, navigation, and control tasks towards more unusual tasks, for example requesting aerial robots to physically interact with the environment, thus extending the manipulation task from the ground into the air. This thesis contributes to the field of aerial manipulation by proposing a novel concept known has Multiple Aerial-Ground Manipulator System or MAGMaS, including what appears to be the first experimental demonstration of a MAGMaS and opening a new route of research. The motivation behind associating ground and aerial robots for cooperative manipulation is to leverage their respective particularities, ground robots bring strength while aerial robots widen the workspace of the system. The first contribution of this work introduces a meticulous system model for MAGMaS. The system model's properties and potential extensions are discussed in this work. The planning, estimation and control methods which are necessary to exploit MAGMaS in a cooperative manipulation tasks are derived. This works proposes an optimal control allocation scheme to exploit the MAGMaS redundancies and a general model-based force estimation method is presented. All of the proposed techniques reported in this thesis are integrated in a global architecture used for simulations and experimental validation. This architecture is extended by the addition of a tele-presence framework to allow remote operations of MAGMaS. The global architecture is validated by robust demonstrations of bar lifting, an application that gives an outlook of the prospective use of the proposed concept of MAGMaS. Another contribution in the development of MAGMaS consists of an exploratory study on the flexibility of manipulated loads. A vibration model is derived and exploited to showcase vibration properties in terms of control. The last contribution of this thesis consists of an exploratory study on the use of elastic joints in aerial robots, endowing these systems with mechanical compliance and energy storage capabilities. Theoretical groundings are associated with a nonlinear controller synthesis. The proposed approach is validated by experimental work which relies on the integration of a lightweight variable stiffness actuator on an aerial robot
29
Olsen, Tim. "Realizing Shared Services - A Punctuated Process Analysis of a Public IT Department." Digital Archive @ GSU, 2012. http://digitalarchive.gsu.edu/cis_diss/49.
Full textAbstract:
IT services are increasingly being offered via a shared service model. This model promises the benefits of centralization and consolidation, as well as an increased customer satisfaction. Adopting shared services is not easy as it necessitates a major organizational change, with few documented exemplars to guide managers. This research explores a public IT unit’s realization of shared services with the intent to improve the transparency of its value proposition to their stakeholders. An ethnographic field study enabled in-situ data collection over a 24-month period. We analyzed the resulting, rich process data using the Punctuated Socio-Technical IS Change (PSIC) model. This resulted in several contributions: an explanatory account of shared services realization, an empirically grounded punctuated process model with seventeen critical incidents, and twelve key lessons for practitioners. Several extensions to extant process research methods are developed. These contributions combine to form a detailed and nuanced understanding of the process of realizing IT shared services at a large public university over a multi-year period.
30
Paakkulainen, Elina. "Better Alone." Thesis, KTH, Arkitektur, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-280713.
Full textAbstract:
My thesis project, Better Alone focuses on single person households from a perspective of loneliness. The objective has been to find an architectural solution to decrease experienced loneliness. In this project I intend to address the issue and design a way of living that can relieve the experience of involuntary loneliness. I have used two main strategies: the first is to provide space for social interaction in connection to the home and to create reasons to enter and linger in these spaces. The second main strategy is to blur or stretch the border that separates the home into privacy through visibility. The project's site is in southern Stockholm, in between the neighborhoods Hammarbyhöjden and Hammarby sjöstad, a fairly central location. The site's most prominent characteristic is the fact that it is a steep slope. At the bottom of the slope runs Hammarbyvägen, which is a fairly busy road. Together these two aspects create a barrier between the neighborhoods of Hammarby sjöstad and Hammarbyhöjden, these are challenges that I have addressed in the project.
31
Löf, Henrik. "Iterative and Adaptive PDE Solvers for Shared Memory Architectures." Doctoral thesis, Uppsala universitet, Avdelningen för teknisk databehandling, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-7136.
Full textAbstract:
Scientific computing is used frequently in an increasing number of disciplines to accelerate scientific discovery. Many such computing problems involve the numerical solution of partial differential equations (PDE). In this thesis we explore and develop methodology for high-performance implementations of PDE solvers for shared-memory multiprocessor architectures. We consider three realistic PDE settings: solution of the Maxwell equations in 3D using an unstructured grid and the method of conjugate gradients, solution of the Poisson equation in 3D using a geometric multigrid method, and solution of an advection equation in 2D using structured adaptive mesh refinement. We apply software optimization techniques to increase both parallel efficiency and the degree of data locality. In our evaluation we use several different shared-memory architectures ranging from symmetric multiprocessors and distributed shared-memory architectures to chip-multiprocessors. For distributed shared-memory systems we explore methods of data distribution to increase the amount of geographical locality. We evaluate automatic and transparent page migration based on runtime sampling, user-initiated page migration using a directive with an affinity-on-next-touch semantic, and algorithmic optimizations for page-placement policies. Our results show that page migration increases the amount of geographical locality and that the parallel overhead related to page migration can be amortized over the iterations needed to reach convergence. This is especially true for the affinity-on-next-touch methodology whereby page migration can be initiated at an early stage in the algorithms. We also develop and explore methodology for other forms of data locality and conclude that the effect on performance is significant and that this effect will increase for future shared-memory architectures. Our overall conclusion is that, if the involved locality issues are addressed, the shared-memory programming model provides an efficient and productive environment for solving many important PDE problems.
32
Sankaranarayanan, Ganesh. "Virtual coupling schemes for position coherency in networked haptic virtual environments /." Thesis, Connect to this title online; UW restricted, 2007. http://hdl.handle.net/1773/5929.
Full text
33
Glowinkowska, Mira. "Continuous Space : Transforming a Car Park Into a Co-House." Thesis, KTH, Arkitektur, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-223391.
Full textAbstract:
The cohouse is a smarter type of housing, where we can find solutions through sharing. It combines the home with the social meeting place, resembling an indoor/outdoor fusion. My intention with this project is to create a housing that is unfinished, a continuous project. Where the residents are encouraged to try other ways of living. Where the rooms are not only made up by walls but also created by the bodies of people, forever changing and rearranged - a continuous space.
34
Holsapple, Stephen Alan. "DSM64: A DISTRIBUTED SHARED MEMORY SYSTEM IN USER-SPACE." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/725.
Full textAbstract:
This paper presents DSM64: a lazy release consistent software distributed shared memory (SDSM) system built entirely in user-space. The DSM64 system is capable of executing threaded applications implemented with pthreads on a cluster of networked machines without any modifications to the target application. The DSM64 system features a centralized memory manager [1] built atop Hoard [2, 3]: a fast, scalable, and memory-efficient allocator for shared-memory multiprocessors.
In my presentation, I present a SDSM system written in C++ for Linux operating systems. I discuss a straight-forward approach to implement SDSM systems in a Linux environment using system-provided tools and concepts avail- able entirely in user-space. I show that the SDSM system presented in this paper is capable of resolving page faults over a local area network in as little as 2 milliseconds.
In my analysis, I present the following. I compare the performance characteristics of a matrix multiplication benchmark using various memory coherency models. I demonstrate that matrix multiplication benchmark using a LRC model performs orders of magnitude quicker than the same application using a stricter coherency model. I show the effect of coherency model on memory access patterns and memory contention. I compare the effects of different locking strategies on execution speed and memory access patterns. Lastly, I provide a comparison of the DSM64 system to a non-networked version using a system-provided allocator.
35
Rihani, Hamza. "Analyse temporelle des systèmes temps-réels sur architectures pluri-coeurs." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAM074/document.
Full textAbstract:
La prédictibilité est un aspect important des systèmes temps-réel critiques. Garantir la fonctionnalité de ces systèmespasse par la prise en compte des contraintes temporelles. Les architectures mono-cœurs traditionnelles ne sont plussuffisantes pour répondre aux besoins croissants en performance de ces systèmes. De nouvelles architectures multi-cœurssont conçues pour offrir plus de performance mais introduisent d'autres défis. Dans cette thèse, nous nous intéressonsau problème d’accès aux ressources partagées dans un environnement multi-cœur.La première partie de ce travail propose une approche qui considère la modélisation de programme avec des formules desatisfiabilité modulo des théories (SMT). On utilise un solveur SMT pour trouverun chemin d’exécution qui maximise le temps d’exécution. On considère comme ressource partagée un bus utilisant unepolitique d’accès multiple à répartition dans le temps (TDMA). On explique comment la sémantique du programme analyséet le bus partagé peuvent être modélisés en SMT. Les résultats expérimentaux montrent une meilleure précision encomparaison à des approches simples et pessimistes.Dans la deuxième partie, nous proposons une analyse de temps de réponse de programmes à flot de données synchroness'exécutant sur un processeur pluri-cœur. Notre approche calcule l'ensemble des dates de début d'exécution et des tempsde réponse en respectant la contrainte de dépendance entre les tâches. Ce travail est appliqué au processeur pluri-cœurindustriel Kalray MPPA-256. Nous proposons un modèle mathématique de l'arbitre de bus implémenté sur le processeur. Deplus, l'analyse de l'interférence sur le bus est raffinée en prenant en compte : (i) les temps de réponseet les dates de début des tâches concurrentes, (ii) le modèle d'exécution, (iii) les bancsmémoires, (iv) le pipeline des accès à la mémoire. L'évaluation expérimentale est réalisé sur desexemples générés aléatoirement et sur un cas d'étude d'un contrôleur de volPredictability is of paramount importance in real-time and safety-critical systems, where non-functional properties --such as the timing behavior -- have high impact on the system's correctness. As many safety-critical systems have agrowing performance demand, classical architectures, such as single-cores, are not sufficient anymore. One increasinglypopular solution is the use of multi-core systems, even in the real-time domain. Recent many-core architectures, such asthe Kalray MPPA, were designed to take advantage of the performance benefits of a multi-core architecture whileoffering certain predictability. It is still hard, however, to predict the execution time due to interferences on sharedresources (e.g., bus, memory, etc.).To tackle this challenge, Time Division Multiple Access (TDMA) buses are often advocated. In the first part of thisthesis, we are interested in the timing analysis of accesses to shared resources in such environments. Our approach usesSatisfiability Modulo Theory (SMT) to encode the semantics and the execution time of the analyzed program. To estimatethe delays of shared resource accesses, we propose an SMT model of a shared TDMA bus. An SMT-solver is used to find asolution that corresponds to the execution path with the maximal execution time. Using examples, we show how theworst-case execution time estimation is enhanced by combining the semantics and the shared bus analysis in SMT.In the second part, we introduce a response time analysis technique for Synchronous Data Flow programs. These are mappedto multiple parallel dependent tasks running on a compute cluster of the Kalray MPPA-256 many-core processor. Theanalysis we devise computes a set of response times and release dates that respect the constraints in the taskdependency graph. We derive a mathematical model of the multi-level bus arbitration policy used by the MPPA. Further,we refine the analysis to account for (i) release dates and response times of co-runners, (ii)task execution models, (iii) use of memory banks, (iv) memory accesses pipelining. Furtherimprovements to the precision of the analysis were achieved by considering only accesses that block the emitting core inthe interference analysis. Our experimental evaluation focuses on randomly generated benchmarks and an avionics casestudy
36
Shell, Michael David. "Cascaded All-Optical Shared-Memory Architecture Packet Switches Using Channel Grouping Under Bursty Traffic." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4892.
Full textAbstract:
This work develops an exact logical operation model to predict the performance of the all-optical shared-memory architecture (OSMA) class of packet switches and provides a means to obtain a reasonable approximation of OSMA switch performance within certain types of networks, including the Banyan family.
All-optical packet switches have the potential to far exceed the bandwidth capability of their current electronic counterparts. However, all-optical switching technology is currently not mature. Consequently, all-optical switch fabrics and buffers are more constrained in size and can cost several orders of magnitude more than those of electronic switches. The use of shared-memory buffers and/or links with multiple parallel channels (channel grouping) have been suggested as ways to maximize switch performance with buffers of limited size. However, analysis of shared-memory switches is far more difficult than for other commonly used buffering strategies. Obtaining packet loss performance by simulation is often not a viable alternative to modeling if low loss rates or large networks are encountered. Published models of electronic shared-memory packet switches (ESMP) have primarily involved approximate models to allow analysis of switches with a large number of ports and/or buffer cells. Because most ESMP models become inaccurate for small switches, and OSMA switches, unlike ESMP switches, do not buffer packets unless contention occurs, existing ESMP models cannot be applied to OSMA switches. Previous models of OSMA switches were confined to isolated (non-networked), symmetric OSMA switches using channel grouping under random traffic. This work is far more general in that it also encompasses OSMA switches that (1) are subjected to bursty traffic and/or with input links that have arbitrary occupancy probability distributions, (2) are interconnected to form a network and (3) are asymmetric.
37
Barsamian, Yann. "Pic-Vert : une implémentation de la méthode particulaire pour architectures multi-coeurs." Thesis, Strasbourg, 2018. http://www.theses.fr/2018STRAD039/document.
Full textAbstract:
Cette thèse a pour contexte la résolution numérique du système de Vlasov–Poisson (modèle utilisé en physique des plasmas, par exemple dans le cadre du projet ITER) par les méthodes classiques particulaires (PIC pour "Particle-in-Cell") et semi-Lagrangiennes. La contribution principale de notre thèse est une implémentation efficace de la méthode PIC pour architectures multi-coeurs, écrite dans le langage C, dont le nom est Pic-Vert. Notre implémentation (a) atteint un nombre quasi-minimal de transferts mémoires avec la mémoire principale, (b) exploite les instructions vectorielles (SIMD) pour les calculs numériques, et (c) expose une quantité suffisante de parallélisme, en mémoire partagée. Pour mettre notre travail en perspective avec l'état de l'art, nous proposons une métrique permettant de comparer différentes implémentations sur différentes architectures. Notre implémentation est 3 fois plus rapide que d'autres implémentations récentes sur la même architecture (Intel Haswell)In this thesis, we are interested in solving the Vlasov–Poisson system of equations (useful in the domain of plasma physics, for example within the ITER project), thanks to classical Particle-in-Cell (PIC) and semi-Lagrangian methods. The main contribution of our thesis is an efficient implementation of the PIC method on multi-core architectures, written in C, called Pic-Vert. Our implementation (a) achieves close-to-minimal number of memory transfers with the main memory, (b) exploits SIMD instructions for numerical computations, and (c) exhibits a high degree of shared memory parallelism. To put our work in perspective with respect to the state-of-the-art, we propose a metric to compare the efficiency of different PIC implementations when using different multi-core architectures. Our implementation is 3 times faster than other recent implementations on the same architecture (Intel Haswell)
38
Sid, Lakhdar Mohamed Wissam. "Scaling the solution of large sparse linear systems using multifrontal methods on hybrid shared-distributed memory architectures." Thesis, Lyon, École normale supérieure, 2014. http://www.theses.fr/2014ENSL0958/document.
Full textAbstract:
La résolution de systèmes d'équations linéaires creux est au cœur de nombreux domaines d'applications. De même que la quantité de ressources de calcul augmente dans les architectures modernes, offrant ainsi de nouvelles perspectives, la taille des problèmes rencontré de nos jours dans les applications de simulations numériques augmente aussi et de façon significative. L'exploitation des architectures modernes pour la résolution efficace de problèmes de très grande taille devient ainsi un défit a relever, aussi bien d'un point de vue théorique que d'un point de vue algorithmique. L'objectif de cette thèse est d'adresser les problèmes de scalabilité des solveurs creux directs basés sur les méthodes multifrontales en environnements parallèles asynchrones. Dans la première partie de la thèse, nous nous intéressons a l'exploitation du parallélisme multicoeur sur les architectures a mémoire partagée. Nous introduisons une variante de l'algorithme Geist-Ng afin de gérer aussi bien un parallélisme a grain fin, a travers l'utilisation de librairies BLAS séquentiel et parallèle optimisées, que d'un parallélisme a plus gros grain, a travers l'utilisation de parallélisme a base de directives OpenMP. Nous considérons aussi des aspects mémoire afin d'améliorer les performances sur des architectures NUMA: (i) d'une part, nous analysons l'influence de la localité mémoire et utilisons des stratégies d'allocation mémoire adaptatives pour gérer les espaces de travail privés et partagés; (ii) d'autre part, nous nous intéressons au problème de partages de ressources sur les architectures multicoeurs, qui induisent des pénalités en termes de performances. Enfin, afin d'éviter que des ressources ne reste inertes a la fin de l'exécution de leurs taches, et ainsi, afin d'exploiter au mieux les ressources disponibles, nous proposons un algorithme conceptuellement proche de l'approche dite de vol de travail, et qui consiste a assigner les ressources de calculs inactives au taches de travail actives de façon dynamique. Dans la deuxième partie de cette thèse, nous nous intéressons aux architectures hybrides, a base de mémoire partagées et de mémoire distribuées, pour lesquels un travail particulier est nécessaire afin d'améliorer la scalabilité du traitement de problèmes de grande taille. Nous étudions et optimisons tout d'abord les noyaux d'algèbre linéaire danse utilisé dans les méthodes multifrontales en environnent distribué asynchrone, en repensant les variantes right-looking et left-looking de la factorisation LU avec pivotage partiel dans notre contexte distribué. De plus, du fait du parallélisme multicoeurs, la proportion des communications relativement aux calculs et plus importante. Nous expliquons comment construire des algorithmes de mapping qui minimisent les communications entres nœuds de l'arbre de dépendances de la méthode multifrontale. Nous montrons aussi que les communications asynchrones collectives deviennent christiques sur grand nombres de processeurs, et que les broadcasts asynchrones a base d'arbres de broadcast doivent être utilisés. Nous montrons ensuite que dans un contexte multifrontale complètement asynchrone, où plusieurs instances de tels communications ont lieux, de nouveaux problèmes de synchronisation apparaissent. Nous analysons et caractérisons les situations de deadlock possibles et établissons formellement des propriétés générales simples afin de résoudre ces problèmes de deadlock. Nous établissons par la suite des propriétés nous permettant de relâcher les synchronisations induites par la solutions précédentes, et ainsi, d'améliorer les performances. Enfin, nous montrons que les synchronisations peuvent être relâchées dans un solveur creux danse et illustrons les gains en performances, sur des problèmes de grande taille issue d'applications réelles, dans notre environnement multifrontale complètement asynchroneThe solution of sparse systems of linear equations is at the heart of numerous applicationfields. While the amount of computational resources in modern architectures increases and offersnew perspectives, the size of the problems arising in today’s numerical simulation applicationsalso grows very much. Exploiting modern architectures to solve very large problems efficiently isthus a challenge, from both a theoretical and an algorithmic point of view. The aim of this thesisis to address the scalability of sparse direct solvers based on multifrontal methods in parallelasynchronous environments.In the first part of this thesis, we focus on exploiting multi-threaded parallelism on sharedmemoryarchitectures. A variant of the Geist-Ng algorithm is introduced to handle both finegrain parallelism through the use of optimized sequential and multi-threaded BLAS libraries andcoarser grain parallelism through explicit OpenMP based parallelization. Memory aspects arethen considered to further improve performance on NUMA architectures: (i) on the one hand,we analyse the influence of memory locality and exploit adaptive memory allocation strategiesto manage private and shared workspaces; (ii) on the other hand, resource sharing on multicoreprocessors induces performance penalties when many cores are active (machine load effects) thatwe also consider. Finally, in order to avoid resources remaining idle when they have finishedtheir share of the work, and thus, to efficiently exploit all computational resources available, wepropose an algorithm wich is conceptually very close to the work-stealing approach and whichconsists in dynamically assigning idle cores to busy threads/activities.In the second part of this thesis, we target hybrid shared-distributed memory architectures,for which specific work to improve scalability is needed when processing large problems. We firststudy and optimize the dense linear algebra kernels used in distributed asynchronous multifrontalmethods. Simulation, experimentation and profiling have been performed to tune parameterscontrolling the algorithm, in correlation with problem size and computer architecture characteristics.To do so, right-looking and left-looking variants of the LU factorization with partialpivoting in our distributed context have been revisited. Furthermore, when computations are acceleratedwith multiple cores, the relative weight of communication with respect to computationis higher. We explain how to design mapping algorithms minimizing the communication betweennodes of the dependency tree of the multifrontal method, and show that collective asynchronouscommunications become critical on large numbers of processors. We explain why asynchronousbroadcasts using standard tree-based communication algorithms must be used. We then showthat, in a fully asynchronous multifrontal context where several such asynchronous communicationtrees coexist, new synchronization issues must be addressed. We analyse and characterizethe possible deadlock situations and formally establish simple global properties to handle deadlocks.Such properties partially force synchronization and may limit performance. Hence, wedefine properties which enable us to relax synchronization and thus improve performance. Ourapproach is based on the observation that, in our case, as long as memory is available, deadlockscannot occur and, consequently, we just need to keep enough memory to guarantee thata deadlock can always be avoided. Finally, we show that synchronizations can be relaxed in astate-of-the-art solver and illustrate the performance gains on large real problems in our fullyasynchronous multifrontal approach
39
Echevarria, Gavidia Vannessa Alexandra. "Centro de Día y Residencia para el Adulto Mayor en San Borja." Bachelor's thesis, Universidad Peruana de Ciencias Aplicadas (UPC), 2020. http://hdl.handle.net/10757/651602.
Full textAbstract:
El tema de mi tesis tiene como principal enfoque brindar calidad de vida al adulto mayor. Por ello, el tema que escogí es Centro de día y residencia para el adulto mayor, ya que este brindara la infraestructura y herramientas sociales para que el adulto mayor se pueda tener buena calidad de vida e insertarse en la comunidad.
La etapa de vida por la que está pasando un adulto mayor debe ser la más satisfactoria, ya que en su mayoría, son personas que se han pasado la vida criando a sus hijos y trabajando por lo cual es el momento para disfrutar de todos los logros, por eso mi proyecto busca darles un espacio físico donde puedan recibir la atención básica que necesitan en su día a día y darles una buena calidad de vida a través de actividades y espacios comunes.
En los últimos años la población adulto mayor a incrementando significativamente, proyectándose para el 2020 que el 20% de la población será mayor a 60 años (Inei, 2016). Habiendo dicho lo anterior podemos darnos cuenta que este es un problema real del que aún no hemos tomado la conciencia suficiente, ya que si bien se habla de lugares y programas específicos para el adulto mayor aún no hay infraestructura eficiente para ellos en los distritos de lima metropolitana, debido a ello el tema de mi tesis busca ayudar a adultos mayores e incentivar la vida activa y saludable de este publico.The theme of my thesis has as main focus to provide quality of life to the elderly, as in my opinion is a group of people who have not been taken seriously by society and are daily excluded from it. For this reason, the theme that I chose is the Day and Residence Center for the elderly, since it will provide the infrastructure and social tools so that the elderly can develop in their community and, most importantly, that they feel useful again and with a purpose. In recent years, the elderly population has increased significantly and this is increasing, projecting for 2020 that 20% of the population will be older than 60 years (Inei, 2016). Having said the above we can realize that this is a real problem that we have not yet taken sufficient consciousness, because although we talk about specific places and programs for the elderly there is still no efficient infrastructure for them in the districts of Lima metropolitan, because of this the theme of my thesis is transcendental since it will be able to help a group of older adults and encourage other districts to have a day and residence center to cover the needs that this public may have and give them a good quality of life.
Trabajo de suficiencia profesional
40
Davari, Mahdad. "Advances Towards Data-Race-Free Cache Coherence Through Data Classification." Doctoral thesis, Uppsala universitet, Avdelningen för datorteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-320595.
Full textAbstract:
Providing a consistent view of the shared memory based on precise and well-defined semantics—memory consistency model—has been an enabling factor in the widespread acceptance and commercial success of shared-memory architectures. Moreover, cache coherence protocols have been employed by the hardware to remove from the programmers the burden of dealing with the memory inconsistency that emerges in the presence of the private caches. The principle behind all such cache coherence protocols is to guarantee that consistent values are read from the private caches at all times. In its most stringent form, a cache coherence protocol eagerly enforces two invariants before each data modification: i) no other core has a copy of the data in its private caches, and ii) all other cores know where to receive the consistent data should they need the data later. Nevertheless, by partly transferring the responsibility for maintaining those invariants to the programmers, commercial multicores have adopted weaker memory consistency models, namely the Total Store Order (TSO), in order to optimize the performance for more common cases. Moreover, memory models with more relaxed invariants have been proposed based on the observation that more and more software is written in compliance with the Data-Race-Free (DRF) semantics. The semantics of DRF software can be leveraged by the hardware to infer when data in the private caches might be inconsistent. As a result, hardware ignores the inconsistent data and retrieves the consistent data from the shared memory. DRF semantics therefore removes from the hardware the burden of eagerly enforcing the strong consistency invariants before each data modification. Instead, consistency is guaranteed only when needed. This results in manifold optimizations, such as reducing the energy consumption and improving the performance and scalability. The efficiency of detecting and discarding the inconsistent data is an important factor affecting the efficiency of such coherence protocols. For instance, discarding the consistent data does not affect the correctness, but results in performance loss and increased energy consumption. In this thesis we show how data classification can be leveraged as an effective tool to simplify the cache coherence based on the DRF semantics. In particular, we introduce simple but efficient hardware-based private/shared data classification techniques that can be used to efficiently detect the inconsistent data, thus enabling low-overhead and scalable cache coherence solutions based on the DRF semantics.
41
Möller, Nathalie. "Adaptation de codes industriels de simulation en Calcul Haute Performance aux architectures modernes de supercalculateurs." Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLV088.
Full textAbstract:
Durant de longues années, la stabilité dans le paradigme d'architecture a facilité la portabilité de performance des grands codes en Calcul de Haute Performance d'une génération à l'autre de supercalculateurs.L'effondrement programmé de la loi de Moore - qui règle les progrès en gravure des micro-processeurs - bouscule ce modèle et requiert un effort nouveau du côté logiciel.Une modernisation des codes basée sur une algorithmique adaptée aux futurs systèmes est ainsi nécessaire.Cette modernisation repose sur des principes de base connus tels que la concurrence des calculs et la localité des données.Cependant, la mise en œuvre de ces principes dans le cadre d'applications réelles en milieu industriel – lesquelles applications sont souvent le fruit d’années d’efforts de développement - s’avère bien plus compliquée que ne le laissait prévoir leur simplicité apparente.Les contributions de cette thèse sont les suivantes :D’une part, nous explorons une méthodologie de modernisation de codes basée sur l’utilisation de proto-applications et la confrontons à une approche directe, en optimisant deux codes de simulation dévéloppés dans un contexte similaire.D’autre part, nous nous concentrons sur l’identification des principaux défis concernant l’adéquation entre applications, modèles de programmation et architectures.Les deux domaines d'application choisis sont la dynamique des fluides et l'électromagnétismeFor many years, the stability of the architecture paradigm has facilitated the performance portability of large HPC codes from one generation of supercomputers to another.The announced breakdown of the Moore's Law, which rules the progress of microprocessor engraving, ends this model and requires new efforts on the software's side.Code modernization, based on an algorithmic which is well adapted to the future systems, is mandatory.This modernization is based on well-known principles as the computation concurrency, or degree of parallelism, and the data locality.However, the implementation of these principles in large industrial applications, which often are the result of years of development efforts, turns out to be way more difficult than expected.This thesis contributions are twofold :On the one hand, we explore a methodology of software modernization based on the concept of proto-applications and compare it with the direct approach, while optimizing two simulation codes developed in a similar context.On the other hand, we focus on the identification of the main challenges for the architecture, the programming models and the applications.The two chosen application fields are the Computational Fluid Dynamics and Computational Electro Magnetics
42
Mama, Awal Halimatou. "La métropole-village(s) de Ouagadougou : explorer les potentiels d'un territoire, supports de processus de projet architectural." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAH005/document.
Full textAbstract:
La ville africaine s'étale et intègre les villages environnants en devenant métropole. Que ce soit le mouvement des ruraux vers les villes ou bien de la ville vers la campagne, ces phénomènes inquiètent les spécialistes. La pensée traditionnelle du monde qui opposait ville-campagne, ville-village, ville-brousse, n'est plus d'actualité. Les réalités du territoire sont devenues autres. Quels sont les outils qui nous permettent de lire ces nouvelles réalités? Comment opérer ce changement de «lunettes» que nous propose Bernardo Secchi pour lire et écrire la «ville contemporaine»?Pour nos recherches, nous considérons Ouagadougou comme un véritable observatoire. L'objectif est d'apprendre des lieux d'initiatives où se construisent de nouveaux modes de vie dans des dynamiques imprévues. Aujourd'hui, la capitale burkinabé est caractérisée par une double identité foncière. Une organisation foncière publique importée de la pensée coloniale dite « lotie », et une organisation foncière informelle issue de la culture villageoise dite « non-lotie ». À force de coexistence, le développement de métropole n'a t-il pas engendré d'autres phénomènes, avec des degrés et des intensités variés de planification et de spontanéité? La rencontre des deux modes opératoires ne définit pas un rapport dual, mais un intervalle. Dans ce contexte, le « village » entendu dans sa dimension sociale et communautaire devient, en milieu urbain, générateur d'espaces communs. Les structures communautaires testent les possibles et inventent la métropole au quotidien : elles rendent flexible toute forme de planification. Ainsi, nous formulons l'hypothèse que l'étude de la « Métropole-village(s)» de Ouagadougou peut amener à de nouvelles connaissances permettant la création d'outils de compréhension des territoires urbanisés contemporainsThe African city spreads and incorporates the surrounding villages becoming metropolis. Whether the migration from rural to urban or from the city to the countryside, these phenomena became a concern for specialists. Traditional thinking of the world that opposed city-countryside, city-village, city-bush, is no longer valid. Territory's realities became different. What are the tools that allow us to read these new realities? How can we proceed to a change of "glasses" that Bernardo Secchi is proposing, in order to read and write the " contemporary city "?For our research, we consider Ouagadougou as a true observatory. The objective is to learning places of initiatives which build new lifestyles in unexpected dynamics. Today, the capital of Burkina Faso is characterized by a dual identity of the land. Public land organization imported from the colonial thinking called " lotie " (subdivided area) and an informal tenure arrangements after the village culture called “non-lotie” (non-subdivided area). To force to coexistence, hasn't the metropolis generated new phenomena, with different degrees and intensities of planification and spontaneity? The meeting of the two procedures does not define a dual report, but an interval. In this context, the "village" understood in its social and community dimension becomes an urban environment generating shared spaces. Communal structures are questioning what is possible and redefine what a metropolis is every day: they make flexible any form of planning. Thus, we hypothesize that the study of "City-village(s)” of Ouagadougou may lead to new knowledge to the creation of tools for understanding contemporary urbanized territories
43
Mohamood, Fayez. "DLL-Conscious Instruction Fetch Optimization for SMT Processors." Thesis, Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10560.
Full textAbstract:
Simultaneous multithreading (SMT) processors can issue multiple instructions from distinct processes or threads in the same cycle. This technique effectively increases the overall throughput by keeping the pipeline resources more occupied at the potential expense of reducing single thread performance due to resource sharing. In the software domain, an increasing number of Dynamically Linked Libraries (DLL) are used by applications and
operating systems, providing better flexibility and modularity, and enabling code sharing. It is observed that a significant amount of execution time in software today is spent in executing standard DLL instructions, that are shared among multiple threads or processes. However, for an SMT processor with a virtually-indexed based cache implementation, existing instruction fetching mechanisms can induce unnecessary false cache misses caused by the DLL-based instructions, which were intended to be shared. This problem is more conspicuous when multiple independent threads are executing concurrently in an SMT processor.
This work investigates an often-neglected form of contention between running threads in the I-TLB and I-cache caused by DLLs. To address these shortcomings, we propose a system level technique involving a light-weight modification in the microarchitecture and the OS. By exploiting the nature of the DLLs in our new
architecture, we are able to reinstate physical sharing of the DLLs in an SMT machine. Using Microsoft Windows based applications, our
simulation results show that the optimized instruction fetching mechanism can reduce the number of DLL misses up to 5.5 times and
improve the instruction cache hit rates by up to 62%, resulting in upto 30% DLL IPC improvements and upto 15% overall IPC improvements.
44
Lee, Jaekyu. "Shared resource management for efficient heterogeneous computing." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50217.
Full textAbstract:
The demand for heterogeneous computing, because of its performance and energy efficiency, has made on-chip heterogeneous chip multi-processors (HCMP) become the mainstream computing platform, as the recent trend shows in a wide spectrum of platforms from smartphone application processors to desktop and low-end server processors. The performance of on-chip GPUs is not yet comparable to that of discrete GPU cards, but vendors have integrated more powerful GPUs and this trend will continue in upcoming processors.
In this architecture, several system resources are shared between CPUs and GPUs. The sharing of system resources enables easier and cheaper data transfer between CPUs and GPUs, but it also causes resource contention problems between cores. The resource sharing problem has existed since the homogeneous (CPU-only) chip-multi processor (CMP) was introduced. However, resource sharing in HCMPs shows different aspects because of the different nature of CPU and GPU cores. In order to solve the resource sharing problem in HCMPs, we consider efficient shared resource management schemes, in particular tackling the problem in shared last-level cache and interconnection network.
In the thesis, we propose four resource sharing mechanisms:
First, we propose an efficient cache sharing mechanism that exploits the different characteristics of CPU and GPU cores to effectively share cache space between them. Second, adaptive virtual channel partitioning for on-chip interconnection network is proposed to isolate inter-application interference. By partitioning virtual channels to CPUs and GPUs, we can prevent the interference problem while guaranteeing quality-of-service (QoS) for both cores. Third, we propose a dynamic frequency controlling mechanism to efficiently share system resources. When both cores are active, the degree of resource contention as well as the system throughput will be affected by the operating frequency of CPUs and GPUs. The proposed mechanism tries to find optimal operating frequencies for both cores, which reduces the resource contention while improving system throughput. Finally, we propose a second cache sharing mechanism that exploits GPU-semantic information. The programming and execution models of GPUs are more strict and easier than those of CPUs. Also, programmers are asked to provide more information to the hardware. By exploiting these characteristics, GPUs can energy-efficiently exercise the cache and simpler, but more efficient cache partitioning can be enabled for HCMPs.
45
Wen, Hao. "IMPROVING PERFORMANCE AND ENERGY EFFICIENCY FOR THE INTEGRATED CPU-GPU HETEROGENEOUS SYSTEMS." VCU Scholars Compass, 2018. https://scholarscompass.vcu.edu/etd/5664.
Full textAbstract:
Current heterogeneous CPU-GPU architectures integrate general purpose CPUs and highly thread-level parallelized GPUs (Graphic Processing Units) in the same die. This dissertation focuses on improving the energy efficiency and performance for the heterogeneous CPU-GPU system.
Leakage energy has become an increasingly large fraction of total energy consumption, making it important to reduce leakage energy for improving the overall energy efficiency. Cache occupies a large on-chip area, which are good targets for leakage energy reduction. For the CPU cache, we study how to reduce the cache leakage energy efficiently in a hybrid SPM (Scratch-Pad Memory) and cache architecture. For the GPU cache, the access pattern of GPU cache is different from the CPU, which usually has little locality and high miss rate. In addition, GPU can hide memory latency more effectively due to multi-threading. Because of the above reasons, we find it is possible to place the cache lines of the GPU data caches into the low power mode more aggressively than traditional leakage management for CPU caches, which can reduce more leakage energy without significant performance degradation.
The contention in shared resources between CPU and GPU, such as the last level cache (LLC), interconnection network and DRAM, may degrade both CPU and GPU performance. We propose a simple yet effective method based on probability to control the LLC replacement policy for reducing the CPU’s inter-core conflict misses caused by GPU without significantly impacting GPU performance. In addition, we develop two strategies to combine the probability based method for the LLC and an existing technique called virtual channel partition (VCP) for the interconnection network to further improve the CPU performance.
For a specific graph application of Breadth first search (BFS), which is a basis for graph search and a core building block for many higher-level graph analysis applications, it is a typical example of parallel computation that is inefficient on GPU architectures. In a graph, a small portion of nodes may have a large number of neighbors, which leads to irregular tasks on GPUs. These irregularities limit the parallelism of BFS executing on GPUs. Unlike the previous works focusing on fine-grained task management to address the irregularity, we propose Virtual-BFS (VBFS) to virtually change the graph itself. By adding virtual vertices, the high-degree nodes in the graph are divided into groups that have an equal number of neighbors, which increases the parallelism such that more GPU threads can work concurrently. This approach ensures correctness and can significantly improve both the performance and energy efficiency on GPUs.
46
Radovic, Zoran. "Software Techniques for Distributed Shared Memory." Doctoral thesis, Uppsala University, Department of Information Technology, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-6058.
Full textAbstract:
In large multiprocessors, the access to shared memory is often nonuniform, and may vary as much as ten times for some distributed shared-memory architectures (DSMs). This dissertation identifies another important nonuniform property of DSM systems: nonuniform communication architecture, NUCA. High-end hardware-coherent machines built from large nodes, or from chip multiprocessors, are typical NUCA systems, since they have a lower penalty for reading recently written data from a neighbor's cache than from a remote cache. This dissertation identifies node affinity as an important property for scalable general-purpose locks. Several software-based hierarchical lock implementations exploiting NUCAs are presented and evaluated. NUCA-aware locks are shown to be almost twice as efficient for contended critical sections compared to traditional lock implementations.
The shared-memory “illusion”' provided by some large DSM systems may be implemented using either hardware, software or a combination thereof. A software-based implementation can enable cheap cluster hardware to be used, but typically suffers from poor and unpredictable performance characteristics.
This dissertation advocates a new software-hardware trade-off design point based on a new combination of techniques. The two low-level techniques, fine-grain deterministic coherence and synchronous protocol execution, as well as profile-guided protocol flexibility, are evaluated in isolation as well as in a combined setting using all-software implementations. Finally, a minimum of hardware trap support is suggested to further improve the performance of coherence protocols across cluster nodes. It is shown that all these techniques combined could result in a fairly stable performance on par with hardware-based coherence.
47
Gonzalez-Rubio, Sandoval Rubén. "Propositions d'architectures pour les traitements symboliques." Paris 6, 1987. http://www.theses.fr/1987PA066402.
Full textAbstract:
Developpement d'un ensemble de propositions concernant l'architecture des ordinateurs. Les propositions et realisations presentees sont: schuss, un accelerateur materiel pour l'acces aux bases de donnees; ddc, une machine parallele a inferences
48
Atohoun, Béthel Christian A. R. K. "Architecture logique d'un système multi agents de suivi multi caméra distribué : exploitation du modèle de croyance transférable." Thesis, Littoral, 2013. http://www.theses.fr/2013DUNK0373/document.
Full textAbstract:
Cette thèse présente l'utilisation conjointe de la théorie de l'évidente et du suivi multi-hypothèses pour la modélisation et la gestion d'un système de suivi multi-caméras dans un environnement autoroutier. Le suivi est basé sur la ré-identification des objets (véhicules) sur la base d'information visio-temporelles. Une concrétisation de ces concepts se traduit par la conception et la mise en oeuvre d'une architecture logicielle multi-agents de gestion du suivi multi-caméras. Après une présentation de l'état de l'art sur les cadres de gestion de l'incertain et celui relatif à fusion de l'information pour la mise en correspondance, et sur les systèmes multi-agents, notre apport dans ce travail se situe à trois niveaux. Le premier a été une adaptation de la phase de décision du modèle de croyance transférable pour y intégrer l'utilisation du suivi multi-hypothèses comme outil de levée d'ambigüité rn cas d'indécision face à une situation de mise en correspondance. Le second apport a été celui de proposer une architecture logicielle à base d'agents pour la gestion du système du suivi multi-caméras. Nous en avons proposé la modélisation globale ainsi que celle des agents et de leurs interactions en utilisant une démarche personnelle d'analyse mais toutefois inspirée de langages et outils de modélisation tels que Agent UML et MaSE pour ne citer que ceux-là, du fait qu'il n'existe pas réellement un standard normalisé à ce jour dans ce domaine. Notre troisième apport a été de faire un début d'implémentation de notre architecture logicielle à base d'agent en nous basant sur la plateforme JADE (Java Agent DEvelopment Framework). Quelques expérimentations et discussions des résultats sont présentées à la fin pour déboucher sur nos conclusions et perspectivesThis thesis presents the joint use of the theory of evidence and multiple hypothesis tracking for modeling and managing a system for monitoring multiple cameras in a motorway. The tracking is based on the re-identification of objects (vehicles) on the basis of visuals and times informations. A realization of these concepts results in the design and implementation of a software architecture for multiple agents management of multiple camera tracking system. After presenting the state of the art on the frameworks of uncertainty management and that on information fusion for the matching, and the multi-agent systems, our contribution in this work is on two or three levels. The first was an adaptation of the decision phase of the transferable belief model to incorporate the use of multi-hypotheses tracking as a tool of ambiguity survey in case of indecision in matching situation. The second contribution was a proposition of agent-based software architecture for management of a multiple cameras tracking system. We have proposed the global system modeling as well as agents and their interactions modeling using a personal analysis method but nevertheless inspired by modelisation languages and tolls such as Agent UML, MaSE and others, because there is not yet a standard and normalized tool on the subject. Our third contribution was to begin an implementation of our agent-based software architecture using JADE (Java Agent Development Framework). Some experiment and discussions are presented at the end to lead to our conclusions and perspectives
49
Díaz, Sedano Carlos Alfredo. "Colegio inicial, primaria y secundaria en la provincia de Satipo-Junín enfocado en espacios compartidos y comunitarios." Bachelor's thesis, Universidad Peruana de Ciencias Aplicadas (UPC), 2020. http://hdl.handle.net/10757/652949.
Full textAbstract:
Se plantea diseñar un colegio público en el distrito de Satipo, en donde la interacción del colegio con la comunidad se manifieste de manera fluida y flexible. El proyecto busca brindar espacios de aprendizaje fuera y dentro de aulas proponiendo espacios compartidos en las aulas, y en áreas de esparcimiento; así como vincular las actividades del colegio con el desarrollo de las comunidades nativas cercanas. Para esto, se analiza y considera los factores del lugar y clima que influyen en el diseño del colegio para proporcionar confort al usuario.
El proyecto busca contemplar las necesidades de la comunidad locales proponiendo talleres por medio de los centros técnicos de producción (cetpro) que beneficiarían a los estudiantes al culminar los estudios; así como, la implementación de áreas recreativas y espacios abiertos para la comunidad.It is proposed to design a public school in the district of Satipo, where the interaction of the school with the community is manifested in a fluid and flexible way. The project seeks to provide learning spaces outside and within classrooms by proposing in between spaces in the classrooms, and in recreation areas; as well as linking the activities of the school with the development of nearby native communities. In addition, it analyzes and considers the factors of the place and climate that influence the design to provide comfort to the user. The project seeks to contemplate the needs of the local community by proposing workshops through the technical production centers that would benefit students at the end of their studies; as well as the implementation of recreational areas and open spaces for the community.
Tesis
50
Jacobsen, Erica Dawn. "Forced Vibration Testing and Analysis of Pre- and Post- Retrofit Buildings." DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/531.
Full textAbstract:
ABSTRACT
Forced Vibration Testing and Analysis of Pre- and Post- Retrofit Buildings
Erica Dawn Jacobsen
The primary goal of the thesis was to detect the retrofit through vibration testing of both buildings. The secondary goal focused on correctly identifying the behavior of the building through FVT, comparing that behavior to computational model predictions, and determining the necessary level of detail to include in the computational modeling. Forced vibration testing (FVT) of two stiff-wall/flexible-diaphragm buildings yielded natural frequencies and mode shapes for the two buildings. The buildings were nearly identical with the exception that one had been retrofitted. Both buildings were comprised of concrete shearwalls and steel moment frames in the north/south direction and moment frames in the east/west direction. The retrofit strengthened the moment connections and added braces to the perimeter walls in the east/west direction.
The natural frequencies were found through FVT by setting a 30-lb shaker on the roof of both buildings and sweeping through a range of frequencies in both the east/west and north/south directions. Accelerometers were placed on the building to detect the accelerations. The peaks on the Fast Fourier Transform (FFT) graphs indicated the frequencies at which the structure resonated. Mode shapes were tested for by placing the shaker in a position ideal for exciting the mode and setting the shaker to the natural frequency detected from the FFT graphs. The accelerometers were placed around the roof of the building to record the mode shape.
After testing, computational models were created to determine if the models could accurately predict the frequencies and mode shapes of the buildings as well as the effect of the retrofit. A series of increasingly complex computational models, ranging from hand calculations to 3D models, were created to determine the level of detail necessary to predict the building behavior. Natural frequencies were the primary criteria used to determine whether the model accurately predicted the building behavior. The mid-diaphragm deflection and base shear from spectral analysis were the final criteria used to compare these select models.
It was determined that in order to properly capture the modal behavior of the building, the sawtooth framing, major beams, and the lateral-force-resisting-system (LFRS) must be modeled. Though the mode shape of the building is dominated by the flexible diaphragm, the LFRS is necessary to model to accurately predict both the natural frequency of the building as well as the diaphragm deflection.