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Relevant bibliographies by topics / Shallow trench isolation

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Academic literature on the topic 'Shallow trench isolation'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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Journal articles on the topic "Shallow trench isolation"

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Sang, Sheng Bo, Chen Yang Xue, Wen Dong Zahng, and Ji Jun Xiong. "Raman Investigation of Stress for Shallow Trench." Defect and Diffusion Forum 265 (May 2007): 1–6. http://dx.doi.org/10.4028/www.scientific.net/ddf.265.1.

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A trench is used as a storage capacitor in dynamic memory (DRAM) technologies (deep storage trenches), or as an isolation structure in CMOS, bipolar and BiCMOS technologies. But a shallow trench structure has also been shown to be a major factor in substrate defect generation during processing. Such defect generation is directly related to mechanical stresses existing around the trench. This stress can be monitored, using Raman spectroscopy, to a stress resolution of 10MPa and a spatial resolution of 0.2μm. In this paper, a trench structure is designed and fabricated, and the test results for local stresses within the trench are shown to be in good correspondence with theory.

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Cheng, Juing-Yi, Tan Fu Lei, and Tien Sheng Chao. "A Novel Shallow Trench Isolation Technique." Japanese Journal of Applied Physics 36, Part 1, No. 3B (1997): 1319–24. http://dx.doi.org/10.1143/jjap.36.1319.

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Gupta, Aakashdeep, K. Nidhin, Suresh Balanethiram, et al. "Static Thermal Coupling Factors in Multi-Finger Bipolar Transistors: Part I—Model Development." Electronics 9, no. 9 (2020): 1333. http://dx.doi.org/10.3390/electronics9091333.

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In this part, we propose a step-by-step strategy to model the static thermal coupling factors between the fingers in a silicon based multifinger bipolar transistor structure. First we provide a physics-based formulation to find out the coupling factors in a multifinger structure having no-trench isolation (cij,nt). As a second step, using the value of cij,nt, we propose a formulation to estimate the coupling factor in a multifinger structure having only shallow trench isolations (cij,st). Finally, the coupling factor model for a deep and shallow trench isolated multifinger device (cij,dt) is presented. The proposed modeling technique takes as inputs the dimensions of emitter fingers, shallow and deep trench isolations, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are validated against 3D TCAD simulations of multifinger bipolar transistors with and without trench isolations. Geometry scalability of the model is also demonstrated.

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Boning, Duane, and Brian Lee. "Nanotopography Issues in Shallow Trench Isolation CMP." MRS Bulletin 27, no. 10 (2002): 761–65. http://dx.doi.org/10.1557/mrs2002.246.

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AbstractAs advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important concern in shallow trench isolation (STI) on wafers polished by means of chemical–mechanical planarization (CMP). Previous work has shown that nanotopography—small surface-height variations of 10–100 nm in amplitude extending across millimeter-scale lateral distances on virgin wafers—can result in CMP-induced localized thinning of surface films such as the oxides or nitrides used in STI. A contact-wear CMP model can be employed to produce maps of regions on a given starting wafer that are prone to particular STI failures, such as the lack of complete clearing of the oxide in low spots and excessive erosion of nitride layers in high spots on the wafer. Stiffer CMP pads result in increased nitride thinning. A chip-scale pattern-dependent CMP simulation shows that substantial additional dishing and erosion occur because of the overpolishing time required due to nanotopography. Projections indicate that nanotopography height specifications will likely need to decrease in order to scale with smaller feature sizes in future IC technologies.

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Brady, F. T., J. D. Maimon, and M. J. Hurt. "A scaleable, radiation hardened shallow trench isolation." IEEE Transactions on Nuclear Science 46, no. 6 (1999): 1836–40. http://dx.doi.org/10.1109/23.819162.

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Srinivasan, Ramanathan, Pradeep VR Dandu, and S. V. Babu. "Shallow Trench Isolation Chemical Mechanical Planarization: A Review." ECS Journal of Solid State Science and Technology 4, no. 11 (2015): P5029—P5039. http://dx.doi.org/10.1149/2.0071511jss.

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Itoh, Akio, Masahiko Imai, and Yoshihiro Arimoto. "Photoresist Chemical Mechanical Polishing for Shallow Trench Isolation." Japanese Journal of Applied Physics 37, Part 1, No. 4A (1998): 1697–700. http://dx.doi.org/10.1143/jjap.37.1697.

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Hong, Sug Hun, Dong Ho Ahn, Moon Han Park, and Ho Kyu Kang. "A Novel T-Shaped Shallow Trench Isolation Technology." Japanese Journal of Applied Physics 40, Part 1, No. 4B (2001): 2616–20. http://dx.doi.org/10.1143/jjap.40.2616.

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Belyansky, M., N. Klymko, R. Conti, D. Chidambarrao, and F. Liu. "Study of silicon strain in shallow trench isolation." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 28, no. 4 (2010): 829–33. http://dx.doi.org/10.1116/1.3427660.

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Chen, Coming, Chun-Yen Chang, Jih-Wen Chou, Water Lur, and Shih-Wei Sun. "Shallow-Trench Isolation With Raised-Field-Oxide Structure." Japanese Journal of Applied Physics 39, Part 1, No. 3A (2000): 1080–84. http://dx.doi.org/10.1143/jjap.39.1080.

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Dissertations / Theses on the topic "Shallow trench isolation"

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Lee, Brian 1975. "Modeling of chemical mechanical polishing for shallow trench isolation." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/29907.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.<br>Includes bibliographical references (p. 195-201).<br>This thesis presents the nonlinear analysis, design, fabrication, and testing of an axial-gap magnetic induction micro machine, which is a two-phase planar motor in which the rotor is suspended above the stator via mechanical springs, or tethers. The micro motor is fabricated from thick layers of electroplated NiFe and copper, by our collaborators at Georgia Institute of Technology. The rotor and the stator cores are 4 mm in diameter each, and the entire motor is about 2 mm thick. During fabrication, SU-8 epoxy is used as a structural mold material for the electroplated cores. The tethers are designed to be compliant in the azimuthal direction, while preventing axial deflections and maintaining a constant air gap. This enables accurate measurements of deflections within the rotor plane via a computer microvision system. The small scale of the magnetic induction micro machine, in conjunction with the good thermal contact between its electroplated stator layers, ensures an isothermal device which can be cooled very effectively. Current densities over 109 A/m2 simultaneously through each phase is repeatedly achieved during experiments; this density is over two orders of magnitude larger than what can be achieved in conventional macro-scale machines.<br>(cont.) More than 5 Nm of torque is obtained for an air gap of about 5 zm, making this micro motor the highest torque density micro-scale magnetic machine to date. About 0.3 buNm for the large air gap of 70 m is also achieved in systematic tests that reveal the influence of strong eddy-currents and associated nonlinear saturation within the micro motor Eddy-current effects are modeled using a finite-difference vector potential formulation. Its results demonstrate the presence of flux crowding on the stator surface, which leads to heavy saturation. To capture saturation effects, a fully nonlinear finite-difference time-domain simulation is developed to solve Maxwell's Equations within the computational space of the micro machine. To mitigate the inherent stiffness in the partial differential equations, the speed of light is artificially reduced by five orders of magnitude, taking special care that assumptions of magnetoquasistatic behavior are still met. The results from this model are in very good agreement with experimental data from the tethered magnetic induction micro motor.<br>by Brian Lee.<br>Ph.D.

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Gan, Terence (Terence Chihkiong) 1975. "Modeling of chemical mechanical polishing for shallow trench isolation." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86469.

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Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.<br>Includes bibliographical references (p. 75-77).<br>by Terence Gan.<br>S.B.and M.Eng.

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Garud, Niharika Triplett Gregory Edward. "Shallow trench isolation process in microfabrication for flash (NAND) memory." Diss., Columbia, Mo. : University of Missouri-Columbia, 2008. http://hdl.handle.net/10355/5622.

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Thesis (M.S.)--University of Missouri-Columbia, 2008.<br>The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on September 2, 2008) Includes bibliographical references.

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Finkelstein, Hod. "Shallow-trench-isolation bounded single-photon avalanche diodes in commercial deep submicron CMOS technologies." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3274523.

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Thesis (Ph. D.)--University of California, San Diego, 2007.<br>Title from first page of PDF file (viewed October 3, 2007). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 256-271).

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Hsu, Mark J. "Development of shallow trench isolation bounded single-photon avalanche detectors for acousto-optic signal enhancement and frequency up-conversion." Diss., [La Jolla] : University of California, San Diego, 2010. http://wwwlib.umi.com/cr/ucsd/fullcit?p3407959.

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Thesis (Ph. D.)--University of California, San Diego, 2010.<br>Title from first page of PDF file (viewed June 17, 2010). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (leaves 172-191).

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Forsberg, Markus. "Chemical Mechanical Polishing of Silicon and Silicon Dioxide in Front End Processing." Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-4304.

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Dobri, Adam. "Mémoires embarquées non volatiles à grille flottante : challenges technologiques et physiques pour l’augmentation des performances vers le noeud 28nm." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT030/document.

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Les mémoires flash sont intégrées dans presque tous les aspects de la vie moderne car leurs uns et zéros représentent les données stockées sur les cartes à puce et dans les capteurs qui nous entourent. Dans les mémoires flash à grille flottante ces données sont représentées par la quantité de charge stockée sur une grille en poly-Si, isolée par un oxyde tunnel et un diélectrique entre grilles (IGD). Au fur et à mesure que les chercheurs et les ingénieurs de l'industrie microélectronique poussent continuellement les limites de mise à l'échelle, la capacité des dispositifs à contenir leurs informations risque de devenir compromise. Même la perte d'un électron par jour est trop élevée et entraînerait l'absence de conservation des données pendant dix ans. Étant trop faibles, les courants de fuite sont impossible à mesurer directement. Cette thèse présente une nouvelle méthode, la séparation du stress aux oxydes (OSS), pour mesurer ces courants en suivant les changements de la tension de seuil de la cellule flash. La nouveauté de la technique est que les conditions de polarisation sont sélectionnées afin que le stress se produise entièrement dans l'IGD, permettant la reconstruction d'une courbe IV de l'IGD à des tensions faibles. Cette thèse décrit également les changements de processus nécessaires pour intégrer la première mémoire flash embarquée de 40 nm basée sur un IGD d'alumine, en remplacement du SiO2/ Si3N4/SiO2 standard. L'intérêt pour les matériaux high-k vient de la motivation de créer un IGD qui est électriquement mince pour augmenter le couplage tout en étant physiquement épais pour bloquer le transport de charge. Comme la flash intégrée au noeud de 40 nm se rapproche de la production, l'approche à prendre dans les nœuds futurs doit également être discutée. Cela fournit la motivation pour le chapitre final de la thèse qui traite de la co-intégration des différents IGD avec des dispositifs logiques ayant les gilles « high-k metal » nécessaires à 28 nm et au-delà<br>Flash memory circuits are embedded in almost every aspect of modern life as their ones and zeros represent the data that is stored on smart cards and in the sensors around us. In floating gate flash memories this data is represented by the amount of charge stored on a poly-Si gate, isolated by a tunneling oxide and an Inter Gate Dielectric (IGD). As the microelectronics industry’s researchers and engineering continuously push the scaling limits, the ability of the devices to hold their information may become compromised. Even the loss of one electron per day is too much and would result in the failure to retain the data for ten years. At such low current densities, the direct measurement of the leakage current is impossible. This thesis presents a new way, Oxide Stress Separation, to measure these currents by following the changes in the threshold voltage of the flash cell. The novelty of the technique is that the biasing conditions are selected such that the stress occurs entirely in the IGD, allowing for the reconstruction of an IV curve of the IGD at low biases. This thesis also describes the process changes necessary to integrate the world’s first 40 nm embedded flash based on an alumina IGD, in replacement of the standard SiO2/Si3N4/SiO2. The interest in high-k materials comes from the motivation to make an IGD that is electrically thin to increase coupling while being physically thick to block charge transport. As embedded flash at the 40 nm node nears production, the approach to be taken in future nodes must also be discussed. This provides the motivation for the final chapter of the thesis which discusses the co-integration of the different IGDs with logic devices having the high-k metal gates necessary at 28 nm and beyond

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Tavernier, Aurélien. "Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées." Phd thesis, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-00987019.

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Réalisées au début du processus de fabrication des circuits intégrés, les tranchées d'isolation permettent d'éviter les fuites de courant latérales qui pourraient avoir lieu entre les transistors. Les tranchées sont remplies par un film d'oxyde de silicium réalisé par des procédés de dépôt chimiques en phase vapeur (aussi appelés CVD). Le remplissage des tranchées est couramment réalisé par un procédé CVD à pression sub-atmosphérique (SACVD TEOS/O3). Cependant, la capacité de remplissage de ce procédé pour les nœuds technologiques CMOS 28 nm et inférieurs est dégradée à cause de profils trop verticaux dans les tranchées. Cela induit la formation de cavités dans l'oxyde et entraine des courts-circuits. Afin de pallier ce problème, une nouvelle stratégie de remplissage en trois étapes est proposée pour la technologie CMOS 14 nm. Dans la première étape, un film mince d'oxyde est déposé dans les tranchées. Puis, dans la deuxième étape, les flancs du film sont gravés à l'aide d'un procédé de gravure innovant, basé sur un plasma délocalisé de NF3/NH3, permettant de créer une pente favorable au remplissage final réalisé au cours de la troisième étape. Le développement de cette nouvelle stratégie de remplissage s'est déroulé selon plusieurs axes. Tout d'abord, le procédé de dépôt a été caractérisé afin de sélectionner les conditions optimales pour la première étape de la stratégie. Puis, le procédé de gravure innovant a été caractérisé en détail. L'influence des paramètres de gravure a été étudiée sur pleine plaque et sur plaques avec motifs afin de comprendre les mécanismes de gravure et de changement de pente dans les tranchées. Enfin, dans un troisième temps, la stratégie de remplissage a été développée et intégrée pour la technologie CMOS 14 nm. Nous montrons ainsi qu'il est possible de contrôler le changement de pente avec les conditions de gravure et que cette stratégie permet un remplissage des tranchées d'isolation sans cavités.

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吳明昆. "Oxide Etch in Shallow Trench Isolation." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/55852764983108910898.

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碩士<br>國立交通大學<br>工學院碩士在職專班半導體材料與製程設備學<br>94<br>Due to photo resist is widely used in pattern definition with semiconductor process, we need photo resist to protect active region when silicon dioxide inside the shallow trench isolation etch .The thesis studies the high selectivity in oxide over nitride with different process parameters split. The hard mask layer will use silicon nitride instead of resist material. The concept of mask less will diminish process flow and production cost. To increase the etch selectivity for silicon dioxide inside shallow trench isolation to silicon nitride in active region, the parameters of etch will be properly used and adjusted in the experiment. The key factors are process gas ratio and pressure. To fine tune the gas ratio of CHF3 to CF4 with low pressure condition, it will get the highest etch selectivity when the gas ratio value is 4.The monitor wafers will be used to check remain nitride and oxide loss. From the SEM image, we find the silicon nitride in active region will over 9.2nm and silicon dioxide loss in shallow trench isolation is near 180 nm. No mask used in the experiment is available.

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Heo, Kuenchy, and 何昆奇. "Shallow Trench Isolation(STI) for Sub-micron MOSFET." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/57092779924475988215.

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碩士<br>長庚大學<br>電機工程研究所<br>87<br>In the experiments, the sub-threshold Id hump and inverse narrow width effect were observed above 50nm pad oxide removal(POR). The off current also elevated by increasing the removal of pad oxide. In the extraction of the characteristics of the corner MOSFET, we empirically found the channel threshold voltage(vtsch) was determined at a current of 1.1μA*Wdes/Ldes and the corner threshold voltage(vtscor) was at a current of 26 nA/Ldes. we demonstrated the degradation depend on the pad oxide removal and the 100nm removal of pad oxide has more large degradation than the others in the narrow channel devices. To understand the above results in detail, we measured the impact-ionization rate (α≡Ib/Id) and found that the impact-ionization rate had increased rapidly for the narrow devices with a large dip STI structure during the stress.

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Book chapters on the topic "Shallow trench isolation"

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Kim, Nam Hoon, Hae Young Yoo, and Eui Goo Chang. "Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory." In Solid State Phenomena. Trans Tech Publications Ltd., 2007. http://dx.doi.org/10.4028/3-908451-31-0.29.

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Zwicker, G., P. Lange, P. Staudt-Fischbach, and W. Windbracke. "Field Isolation Using Shallow Trenches for Submicron CMOS Technology." In ESSDERC ’89. Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-52314-4_29.

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Chang, C. P. "Shallow Trench Isolation." In Encyclopedia of Materials: Science and Technology. Elsevier, 2001. http://dx.doi.org/10.1016/b0-08-043152-6/01508-4.

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Paik, Ungyu, and Jea-Gun Park. "Shallow Trench Isolation CMP." In Nanoparticle Engineering for Chemical-Mechanical Planarization. CRC Press, 2019. http://dx.doi.org/10.1201/9780429291890-3.

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"Shallow Trench Isolation CMP." In Nanoparticle Engineering for Chemical-Mechanical Planarization. CRC Press, 2009. http://dx.doi.org/10.1201/9781420059137.ch3.

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Yanda, Richard F., Michael Heynes, and Anne K. Miller. "Isolate Active Areas (Shallow Trench Isolation)." In Demystifying Chipmaking. Elsevier, 2005. http://dx.doi.org/10.1016/b978-075067760-8/50007-5.

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Stuer, C., A. Steegen, J. Van Landuyt, H. Bender, and K. Maex. "Characterisation of the local stress induced by shallow trench isolation and CoSi2 silicidation." In Microscopy of Semiconducting Materials 2001. CRC Press, 2018. http://dx.doi.org/10.1201/9781351074629-103.

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Morgan, Kevin, Terry Marsden, and Jonathan Murdoch. "Beyond the Placeless Foodscape: Place, Power, and Provenance." In Worlds of Food. Oxford University Press, 2006. http://dx.doi.org/10.1093/oso/9780199271580.003.0015.

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The foregoing chapters bring us to the point where we can directly address the three themes that constitute the subtitle of the book—namely place, power, and provenance. Reflecting the binary thinking that pervades the agri-food literature—global versus local, embedded versus disembedded, conventional versus alternative, quantity versus quality, and so forth— these themes tend to be treated in a highly compartimentalized fashion, with place and provenance being the preserve of the alternative food literature, while power seems to be the proper object of analysis in the conventional food literature. This binary conceptual tradition has the effect of segmenting the food sector into unduly rigid and path-dependent worlds of production. It could even lead to the (erroneous) conclusion that the conventional food chain is inextricably tied to a particular world of production, invariably the Industrial World, while alternative food chains are embedded in, and tethered to, the Interpersonal World. To overcome this unwarranted division of labour, we propose to examine the roles of place, provenance, and power in both the conventional food chain and the ecological food chain. However, we also want to suggest that the borders between these worlds are more porous and much less static than the worlds of production literature sometimes implies, leaving open the possibility that firms and regions can move from one world to another. Each world of production may have its own nuanced regulatory environment, where a specific mix of rules, regulations, and quality conventions defines its distinctive milieu, but all worlds are subject to some meta-regulatory trends that are emerging in the global food sector, two of which have the potential to induce significant changes. For the sake of simplicity, we shall refer to these meta-regulatory trends as the new moral economy on the one hand and the neo-liberal economy on the other. Taken in isolation, these regulatory trends could trigger very different trajectories of development, with major implications for place, power, and provenance in the food chain, because the former involves reregulating the food sector, while the latter aims to deregulate it.

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Conference papers on the topic "Shallow trench isolation"

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Ghidini, Gabriella, Roberta Bottini, Daniela Brazzelli, et al. "Oxide Thinning in Shallow Trench Isolation." In 2006 IEEE International Reliability Physics Symposium Proceedings. IEEE, 2006. http://dx.doi.org/10.1109/relphy.2006.251248.

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Kahng, Andrew B., Puneet Sharma, and Alexander Zelikovsky. "Fill for shallow trench isolation CMP." In the 2006 IEEE/ACM international conference. ACM Press, 2006. http://dx.doi.org/10.1145/1233501.1233639.

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Kahng, Andrew, Puneet Sharma, and Alexander Zelikovsky. "Fill for Shallow Trench Isolation CMP." In 2006 IEEE/ACM International Conference on Computer Aided Design. IEEE, 2006. http://dx.doi.org/10.1109/iccad.2006.320033.

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Cheng, Juing-Yi, Tan Fu Lei, and Tien Sheng Chao. "A Novel Shallow Trench Isolation Technique." In 1996 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1996. http://dx.doi.org/10.7567/ssdm.1996.pd-4-5.

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Itoh, Akio, Masahiko Imai, and Yoshihiro Arimoto. "Photoresist CMP for Shallow Trench Isolation." In 1997 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1997. http://dx.doi.org/10.7567/ssdm.1997.c-13-1.

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Leong Tse Meng, Goh Inn Swee, J. Bonar, et al. "Sphere defects prevention on shallow trench isolation etch." In ISSM 2005, IEEE International Symposium on Semiconductor Manufacturing, 2005. IEEE, 2005. http://dx.doi.org/10.1109/issm.2005.1513410.

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Niitsu, Y., S. Taguchi, K. Shibata, et al. "Latchup-free CMOS structure using shallow trench isolation." In 1985 International Electron Devices Meeting. IRE, 1985. http://dx.doi.org/10.1109/iedm.1985.191015.

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Dudley, Ian, and Anjan Somadder. "Application of scatterometry to shallow trench isolation monitoring." In Microlithography 2004, edited by Richard M. Silver. SPIE, 2004. http://dx.doi.org/10.1117/12.535437.

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Raymond, Christopher J., Michael E. Littau, Richard J. Markle, and Matthew A. Purdy. "Scatterometry for shallow trench isolation (STI) process metrology." In 26th Annual International Symposium on Microlithography, edited by Neal T. Sullivan. SPIE, 2001. http://dx.doi.org/10.1117/12.436798.

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Alsmeier, Kelleher, Beintner, et al. "A Novel 1b Trench DRAM Cell With Raised Shallow Trench Isolation (RSTI)." In Symposium on VLSI Technology. IEEE, 1997. http://dx.doi.org/10.1109/vlsit.1997.623674.

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Reports on the topic "Shallow trench isolation"

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Shaneyfelt, M. R., P. E. Dodd, B. L. Draper, and R. S. Flores. Challenges in hardening technologies using shallow-trench isolation. Office of Scientific and Technical Information (OSTI), 1998. http://dx.doi.org/10.2172/650373.

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