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1
Lee, Brian 1975. "Modeling of chemical mechanical polishing for shallow trench isolation." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/29907.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 195-201).
This thesis presents the nonlinear analysis, design, fabrication, and testing of an axial-gap magnetic induction micro machine, which is a two-phase planar motor in which the rotor is suspended above the stator via mechanical springs, or tethers. The micro motor is fabricated from thick layers of electroplated NiFe and copper, by our collaborators at Georgia Institute of Technology. The rotor and the stator cores are 4 mm in diameter each, and the entire motor is about 2 mm thick. During fabrication, SU-8 epoxy is used as a structural mold material for the electroplated cores. The tethers are designed to be compliant in the azimuthal direction, while preventing axial deflections and maintaining a constant air gap. This enables accurate measurements of deflections within the rotor plane via a computer microvision system. The small scale of the magnetic induction micro machine, in conjunction with the good thermal contact between its electroplated stator layers, ensures an isothermal device which can be cooled very effectively. Current densities over 109 A/m2 simultaneously through each phase is repeatedly achieved during experiments; this density is over two orders of magnitude larger than what can be achieved in conventional macro-scale machines.
(cont.) More than 5 Nm of torque is obtained for an air gap of about 5 zm, making this micro motor the highest torque density micro-scale magnetic machine to date. About 0.3 buNm for the large air gap of 70 m is also achieved in systematic tests that reveal the influence of strong eddy-currents and associated nonlinear saturation within the micro motor Eddy-current effects are modeled using a finite-difference vector potential formulation. Its results demonstrate the presence of flux crowding on the stator surface, which leads to heavy saturation. To capture saturation effects, a fully nonlinear finite-difference time-domain simulation is developed to solve Maxwell's Equations within the computational space of the micro machine. To mitigate the inherent stiffness in the partial differential equations, the speed of light is artificially reduced by five orders of magnitude, taking special care that assumptions of magnetoquasistatic behavior are still met. The results from this model are in very good agreement with experimental data from the tethered magnetic induction micro motor.
by Brian Lee.
Ph.D.
2
Gan, Terence (Terence Chihkiong) 1975. "Modeling of chemical mechanical polishing for shallow trench isolation." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86469.
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Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.Includes bibliographical references (p. 75-77).
by Terence Gan.
S.B.and M.Eng.
3
Garud, Niharika Triplett Gregory Edward. "Shallow trench isolation process in microfabrication for flash (NAND) memory." Diss., Columbia, Mo. : University of Missouri-Columbia, 2008. http://hdl.handle.net/10355/5622.
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Thesis (M.S.)--University of Missouri-Columbia, 2008.The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on September 2, 2008) Includes bibliographical references.
4
Finkelstein, Hod. "Shallow-trench-isolation bounded single-photon avalanche diodes in commercial deep submicron CMOS technologies." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3274523.
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Thesis (Ph. D.)--University of California, San Diego, 2007.Title from first page of PDF file (viewed October 3, 2007). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 256-271).
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Hsu, Mark J. "Development of shallow trench isolation bounded single-photon avalanche detectors for acousto-optic signal enhancement and frequency up-conversion." Diss., [La Jolla] : University of California, San Diego, 2010. http://wwwlib.umi.com/cr/ucsd/fullcit?p3407959.
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Thesis (Ph. D.)--University of California, San Diego, 2010.Title from first page of PDF file (viewed June 17, 2010). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (leaves 172-191).
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Forsberg, Markus. "Chemical Mechanical Polishing of Silicon and Silicon Dioxide in Front End Processing." Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-4304.
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Dobri, Adam. "Mémoires embarquées non volatiles à grille flottante : challenges technologiques et physiques pour l’augmentation des performances vers le noeud 28nm." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT030/document.
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Les mémoires flash sont intégrées dans presque tous les aspects de la vie moderne car leurs uns et zéros représentent les données stockées sur les cartes à puce et dans les capteurs qui nous entourent. Dans les mémoires flash à grille flottante ces données sont représentées par la quantité de charge stockée sur une grille en poly-Si, isolée par un oxyde tunnel et un diélectrique entre grilles (IGD). Au fur et à mesure que les chercheurs et les ingénieurs de l'industrie microélectronique poussent continuellement les limites de mise à l'échelle, la capacité des dispositifs à contenir leurs informations risque de devenir compromise. Même la perte d'un électron par jour est trop élevée et entraînerait l'absence de conservation des données pendant dix ans. Étant trop faibles, les courants de fuite sont impossible à mesurer directement. Cette thèse présente une nouvelle méthode, la séparation du stress aux oxydes (OSS), pour mesurer ces courants en suivant les changements de la tension de seuil de la cellule flash. La nouveauté de la technique est que les conditions de polarisation sont sélectionnées afin que le stress se produise entièrement dans l'IGD, permettant la reconstruction d'une courbe IV de l'IGD à des tensions faibles. Cette thèse décrit également les changements de processus nécessaires pour intégrer la première mémoire flash embarquée de 40 nm basée sur un IGD d'alumine, en remplacement du SiO2/ Si3N4/SiO2 standard. L'intérêt pour les matériaux high-k vient de la motivation de créer un IGD qui est électriquement mince pour augmenter le couplage tout en étant physiquement épais pour bloquer le transport de charge. Comme la flash intégrée au noeud de 40 nm se rapproche de la production, l'approche à prendre dans les nœuds futurs doit également être discutée. Cela fournit la motivation pour le chapitre final de la thèse qui traite de la co-intégration des différents IGD avec des dispositifs logiques ayant les gilles « high-k metal » nécessaires à 28 nm et au-delàFlash memory circuits are embedded in almost every aspect of modern life as their ones and zeros represent the data that is stored on smart cards and in the sensors around us. In floating gate flash memories this data is represented by the amount of charge stored on a poly-Si gate, isolated by a tunneling oxide and an Inter Gate Dielectric (IGD). As the microelectronics industry’s researchers and engineering continuously push the scaling limits, the ability of the devices to hold their information may become compromised. Even the loss of one electron per day is too much and would result in the failure to retain the data for ten years. At such low current densities, the direct measurement of the leakage current is impossible. This thesis presents a new way, Oxide Stress Separation, to measure these currents by following the changes in the threshold voltage of the flash cell. The novelty of the technique is that the biasing conditions are selected such that the stress occurs entirely in the IGD, allowing for the reconstruction of an IV curve of the IGD at low biases. This thesis also describes the process changes necessary to integrate the world’s first 40 nm embedded flash based on an alumina IGD, in replacement of the standard SiO2/Si3N4/SiO2. The interest in high-k materials comes from the motivation to make an IGD that is electrically thin to increase coupling while being physically thick to block charge transport. As embedded flash at the 40 nm node nears production, the approach to be taken in future nodes must also be discussed. This provides the motivation for the final chapter of the thesis which discusses the co-integration of the different IGDs with logic devices having the high-k metal gates necessary at 28 nm and beyond
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Tavernier, Aurélien. "Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées." Phd thesis, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-00987019.
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Réalisées au début du processus de fabrication des circuits intégrés, les tranchées d'isolation permettent d'éviter les fuites de courant latérales qui pourraient avoir lieu entre les transistors. Les tranchées sont remplies par un film d'oxyde de silicium réalisé par des procédés de dépôt chimiques en phase vapeur (aussi appelés CVD). Le remplissage des tranchées est couramment réalisé par un procédé CVD à pression sub-atmosphérique (SACVD TEOS/O3). Cependant, la capacité de remplissage de ce procédé pour les nœuds technologiques CMOS 28 nm et inférieurs est dégradée à cause de profils trop verticaux dans les tranchées. Cela induit la formation de cavités dans l'oxyde et entraine des courts-circuits. Afin de pallier ce problème, une nouvelle stratégie de remplissage en trois étapes est proposée pour la technologie CMOS 14 nm. Dans la première étape, un film mince d'oxyde est déposé dans les tranchées. Puis, dans la deuxième étape, les flancs du film sont gravés à l'aide d'un procédé de gravure innovant, basé sur un plasma délocalisé de NF3/NH3, permettant de créer une pente favorable au remplissage final réalisé au cours de la troisième étape. Le développement de cette nouvelle stratégie de remplissage s'est déroulé selon plusieurs axes. Tout d'abord, le procédé de dépôt a été caractérisé afin de sélectionner les conditions optimales pour la première étape de la stratégie. Puis, le procédé de gravure innovant a été caractérisé en détail. L'influence des paramètres de gravure a été étudiée sur pleine plaque et sur plaques avec motifs afin de comprendre les mécanismes de gravure et de changement de pente dans les tranchées. Enfin, dans un troisième temps, la stratégie de remplissage a été développée et intégrée pour la technologie CMOS 14 nm. Nous montrons ainsi qu'il est possible de contrôler le changement de pente avec les conditions de gravure et que cette stratégie permet un remplissage des tranchées d'isolation sans cavités.
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吳明昆. "Oxide Etch in Shallow Trench Isolation." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/55852764983108910898.
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碩士國立交通大學
工學院碩士在職專班半導體材料與製程設備學
94
Due to photo resist is widely used in pattern definition with semiconductor process, we need photo resist to protect active region when silicon dioxide inside the shallow trench isolation etch .The thesis studies the high selectivity in oxide over nitride with different process parameters split. The hard mask layer will use silicon nitride instead of resist material. The concept of mask less will diminish process flow and production cost. To increase the etch selectivity for silicon dioxide inside shallow trench isolation to silicon nitride in active region, the parameters of etch will be properly used and adjusted in the experiment. The key factors are process gas ratio and pressure. To fine tune the gas ratio of CHF3 to CF4 with low pressure condition, it will get the highest etch selectivity when the gas ratio value is 4.The monitor wafers will be used to check remain nitride and oxide loss. From the SEM image, we find the silicon nitride in active region will over 9.2nm and silicon dioxide loss in shallow trench isolation is near 180 nm. No mask used in the experiment is available.
10
Heo, Kuenchy, and 何昆奇. "Shallow Trench Isolation(STI) for Sub-micron MOSFET." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/57092779924475988215.
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碩士長庚大學
電機工程研究所
87
In the experiments, the sub-threshold Id hump and inverse narrow width effect were observed above 50nm pad oxide removal(POR). The off current also elevated by increasing the removal of pad oxide. In the extraction of the characteristics of the corner MOSFET, we empirically found the channel threshold voltage(vtsch) was determined at a current of 1.1μA*Wdes/Ldes and the corner threshold voltage(vtscor) was at a current of 26 nA/Ldes. we demonstrated the degradation depend on the pad oxide removal and the 100nm removal of pad oxide has more large degradation than the others in the narrow channel devices. To understand the above results in detail, we measured the impact-ionization rate (α≡Ib/Id) and found that the impact-ionization rate had increased rapidly for the narrow devices with a large dip STI structure during the stress.
11
Chen, Chien-Liang, and 陳建良. "Study of Poly-Si Buffered Shallow Trench Isolation Technology." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/72414352195372640838.
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碩士國立臺灣科技大學
電子工程系
89
The conventional LOCOS-based isolation technology is questionable for ULSI generation due to its inherent bird’s beak, field boron encroachment, and non-planarity issues. Shallow Trench Isolation (STI) combined with chemical-mechanical polishing (CMP) is widely used for deep sub-micron devices due to its high package density and good isolation characteristics for the ULSI age. In Shallow Trench Isolation (STI) structures significant stress buildup in the silicon mesa is often observed during thermal cycling process after STI formation. The thermal cycling lead to tensile stress due to the difference of thermal expansion coefficients between the silicon substrate and the trench fill oxide. As the active area pitch decrease, an increase both in stress and leakage current density is observed. That is the stress induced a huge amount defects and those defects generate larger leakage current density. In this thesis, we proposed to provide a new method to eliminate the stress generating from STI structure formation. We deposit a thin Poly-Si film and use the dry etching technology to form the poly silicon spacer, which is used to be a buffer layer to eliminate the stress. We design several kinds of poly silicon buffer layer thicknesses, thermal cycling temperatures and active area pitches and try to find out the relations between the stress by measuring the leakage current.
12
Hu, En-Sung, and 胡恩崧. "Improvement the Global Planarization Process Factor of Shallow Trench Isolation." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/f4pqgs.
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碩士中原大學
機械工程研究所
91
Along with the increment of the wafer size and the numbers of the metal layers, plus the transistors and the metal lines constantly diminished. The technology of semi-conductor VLSI manufacturing process, which does away with the rough and uneven body, presents its necessity. The CMP is a technique of the global planarization, and each factory of semi-conductor has depended on. It’s making use of the slurry for oxidizing the outstanding part of the dipping layer of the wafer surface first and then polishing the gate oxide by the carrier, thus it can provide a flat surface for the next layer. The CMP also needs a nice bit of factors to match mutually. Thus the factors of how to increase the flatness have become the top lesson to the global planarization. Further it has something to do with the raise of good rate, the increment of productivity and the cost down of production. The results will decide the quality of the follow-up process and the reliability of products since the STI‘s main purpose is to isolate from the cells. The objective of this thesis emphasizes at promoting and improving the global planarization of shallow trench isolation (STI) process and putting forward two methods takes into study: 1. Addition extreme edge HDP etch process to promote the global planarization. 2. Change the STI-CMP carrier speed without extreme edge HDP etch process and discuss the effects of the global planarization. Finally we compare the relation of these two methods with the produce and good rate of the factory of semi-conductor.
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Chen, Ying-Tsung, and 陳盈淙. "The Study of CMOS Shallow Trench Isolation Step-height for Device Characteristics." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/37622253468231688097.
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碩士國立清華大學
工程與系統科學系
95
This research studies the effect on device performance from the step-height difference between Shallow Trench Isolation (STI) and its neighboring transistor active-region in Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The study utilizes the two methods of Chemical Mechanical Planarization (CMP) and Hydro-Fluoric Acid (HF) wet etch to create dielectric step-height difference higher or lower than standard, than discuss the effect on transistor isolation properties, specifically Junction Leakage and it’s effect on device performance, including Short Channel Effect (SCE), Narrow Width Effect (NWE), etc. For qualitative analysis, it was discovered that the final STI physical structure is determined by the initial step-height right after CMP or HF wet-dip process is finished. It is gradually decrease correlations both step-height and divot. On quantitative analysis, we find out the relationship of specific pattern thickness versus the outcome of step-height. The relationship of CMP Nitride thickness and step-height was found to be 0.43：1; HF wet-dip oxide thickness and step-height’s relationship was found to be 1.77：1. In electrical performance, the results show that when step-height was reduced from 660 Å to 170Å, 3 to 5 order of magnitude difference in Inter-well leakage was found in the minimum feature transistor (clearance 0.08 �慆). For NWE property, there was a 10 to 20% enhanced in saturation drain current (Idsat) for the narrowest width device (0.12 �慆). For SCE property, 9.8 to 16.5 mV/V difference on DIBL was found for the shortest tunnel-length device (50 nm). It is shown that transistor performance can be significantly affected by step-height change. Besides, we employed 3 patterns of difference sizes, attempting to find the individual contribution of perimeter and area on interface leakage. The results show that area’s contribution to leakage is 22 to 24 times as much as perimeter’s contribution, indicating the device size as the determining factor for device leakage. We can make use of this relationship to calculate the leakage value for patterns with known area and perimeter; for step-height between 660 to 390 Å, the error margin is within 10%. This study links the relationship of the process thickness parameter between step-height and electrical performance; the result can help control device abnormality, furthermore can be the development basis for Advanced Process Control, thus be used as an important reference for process control and yield improvement.
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Wang, ZIh-Song, and 王子嵩. "The Reliability Study of Self-Aligned Shallow Trench Isolation NAND Flash Memory." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/71218676141422394216.
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博士國立清華大學
電子工程研究所
101
Over the past 10 years, the dimension of NAND flash cell has decreased dramatically, from 130nm to middle-1Xnm. As technology nodes advance, various scaling barriers appear, and minor effects become increasingly problematic. Therefore, scaling conventional floating gate technology is very difficult due to physical and electrical limitations. This dissertation proposes some feasibility of fabricating optimized processes on 50-nm NAND Flash technology. First, a flat-bottom Control Gate (CG) with a raised STI has been developed to maintain adequate reliability distance against stresses from cycling, as well as filling in the small Floating Gate (FG) to FG spacing. Thus, the proposed flat-bottom CG structure and process are the most promising solution for advanced Self-Aligned shallow trench isolation (SA-STI) structure exceeding 50 nm. Second, the “redirection programming electron” Inter-Poly Dielectric (IPD) leakage in the traditional SA-STI structure presented here for the first time and redirection IPD leakage current are determined, these should be considered new phenomena. The design of NAND Flash structure should be optimized by a smaller CG fringing E-field effect and special IPD engineering for this unanticipated leakage current when scaling future NAND Flash. Third, this dissertation demonstrates the feasibility of the degradation model of data retention on NAND Flash memory as the bottom poly oxide (BPO) is scaled down. The proposed solution, involving an optimized IPD film scheme with FG top nitridation, solves the “FG charge loss” problem and eliminates “trapped electrons back-tunneling” from the IPD. Finally, the degradation model of the passivation process on a FG type NAND Flash memory is demonstrated. The water (moisture) diffusion model explains all degradation phenomena and observations explain why post metallization anneal (PMA) should be arranged before the deposition of the top P-SiN or the coating of the top metal with Polymide (PI). This dissertation contributes significantly to efforts to improve the endurance and retention of FG-type NAND Flash memory by optimizing the passivation process flow and film scheme. In summary, this dissertation provides some design considerations for cell structure and promising solutions to continue miniaturizing the technology with the same reliability characteristics.
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Wang, Shih-Yao, and 王詩堯. "Analysis on Pad Performance for Chemical Mechanical Polishing/Planarization of Shallow Trench Isolation." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/6x27u4.
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碩士國立臺灣科技大學
機械工程系
106
Chemical mechanical planarization/polishing (CMP) has been widely adopted in the integrated circuit (IC) fabrication. Due to demand of IC downsizing to nanoscale, CMP process stability and reproducibility continue to face stringent challenges. Polishing pad surface topography is one of the major factors for determination on wafer planarization, which pad polishing efficiency index (PEI) can be considered as one of quantification of pad surface performance in CMP process. This study is to develop PEI based on the interfacial area ratio (Sdr) and related root-mean-square surface roughness(Sq) and (Spk). The PEI is (Sdr) defined by the ratio between multiplication of the interfacial area ratio and reduced peak height (Spk) dividing to the root mean square height (Sq). Finally, the shallow trench isolation (STI) CMP process is used to verified by PEI. The CMP process of silicon oxide (SiO2) and silicon nitride (Si3N4) film wafers has been verified to identify the correlation between the pad PEI and material removal rate (MRR) of oxide and nitride film wafer. Experimental results show that the PEI increases as with MRR of oxide wafer increasing and also as decreasing wafer surface topography. Thus the PEI can be used a pad performance index for STI CMP process based on current configuration of this study. Results of this study can be further adopted as an index for in-situ monitoring of pad topography for process control of STI CMP for advanced node IC demands.
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Wu, Chia-Wei, and 吳嘉偉. "The Impact of the Shallow Trench Isolation on the Reliability of Trigate MOSFET." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/86954388498297361375.
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碩士國立交通大學
電子工程學系 電子研究所
103
For the continuing scaled down of the device’s size, many problems will be encountered such as short channel effect, random dopant fluctuation, and leakage currents. Several of these problems have been handled well in advanced CMOS technology. Among these, the trigate structure has been considered to be the candidate for the future generations. Trigate MOSFET has better gate controllability to solve the short channel effect. It also has immunity from the random dopant fluctuation because of the lightly doped channel. However, trigate devices also suffer from another problems such as side wall surface roughness, metal work function variation, and self-heating effect etc. The trigate device needs to be thoroughly studied for the future design and applications. Since the fin width is getting thinner, the STI (shallow trench isolation) are closer to the channel region, and it might have some impacts on that. In this thesis, we propose a new method to characterize the STI traps under the fin channel. Under the long term NBTI stress, the standard deviation of threshold voltage will change and by using the trigate depletion model we proposed, we can easily find the distribution of these traps under the channel region. The second part, we apply the technique to examine the radiation induced random STI traps. It is known that the X-ray will have an influence on STI traps. As the size of MOSFET shrinks down, the gate oxide is becoming so thin. However the STI oxide cannot become as thin as the gate oxide, so there are still some problems when exposing under the radiations. In the previous studies that were mainly focusing on the nuclear models or the effects of different kinds of radiations. We first combined the reliability test with the X-ray. After being exposed to the radiations, the trigate devices were then taken to the NBTI testing. The pre X-ray irradiated procedure affects the reliability a lot due to the massively increased STI traps. The on current of the device will be degraded and threshold voltage will increase due to the increased STI traps near the channel region. This result is helpful to the design of the future devices especially in the space technology.
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Chang, Ming-Feng, and 張明豐. "Study of Shallow Trench Isolation Processes to Improve the Reliability on Flash Memory." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/97625039631290119288.
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碩士國立中興大學
材料科學與工程學系所
101
Flash Memory Technology has been developed over 20 years, and advance 20nm node floating gate structural flash is main stream on non-volatile memory market. And it faces reliability failure on process critical dimension shrinkage, therefore, it is important to improve process to ensure the reliability performance. Many papers of process improvement on reliability respect already disclosed in semiconductor engineering journals, including plasma induce damage; hydrogen penetrate to influence tunnel oxide quality; mechanical stress; tunnel oxide integrity and etc. these improvement research is on going. The technology of this paper was to focus on 120nm NAND type flash process technology. To investigate tunnel oxide integrity and to use shallow trench isolation related processes to improve the reliability, the experiments included additional N2 treatment after shallow trench isolation liner HTO(high temp. oxidation) oxide deposition; shallow trench isolation liner HTO(high temp. oxidation) oxide thickness split and different shallow trench isolation high density plasma oxide(STI HDP oxide) deposition method. Base on these experiments to check 100k cycling erase threshold voltage(Vte) difference, the minor erase threshold voltage(Vte) push up after 100k cycling was to change shallow trench isolation oxide deposition method. It was improved from 3.08V to 2.35V and it can judge the correct data after 100k cycling.
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Liao, Chu Feng, and 廖矩鋒. "A Novel CMOS Logic Compatible Shallow Trench Isolation Sidewall edge Resistive Random Access Memory." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/89223580516228085463.
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碩士國立清華大學
電子工程研究所
104
In the future, digitized world can be achieved by IOT. All item will be network links, human life may be changed. With the wisdom handheld products takeoff, products are slim and light as a trend and Process-in-Memory , PIM is the most representative technology to make the memory embedded in CPU. On the one hand it can enhance the operation speed, on the other hand it can reduce the power consumption. This technology might be a key to the generation of IOT and big data. Large information must have a corresponding storage media for operation and usage. Currently, the main NVM is flash on the market. As semiconductor manufacturing process scales, the charge in the floating gate decreases .The storage state will become difficult to identify. Flash may encounter the physical limitation that can’t operate and use normally. Therefore, new NVM exploitation is important nowadays. Based on 40nm COMS logic process, we realized Shallow trench Isolation Sidewall Edge Resistive Random Access Memory(STI Sidewall Edge RRAM).No additional process masks and ultra-small size is the characteristic of this memory. We can control the RRAM film easily and precisely. The variation of this cell may decrease with process scaling. By DC and AC operation, this memory has the feature of low power consumption and high program speed. Incremental Step Pulse Programming(ISPP) Algorithm can be used to promote the endurance to make this memory achieve 1000K Set/Reset cycles. Data stored show stability under 150oC baking over a period of 1000K seconds and it can endure 10K seconds continuously reading that guarantee STI Sidewall Edge RRAM unit has no reliability concern. STI Sidewall Edge RRAM has great operation feature and data retention ability.
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Huang, Kuo-Feng, and 黃國峰. "Study of Nano-scale Shallow Trench Isolation Planarization Process for Semiconductor Integrated Circuits Manufacture." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/11902889614422452825.
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碩士國立交通大學
光電科技學程
100
With semiconductor manufacture shrunk down to the nano-scale technology, the shallow trench isolation (STI) of the device would be faced to the nano-scale manufacturing and integration. The nano-scale shallow trench isolation could provide well isolation and surface condition to reduce current leakage. The well shallow trench isolation performance was dominated by the Oxide film deposition and following Chemical Mechanical Planarization (CMP). Accompanying device dimension shrunk down, the semiconductor manufacture micro defect issue, such as silicon substrate damage due to Nitride film not stopping the polishing planarization effectively, or device current leakage induced by micro scratch. This thesis would focus on the slurry effect on micro defect including silicon damage and micro scratch. Unique high SiO2/ Nitride removal rate selectivity slurry and combining new concept STI polishing sequence to two steps from three steps could purpose well isolation and surface condition. It also results in well device leakage performance on nano-scale semiconductor manufacture.
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Hong-JiaKong and 龔泓家. "Studies of the Novel Shallow Trench Isolation Technology for Deep Nano CMOS Device Application." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/82697809014373009610.
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Yang, Wen-Jei, and 楊文杰. "The Width-Dependent Hot Carrier Reliability of Deep-Submicron CMOS with Shallow Trench Isolation." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/64955702322560017981.
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碩士國立交通大學
電子工程系
87
To improve the packing density of integrated circuits, scaling of CMOS isolation become indispensable. Recently, the shallow-trench-isolation (STI) technology has been widely used to achieve this goal. Moreover, STI can improve the subthreshold hump, bird掇 beak, and field oxide thinning effect in LOCOS (Local Oxidation of Silicon). However, hot-carrier effect has been be a major reliability issue in a STI device. In this thesis, width dependent hot-carrier degradation of shallow-trench-isolated MOSFET's is investigated. Smaller hot carrier injection is observed in a narrower device. However, it is shown that a narrower device causes larger drain current degradation under the same stress condition. A new model is then proposed to explain the width dependent degradation. This model is based on the channel shortening concept which can be used to explain the width dependent hot carrier degradation in PMOSFET's. It was found that the channel shortening length after device stress becomes larger at the edge of a PMOFET. Thus, a narrower PMOSFET has larger effective channel shortening length and hence a larger current degradation after stress. In the case of NMOSFET's, enhanced interface state generation was found at the STI edge. This may be due to the mechanical stress at the device edge. So, the average amount of interface states and current degradation in a narrower NMOSFET is larger after hot-carrier stress.
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Hsu, Meng-Yin, and 許孟尹. "Shallow Trench Isolation Sidewall edge Resistive Random Access Memory Integrated Nonvolatile Static Random Access Memory." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/k76znp.
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Siu, Tang Ng, and 吳兆騰. "Study of Shallow Trench Isolation Gap Filling Capability for Advanced DRAM by Chemical Vapor Deposition." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/41610688803739803030.
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碩士國立交通大學
工學院碩士在職專班半導體材料與製程設備學
94
In this thesis, we explored the extendibility of shallow trench isolation (STI) gap filling capability of undoped silicate glass (USG) prepared by high aspect ratio process (HARP) in sub-atmosphere chemical vapor deposition (SACVD) systems for sub-70 nm technology nodes for the advanced dynamic random access memory (DRAM) applications. Based on the study, a 3-step deposition process, which is capable of achieving void free gap filling at 0.06μm trench width and > 7:1 aspect ratio with a smooth profile of trench sidewall, was developed. The first step is to deposit a homogeneous nucleation layer with trivial surface selectivity by using a gas source with a high O3/ tetraethoxysilane (TEOS) ratio so that better film conformality can be achieved. The second step is to deposit a sufficiently thick USG to fill trenches with a small to moderate width by using a gas feed of a relatively high O3/TEOS ratio. The final step is targeted at throughput enhancement. The effect of initial TEOS composition and annealing treatment after the HARP USG deposition on the trench filling capability was also studied.
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Wu, Jiwnn-Jye, and 吳俊杰. "The Application of the Selective Liquid-Phase Deposited Oxide to the Shallow Trench Isolation Technology." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/94891119917656878697.
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碩士國立交通大學
電子工程系
87
Selective deposition against photoresist for liquid-phase deposited oxide has been found. According to this unique characteristic, the shallow trench isolation technology without etching back in integrated circuits is developed. In this thesis, we call it selective liquid-phase deposition shallow trench isolation (SLPD-STI) technology. SLPD-STI processes begin with photoresist masked silicon etching on a silicon wafer. Selective liquid-phase oxide deposition is followed to refill the shallow trench. After that, photoresist mask on the active device region is removed. At last, thin sacrificial oxide is grown and a SLPD oxide densification process is performed. Then, the processes of SLPD-STI technology are finished after removing sacrificial oxide. At first, the excellent gap filling ability of the selective liquid-phase deposited oxide over conventional CVD oxide is confirmed. It is found that high aspect-ratio narrow trench can be filled with selective liquid-phase deposited oxide free of voids. In order to verify the feasibility of SLPD-STI technology, we fabricate test devices such as capacitors, n+/p junction diodes, n+/n+ metal-gate isolation transistors and nmos poly-gate transistors, with our proposed SLPD-STI technology. It is demonstrated that good electrical performances of devices fabricated by SLPD-STI technology can be obtained. In addition, the effects of different thermal treatments on the isolation efficacy and devices electrical characteristics for SLPD-STI technology are also investigated. It indicates that short-time oxidation before refilled-oxide densification is necessary for SLPD-STI technology to obtain better electrical performances of devices.
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Wei, Chin-chung, and 魏清忠. "An investigation of the effects of fixed abrasive chemical mechanical polishing to shallow trench isolation process." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/09326768543061965596.
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碩士國立成功大學
工程科學系專班
95
At present, chemical mechanical polishing (CMP) is the most effective technology to achieve global planarization in semiconductor manufacturing processes. In recent years, the feature size of the IC processes is down to the nanometer range. Because the interconnect and electrode patterns are defined by masks, the wafer global planarization is very important. Without CMP, it is extremely difficult to focus in the unsmooth wafer surface. Furthermore, the connection between each electric circuit also needs suitable planarization, otherwise the interconnections may be short or cause leakage currents. Thus, CMP plays an extremely important role in the IC manufacturing industry. The purpose of this study is to investigate the effects of the important fixed abrasive polishing (FACMP) parameters and consumables for the shallow trench isolation process. From the parameters, consumables and Taguchi DOE methods, the best polishing performance is obtained. The experimental results not only improve the double removal rate for polishing but also 6% uniformity performance
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Yeh, Po-Feng, and 葉柏峰. "Design & Implementation of 5-GHz-Band Wide Tuning Range VCO and Shallow Trench Isolation Varactors." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/85318346870477258704.
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碩士國立暨南國際大學
電機工程學系
94
In this thesis, study of three passive devices, and a wide tuning range voltage controlled oscillator (VCO) which is applied to the wireless transceiver. Three devices included variable inductances inductors and varactors applied to ultra-tuning range VCO and transformers for millimeter-wave applications. A variable monolithic inductor having a planar spiral inductor connected with MOSFET switches is proposed。By controlling a voltage of the MOSFET switch gate and body for inductance。.The varactors were fabricated by shallow trench isolation to make the performances of varactors better. It can increase the turning range and decrease the phase of it, and study the influence of differential shallow trench isolation wide. In chapter 4, we demonstrate that high-coupling and ultra-low-loss transformers for 60100 GHz CMOS RFIC applications can be achieved by using single-turn two-layer interlaced stacked (STIS) structure implemented in a standard CMOS technology. In chapter 5, the 5.5-GHz low power consumption and wide tuning range differential voltage-controlled oscillator (VCO) is presented. This circuit optimized for maximum tuning range was designed and fabricated using TSMC 0.18-um one-poly-six metal (1P6M) CMOS process. Keywords: MOSFET, shallow trench isolation (STI), coupling, RFIC, VCO
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Cheng, Tzu How, and 鄭子浩. "Application of Multivariable Run-to-run Control for Shallow Trench Isolation Process of Chemical Mechanical Polishing." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/24198274103785424832.
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碩士長庚大學
化工與材料工程研究所
96
Abstract The semiconductor manufacturing industry is arguably the fastest evolving major industry in the world. Success in the industry requires constant attention to the state of the art in process tool, process chemistries and physics, and technicians for processing and process improvement. The chemical mechanical polishing (CMP) is the key technology for global planarization at integrated circuit. In CMP process, lots of factors result in process variations. Therefore, how to effectively decrease or eliminate the variation sources is an important issue. This study uses the multivariable control strategy to predict the key variables of the STI CMP process. The empirical parameters of the mechanical mechanism are considered in the projects. The results show that the suitable recipe inputs are provided to overcome the unknown disturbances. One can use the modified double EWMA control to adjust over polishing time and zone pressures, to make the nitride thickness and oxide film uniformity achieve the corresponding process targets.
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Eberlein, Michel. "Contraintes locales induites par le procédé « Shallow Trench Isolation » : Diffraction X haute résolution et simulation par éléments finis." Phd thesis, 2008. http://tel.archives-ouvertes.fr/tel-00419896.
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La procédé STI (« Shallow Trench Isolation ») est couramment utilisé dans la microélectronique afin d'isoler électriquement les dispositifs entre eux. Les nombreuses étapes de ce procédé engendrent des contraintes mécaniques très importantes qui peuvent nuire à la fiabilité. L'originalité de la diffraction X haute résolution est d'utiliser l'intensité diffractée par le silicium déformé périodiquement comme empreinte du champ de déformation locale. Les mesures ont porté sur des structures de période allant de 2 µm à 200 nm, avec des lignes de silicium de largeur inférieure à 100 nm pour les plus petites périodes. Pour les échantillons de période submicronique, un second pic de diffraction apparaît sur les cartographies du réseau réciproque. Ce pic est attribué à une déformation homogène du silicium entre les tranchées et permet une mesure directe et sans modèle des déformations. L'effet sur les déformations et les contraintes de variations géométriques et de procédé ont été ainsi étudiées. Cette méthode expérimentale s'appuie sur des simulations numériques par éléments finis.
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Lai, Jinn-Horng, and 賴進鴻. "The Effects of Shallow Trench Isolation Induced Mechanical Stress on The Electrical Properties of Deep Sub-Micron MOSFETs." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/81514251140128095265.
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博士國立清華大學
電機工程學系
92
Shallow trench isolation induced mechanical stress has become more and more important as the dimension of devices scaling-down continuously. The stress can induce the variation of device’s performance as large as 20% depend on processes and layout of devices. Up to now, the layout dependence of the STI mechanical stress effect has not been understood clearly. In this thesis, we have proposed an exponential stress distribution model successfully explaining most of the behaviors of the layout dependent STI-induced mechanical stress effect. Temperature dependence of STI mechanical stress effect has been studied thoroughly for the first time in this thesis. According to the results, increased operating temperature results in a slight reduction of the drive-current degradation caused by STI-induced mechanical stress for n-MOSFET. An empirical formula was obtained and can be taken into account in IC design easily. In order to overcome STI-induced mechanical stress effect, we have proposed a new method to improve the stress effect by changing the structure of n-MOSFET without any modification of processes. It has been proved that the new structured devices are less sensitive to STI-induced mechanical stress effect than conventionally structured devices due to the stress reduction in newly structured devices. In the noise point of view, we have shown that noise characteristics are insensitive to STI-induced mechanical stress.
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Yen, Yung-Ming, and 嚴永民. "Dislocation Improvement and Yield Enhancement for the Process of the Shallow Trench Isolation of High Voltage Semiconductor Devices." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/91557821370083944779.
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碩士國立交通大學
工學院半導體材料與製程設備學程
100
Shallow Trench Isolation (STI) techniques are essential for semiconductor device for reducing electrical interferences between devices of sub-micro and sub 100-nm High Voltage Complementary Metal-Oxide- Semiconductor. By separating active regions with oxide isolation structures, it is possible to reduce the cross-talk between elements. STI has become more and more important as the dimension of devices continuously scales down. However, the mismatch in thermal and mechanical properties between the oxide and the silicon substrate create, enormous stress and results in current leakage due to the generation of dislocations in active zones. As a result, it is important to carefully design the isolation structures. In the STI structure, a significant stress is built up in the silicon mesa during the thermal cycling process after the STI formation. The thermal cycling lead to tensile stress as a result of the difference in the thermal expansion coefficient between the silicon substrate and the trench fill oxide. As the active area pitch decreases, an increase both in the stress and the leakage current density is observed. The stress causes a large amount of defects, which results in a large leakage current density. This study explores the cause of the cause of the stress build-up during thermal cycling process. We optimize the thickness of the liner oxide layer and the liner nitride layer and the thermal cycling temperature to eliminate the production of the dislocation.
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Tsao, F. C., and 曹峰誠. "The Effect of LOCOS Isolation and Shallow Trench Isolation on the Gate Oxide Integrity and The Impact of MOSFET with and without S/D Junctions on the C/V Measuring of Ultra Thin Gate Oxide." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/84612879648625447490.
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碩士國立成功大學
電機工程學系
89
The Effect of LOCOS Isolation and Shallow Trench Isolation on the Gate Oxide Integrity In the part of this thesis, the effect of LOCOS isolation and STI (shallow trench isolation) on the gate oxide integrity is investigated. In LOCOS process, oxide encroachment under the nitride mask, called “Bird’s Beak” reduces the active area. If one uses the thicker nitride film or the thinner pad oxide film to reduce the bird’s beak length, the stress induced crystalline defects become more prevalent. In addition, the GOI(gate oxide integrity) will be impacted by the Kooi effect induced gate oxide thinning and the boron out diffusion after channel stop implantation. In STI process, there is high leakage current on the corner dues to high electric field. Therefore, the gate oxide is usually breakdown at this location. A way to improve the problem is corner rounding. The commonly used technique for corner rounding is the thermal lining oxidation of the trench sidewall. In addition, the corner will be damaged when the trench is filled oxide using HDP CVD due to the sputtering effect of the HDP CVD. Turn off the low frequency bias at the initial stage of depositing oxide can solve the problem. Furthermore, the impact of different isolation processes on GOI with different gate thickness is investigated. At 48Å gate oxide (0.25μm generation), the GOI is better with LOCOS process. While as the gate oxide is 32Å (0.25μm generation), the GOI is better by using STI process. This means, the LOCOS process is preferred in 0.25μm technology. However as down to 0.18μm technology, the STI process is more suitable. The Impact of MOSFET with and without S/D Junctions on the C/V Measuring of Ultra Thin Gate Oxide In the part of this thesis, the impact of different gate oxide thickness and different device structure on the C/V measuring was investigated. The results of C/V measuring on MOS capacitor with 70Å gate oxide exhibit low-frequency C/V curve at 1kHz frequency and high-frequency C/V curve at 10kHz~1MHz frequency. However, only the high-frequency C/V curve was found with 1kHz~1MHz frequency on the MOS capacitor with 26Å and 20Å gate oxide. This is due to the decrease in generation-recombination rate of carrier on the gate oxide by the direct tunneling. In MOSFET structure, the C/V measuring curve is similar to the MOS capacitor. However, if the source and drain of MOSFET were connected with bulk grounding, the low-frequency C/V curves were always found from 1kHz to 1MHz frequency for 26Å and 20Å gate oxide device. It is because the grounded source and drain provide enough gate oxide carrier to increase the rate of generation-recombination of carrier, so that the generation-recombination rate of carrier on the gate oxide of the structure is fast enough for all frequency.