Log in

Relevant bibliographies by topics / Shallow trench isolation / Journal articles

To see the other types of publications on this topic, follow the link: Shallow trench isolation.

Journal articles on the topic 'Shallow trench isolation'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Shallow trench isolation.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Sang, Sheng Bo, Chen Yang Xue, Wen Dong Zahng, and Ji Jun Xiong. "Raman Investigation of Stress for Shallow Trench." Defect and Diffusion Forum 265 (May 2007): 1–6. http://dx.doi.org/10.4028/www.scientific.net/ddf.265.1.

Full text

Abstract:

A trench is used as a storage capacitor in dynamic memory (DRAM) technologies (deep storage trenches), or as an isolation structure in CMOS, bipolar and BiCMOS technologies. But a shallow trench structure has also been shown to be a major factor in substrate defect generation during processing. Such defect generation is directly related to mechanical stresses existing around the trench. This stress can be monitored, using Raman spectroscopy, to a stress resolution of 10MPa and a spatial resolution of 0.2μm. In this paper, a trench structure is designed and fabricated, and the test results for local stresses within the trench are shown to be in good correspondence with theory.

APA, Harvard, Vancouver, ISO, and other styles

2

Cheng, Juing-Yi, Tan Fu Lei, and Tien Sheng Chao. "A Novel Shallow Trench Isolation Technique." Japanese Journal of Applied Physics 36, Part 1, No. 3B (March 30, 1997): 1319–24. http://dx.doi.org/10.1143/jjap.36.1319.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Gupta, Aakashdeep, K. Nidhin, Suresh Balanethiram, Shon Yadav, Anjan Chakravorty, Sebastien Fregonese, and Thomas Zimmer. "Static Thermal Coupling Factors in Multi-Finger Bipolar Transistors: Part I—Model Development." Electronics 9, no. 9 (August 19, 2020): 1333. http://dx.doi.org/10.3390/electronics9091333.

Full text

Abstract:

In this part, we propose a step-by-step strategy to model the static thermal coupling factors between the fingers in a silicon based multifinger bipolar transistor structure. First we provide a physics-based formulation to find out the coupling factors in a multifinger structure having no-trench isolation (cij,nt). As a second step, using the value of cij,nt, we propose a formulation to estimate the coupling factor in a multifinger structure having only shallow trench isolations (cij,st). Finally, the coupling factor model for a deep and shallow trench isolated multifinger device (cij,dt) is presented. The proposed modeling technique takes as inputs the dimensions of emitter fingers, shallow and deep trench isolations, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are validated against 3D TCAD simulations of multifinger bipolar transistors with and without trench isolations. Geometry scalability of the model is also demonstrated.

APA, Harvard, Vancouver, ISO, and other styles

4

Boning, Duane, and Brian Lee. "Nanotopography Issues in Shallow Trench Isolation CMP." MRS Bulletin 27, no. 10 (October 2002): 761–65. http://dx.doi.org/10.1557/mrs2002.246.

Full text

Abstract:

AbstractAs advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important concern in shallow trench isolation (STI) on wafers polished by means of chemical–mechanical planarization (CMP). Previous work has shown that nanotopography—small surface-height variations of 10–100 nm in amplitude extending across millimeter-scale lateral distances on virgin wafers—can result in CMP-induced localized thinning of surface films such as the oxides or nitrides used in STI. A contact-wear CMP model can be employed to produce maps of regions on a given starting wafer that are prone to particular STI failures, such as the lack of complete clearing of the oxide in low spots and excessive erosion of nitride layers in high spots on the wafer. Stiffer CMP pads result in increased nitride thinning. A chip-scale pattern-dependent CMP simulation shows that substantial additional dishing and erosion occur because of the overpolishing time required due to nanotopography. Projections indicate that nanotopography height specifications will likely need to decrease in order to scale with smaller feature sizes in future IC technologies.

APA, Harvard, Vancouver, ISO, and other styles

5

Brady, F. T., J. D. Maimon, and M. J. Hurt. "A scaleable, radiation hardened shallow trench isolation." IEEE Transactions on Nuclear Science 46, no. 6 (1999): 1836–40. http://dx.doi.org/10.1109/23.819162.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Srinivasan, Ramanathan, Pradeep VR Dandu, and S. V. Babu. "Shallow Trench Isolation Chemical Mechanical Planarization: A Review." ECS Journal of Solid State Science and Technology 4, no. 11 (2015): P5029—P5039. http://dx.doi.org/10.1149/2.0071511jss.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Itoh, Akio, Masahiko Imai, and Yoshihiro Arimoto. "Photoresist Chemical Mechanical Polishing for Shallow Trench Isolation." Japanese Journal of Applied Physics 37, Part 1, No. 4A (April 15, 1998): 1697–700. http://dx.doi.org/10.1143/jjap.37.1697.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Hong, Sug Hun, Dong Ho Ahn, Moon Han Park, and Ho Kyu Kang. "A Novel T-Shaped Shallow Trench Isolation Technology." Japanese Journal of Applied Physics 40, Part 1, No. 4B (April 30, 2001): 2616–20. http://dx.doi.org/10.1143/jjap.40.2616.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Belyansky, M., N. Klymko, R. Conti, D. Chidambarrao, and F. Liu. "Study of silicon strain in shallow trench isolation." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 28, no. 4 (July 2010): 829–33. http://dx.doi.org/10.1116/1.3427660.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Chen, Coming, Chun-Yen Chang, Jih-Wen Chou, Water Lur, and Shih-Wei Sun. "Shallow-Trench Isolation With Raised-Field-Oxide Structure." Japanese Journal of Applied Physics 39, Part 1, No. 3A (March 15, 2000): 1080–84. http://dx.doi.org/10.1143/jjap.39.1080.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Roussy, A., L. Delachet, D. Belharet, J. Pinaton, and P. Collot. "Oxide HDP-CVD Modeling for Shallow Trench Isolation." IEEE Transactions on Semiconductor Manufacturing 23, no. 3 (August 2010): 400–410. http://dx.doi.org/10.1109/tsm.2010.2051749.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Shaneyfelt, M. R., P. E. Dodd, B. L. Draper, and R. S. Flores. "Challenges in hardening technologies using shallow-trench isolation." IEEE Transactions on Nuclear Science 45, no. 6 (1998): 2584–92. http://dx.doi.org/10.1109/23.736501.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Cabanal, J. P., and M. Haond. "Improved shallow trench isolation for sub-halfmicron CMOS." Microelectronic Engineering 15, no. 1-4 (October 1991): 651–54. http://dx.doi.org/10.1016/0167-9317(91)90303-u.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Fejes, Peter, N. David Theodore, and Han-Bin Liang. "Geometry-dependence of defects in PBLT serpentines." Proceedings, annual meeting, Electron Microscopy Society of America 50, no. 2 (August 1992): 1410–11. http://dx.doi.org/10.1017/s0424820100131681.

Full text

Abstract:

Poly-buffered LOCOS + trench-isolation is a technique being explored for device-isolation on semiconductor substrates. The method creates self-aligned shallow field-oxide elements with minimal encroachment into active regions. In an earlier study/dislocations were observed in PBLT structures, associated with a combination of high-dose [∼1E15 cm−2] phosphorus implants and PBLT isolation. The present study investigates the effect of implant- and isolation-geometries on the formation of extended-defects in PBLT structures. The effect of fabrication-related stresses in the structures is of interest because extended-defects, once formed, can electrically degrade devices.PBLT structures were fabricated using varied implant- and isolation- geometries. Selected regions of the structures were exposed to 1E15 cm−2 phosphorus implants. Transmission electron microscopy was then used to characterize these regions. Some of the structures investigated were (i) trench with no adjacent implant, (ii) trench with an adjacent trench, but no implant, (iii) trench with a 1E15 cm−2 phosphorus implant placed ∼4 μm from the trench, (iv) trench with a 1E15 cm−2 phosphorus implant placed ∼2 μm from the trench, (v) doubly-kinked trench with a 1E15cm−2 phosphorus implant placed between the kinks.

APA, Harvard, Vancouver, ISO, and other styles

15

Faccio, Federico, Hugh J. Barnaby, Xiao J. Chen, Daniel M. Fleetwood, Laura Gonella, Michael McLain, and Ronald D. Schrimpf. "Total ionizing dose effects in shallow trench isolation oxides." Microelectronics Reliability 48, no. 7 (July 2008): 1000–1007. http://dx.doi.org/10.1016/j.microrel.2008.04.004.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Cheng, Juing‐Yi, Tan Fu Lei, Tien Sheng Chao, Daniel L. W. Yen, B. J. Jin, and C. J. Lin. "A Novel Planarization of Oxide‐Filled Shallow‐Trench Isolation." Journal of The Electrochemical Society 144, no. 1 (January 1, 1997): 315–20. http://dx.doi.org/10.1149/1.1837402.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

VanDerVoom, P., D. Gan, and J. P. Krusius. "CMOS shallow-trench-isolation to 50-nm channel widths." IEEE Transactions on Electron Devices 47, no. 6 (June 2000): 1175–82. http://dx.doi.org/10.1109/16.842959.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Irrera, F., G. Puzzilli, L. Ricci, F. Russo, and F. Stirpe. "T-shaped shallow trench isolation with unfilled floating void." Solid-State Electronics 52, no. 8 (August 2008): 1188–92. http://dx.doi.org/10.1016/j.sse.2008.05.002.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Lee, YongJae. "Simulations of Proposed Shallow Trench Isolation using TCAD Tool." Journal of the Korea Society for Simulation 22, no. 4 (December 31, 2013): 93–98. http://dx.doi.org/10.9709/jkss.2013.22.4.093.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Yeh, Wen-Kuan, Tony Lin, Coming Chen, Jih-Wen Chou, and Shin-Wei Sun. "A Novel Shallow Trench Isolation with Mini-Spacer Technology." Japanese Journal of Applied Physics 38, Part 1, No. 4B (April 30, 1999): 2300–2305. http://dx.doi.org/10.1143/jjap.38.2300.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Blumenstock, K. "Shallow trench isolation for ultra-large-scale integrated devices." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 12, no. 1 (January 1994): 54. http://dx.doi.org/10.1116/1.587107.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Hu, Chan-Yuan, Jone F. Chen, Shih-Chih Chen, Shoou-Jinn Chang, Shih-Ming Wang, Chih-Ping Lee, and Kay-Ming Lee. "Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology." Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 28, no. 2 (March 2010): 391–97. http://dx.doi.org/10.1116/1.3359612.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Esqueda, Ivan S., Hugh J. Barnaby, Philippe C. Adell, Bernard G. Rax, Harold P. Hjalmarson, Michael L. McLain, and Ronald L. Pease. "Modeling Low Dose Rate Effects in Shallow Trench Isolation Oxides." IEEE Transactions on Nuclear Science 58, no. 6 (December 2011): 2945–52. http://dx.doi.org/10.1109/tns.2011.2168569.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Cooperman, S. S., A. I. Nasr, and G. J. Grula. "Optimization of a Shallow Trench Isolation Process for Improved Planarization." Journal of The Electrochemical Society 142, no. 9 (September 1, 1995): 3180–85. http://dx.doi.org/10.1149/1.2048709.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Li, Yiming, Hung-Ming Chen, Shao-Ming Yu, Jiunn-Ren Hwang, and Fu-Liang Yang. "Strained CMOS Devices With Shallow-Trench-Isolation Stress Buffer Layers." IEEE Transactions on Electron Devices 55, no. 4 (April 2008): 1085–89. http://dx.doi.org/10.1109/ted.2008.916708.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Tavernier, A., L. Favennec, T. Chevolleau, and V. Jousseaume. "Innovative Gap-Fill Strategy for 28 nm Shallow Trench Isolation." ECS Transactions 45, no. 3 (April 27, 2012): 225–32. http://dx.doi.org/10.1149/1.3700888.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Lan, Jin Kun, Ying Lang Wang, Chuan-Pu Liu, Chuen Guang Chao, Chyung Ay, Chi Wen Liu, and Yi Lung Cheng. "Mechanisms of circular defects for shallow trench isolation oxide deposition." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 21, no. 5 (2003): 2098. http://dx.doi.org/10.1116/1.1609475.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Bourdon, Helene, Claire Fenouillet-Béranger, Claire Gallon, Philippe Coronel, and Damien Lenoble. "Selective SiGe Etching Formed by Localized Ge Implantation on SOI." Solid State Phenomena 108-109 (December 2005): 439–44. http://dx.doi.org/10.4028/www.scientific.net/ssp.108-109.439.

Full text

Abstract:

The fully depleted SOI devices present lateral isolation issues due to the shallow trench isolation (STI) process. We propose in this paper to study a new fabrication process for integrating local isolation trenches. Germanium (Ge) implantation is used to create SiGe (Silicon-Germanium) layer on thin SOI (silicon on insulator) that can be selectively etched. The advantage is the capability of implantation to localize the SiGe area on this substrate and to avoid STI process issues. Aggressive dimensions and geometries are studied and resulting material transformation (crystallization and Ge diffusion) are apprehending via SEM (Secondary Electron Microscopy) or AFM (Atomic Force Spectroscopy) to understand the etching kinetics. After optimization, we demonstrate the capability of fabricating localized trenches on SOI without degrading the neighboring Si layer or consuming the thin BOX (buried oxide).

APA, Harvard, Vancouver, ISO, and other styles

29

Gharbi, A., B. Remaki, A. Halimaoui, D. Bensahel, and A. Souifi. "Shallow trench isolation based on selective formation of oxidized porous silicon." Microelectronic Engineering 88, no. 7 (July 2011): 1214–16. http://dx.doi.org/10.1016/j.mee.2011.03.110.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Lee, Woosung, and Hyunsang Hwang. "Hot carrier degradation for narrow width MOSFET with shallow trench isolation." Microelectronics Reliability 40, no. 1 (January 2000): 49–56. http://dx.doi.org/10.1016/s0026-2714(99)00222-x.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Balasubramanian, N., E. Johnson, I. V. Peidous, Shiu Ming-Jr, and R. Sundaresan. "Active corner engineering in the process integration for shallow trench isolation." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 18, no. 2 (2000): 700. http://dx.doi.org/10.1116/1.591262.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Forsberg, Markus, Ted Johansson, Wei Liu, and Manoj Vellaikal. "A Shallow and Deep Trench Isolation Process Module for RF BiCMOS." Journal of The Electrochemical Society 151, no. 12 (2004): G839. http://dx.doi.org/10.1149/1.1811596.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Seung-Ho Pyi, In-Seok Yeo, Dae-Hee Weon, Young-Bog Kim, and Sahng-Kyoo Lee. "Roles of sidewall oxidation in the devices with shallow trench isolation." IEEE Electron Device Letters 20, no. 8 (August 1999): 384–86. http://dx.doi.org/10.1109/55.778149.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Floresca, Herman C., J. G. Wang, M. J. Kim, and J. A. Smythe. "Shallow trench isolation liners and their role in reducing lattice strains." Applied Physics Letters 93, no. 14 (October 6, 2008): 143116. http://dx.doi.org/10.1063/1.2999589.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Nishimura, Hiroshi, Shigeyuki Takagi, Makoto Fujino, and Norio Nishi. "Gap-Fill Process of Shallow Trench Isolation for 0.13 µm Technologies." Japanese Journal of Applied Physics 41, Part 1, No. 5A (May 15, 2002): 2886–93. http://dx.doi.org/10.1143/jjap.41.2886.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Roh, Byung Hyug, Yun Hee Cho, Yu Gyun Shin, Chang Gi Hong, Sang Dong Gwun, Kang Yun Lee, Ho Gyu Kang, Ki Nam Kim, and Jong Woo Park. "Easily Manufacturable Shallow Trench Isolation for Gigabit Dynamic Random Access Memory." Japanese Journal of Applied Physics 35, Part 1, No. 9A (September 15, 1996): 4618–23. http://dx.doi.org/10.1143/jjap.35.4618.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Turowski, M., A. Raman, and R. D. Schrimpf. "Nonuniform total-dose-induced charge distribution in shallow-trench isolation oxides." IEEE Transactions on Nuclear Science 51, no. 6 (December 2004): 3166–71. http://dx.doi.org/10.1109/tns.2004.839201.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Mizukoshi, T., K. Shibusawa, S. Yo, R. Sugie, and T. Ajioka. "An Application of Cathodoluminescence to Optimize the Shallow Trench Isolation Process." IEEE Transactions on Semiconductor Manufacturing 18, no. 4 (November 2005): 546–53. http://dx.doi.org/10.1109/tsm.2005.858497.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Gan, Terence, Tamba Tugbawa, Brian Lee, Duane S. Boning, and Simon Jang. "Modeling of Reverse Tone Etchback Shallow Trench Isolation Chemical Mechanical Polishing." Journal of The Electrochemical Society 148, no. 3 (2001): G159. http://dx.doi.org/10.1149/1.1348266.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Doyle, B. S., R. S. O'Connor, K. R. Mistry, and G. J. Grula. "Comparison of shallow trench and LOCOS isolation for hot-carrier resistance." IEEE Electron Device Letters 12, no. 12 (December 1991): 673–75. http://dx.doi.org/10.1109/55.116951.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

David Theodore, N., Barbara Vasquez, and Peter Fejes. "Microstructural characterization of implanted LOCOS + trench-isolated structures." Proceedings, annual meeting, Electron Microscopy Society of America 49 (August 1991): 888–89. http://dx.doi.org/10.1017/s0424820100088750.

Full text

Abstract:

As device dimensions decrease and circuit densities increase, conventional LOCOS (Local-Oxidation of Silicon) isolation presents a limitation due to lateral encroachment of the isolation-oxide. Variations in LOCOS, including poly-buffered LOCOS have been of interest as means to limit lateral encroachment of the field-oxide into the active device-region. Deep-trench isolation provides a means to support device scaling and in this work is integrated with poly-buffered LOCOS to create self-aligned shallow fieldoxide elements with minimal encroachment into active regions. Use of these technologies however requires an understanding of the behavior of the materials and structures being used and their interactions under different processing conditions. The effect of fabrication-related stresses in the structures is of interest because extended-defects, if formed, could electrically degrade devices.

APA, Harvard, Vancouver, ISO, and other styles

42

Yeon, Chung-Kyu, and Hyuk-Joon You. "Deep-submicron trench profile control using a magnetron enhanced reactive ion etching system for shallow trench isolation." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 16, no. 3 (May 1998): 1502–8. http://dx.doi.org/10.1116/1.581177.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Sato, Michihiro, Tetsuya Ohashi, Keisuke Aikawa, Takuya Maruizumi, and Isao Kitagawa. "Simulation of Dislocation Accumulation in ULSI Cells of Reduced Gate Length." Materials Science Forum 654-656 (June 2010): 1682–85. http://dx.doi.org/10.4028/www.scientific.net/msf.654-656.1682.

Full text

Abstract:

We numerically evaluate the accumulation of dislocations in periodic structure of the shallow trench isolation (STI) type ULSI cells which has generally been adopted as the latest semiconductor device structure. STI type ULSI cells with gate length less than 62 nm and various trench depths are employed and subjected to a temperature drop from the initial value of 1000 °C. Dislocation accumulation is evaluated by a technique of crystal plasticity analysis. Relations between the geometry of the STI type ULSI cells and dislocation accumulation are discussed.

APA, Harvard, Vancouver, ISO, and other styles

44

Ning, Bingxu, Zhengxuan Zhang, Zhangli Liu, Zhiyuan Hu, Ming Chen, Dawei Bi, and Shichang Zou. "Radiation-induced shallow trench isolation leakage in 180-nm flash memory technology." Microelectronics Reliability 52, no. 1 (January 2012): 130–36. http://dx.doi.org/10.1016/j.microrel.2011.07.090.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Peng, Chao, Zhiyuan Hu, Zhengxuan Zhang, Huixiang Huang, Bingxu Ning, and Dawei Bi. "Total ionizing dose effect in 0.2μm PDSOI NMOSFETs with shallow trench isolation." Microelectronics Reliability 54, no. 4 (April 2014): 730–37. http://dx.doi.org/10.1016/j.microrel.2013.12.016.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Xu, Yue, Feng Yan, DunJun Chen, Yi Shi, ZhiGuo Li, Fan Yang, Joshua Wang, et al. "Investigation of impact of shallow trench isolation on SONOS type memory cells." Solid-State Electronics 54, no. 12 (December 2010): 1644–49. http://dx.doi.org/10.1016/j.sse.2010.08.006.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

Oh, Hyuntaek, Jae Hyun Kim, and Jyongsik Jang. "Narrow gap filling in 25nm shallow trench isolation using highly porous organosilica." Thin Solid Films 562 (July 2014): 166–71. http://dx.doi.org/10.1016/j.tsf.2014.04.046.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

Spessot, A., S. Frabboni, R. Balboni, and A. Armigliato. "Strain field reconstruction in shallow trench isolation structures by CBED and LACBED." Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms 253, no. 1-2 (December 2006): 149–53. http://dx.doi.org/10.1016/j.nimb.2006.10.052.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Dombrowski, K. F., B. Dietrich, I. De Wolf, R. Rooyackers, and G. Badenes. "Investigation of stress in shallow trench isolation using UV micro-Raman spectroscopy." Microelectronics Reliability 41, no. 4 (April 2001): 511–15. http://dx.doi.org/10.1016/s0026-2714(00)00260-2.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Niu, G., J. D. Cressler, S. J. Mathew, and D. C. Ahlgren. "Enhanced low-temperature corner current-carrying inherent to shallow trench isolation (STI)." IEEE Electron Device Letters 20, no. 10 (October 1999): 520–22. http://dx.doi.org/10.1109/55.791929.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!