Relevant bibliographies by topics / Si-LDMOS

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Si-LDMOS'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 February 2022

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Journal articles on the topic "Si-LDMOS"

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Tsai, Jhen-Yu, and Hsin-Hui Hu. "Novel Poly-Si SJ-LDMOS for System-on-Panel Applications." IEEE Transactions on Electron Devices 63, no. 6 (June 2016): 2482–87. http://dx.doi.org/10.1109/ted.2016.2554609.

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Tsai, Jhen-Yu, Hsin-Hui Hu, Yung-Chun Wu, Yi-Rue Jhan, Kun-Ming Chen, and Guo-Wei Huang. "A Novel Hybrid Poly-Si Nanowire LDMOS With Extended Drift." IEEE Electron Device Letters 35, no. 3 (March 2014): 366–68. http://dx.doi.org/10.1109/led.2014.2299811.

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Tsai, Jhen-Yu, and Hsin-Hui Hu. "New Super-Junction LDMOS Based on Poly-Si Thin-Film Transistors." IEEE Journal of the Electron Devices Society 4, no. 6 (November 2016): 430–35. http://dx.doi.org/10.1109/jeds.2016.2600253.

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Mohammed, B. A., N. A. Abduljabbar, A. S. Hussaini, R. Abd-Alhameed, S. M. R. Jones, B. A. L. Gwandu, and J. Rodriguez. "A Si-LDMOS Doherty Power Amplifier for 2.620–2.690 GHz Applications." Advanced Science Letters 23, no. 5 (May 1, 2017): 3874–78. http://dx.doi.org/10.1166/asl.2017.8243.

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Chung, Y., and J. Jones. "Si-LDMOS high power amplifier RFIC with integrated analogue pre-distorter." Electronics Letters 44, no. 5 (2008): 361. http://dx.doi.org/10.1049/el:20083085.

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Wang, Yulong, Baoxing Duan, Licheng Sun, Xin Yang, Yunjia Huang, and Yintang Yang. "Breakdown point transfer theory for Si/SiC heterojunction LDMOS with deep drain region." Superlattices and Microstructures 151 (March 2021): 106810. http://dx.doi.org/10.1016/j.spmi.2021.106810.

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Fragoudakis, Roselita, Michael A. Zimmerman, and Anil Saigal. "Application of a Ag Ductile Layer in Minimizing Si Die Stresses in LDMOS Packages." Key Engineering Materials 605 (April 2014): 372–75. http://dx.doi.org/10.4028/www.scientific.net/kem.605.372.

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Lateral Diffused Metal Oxide Semiconductors (LDMOS) normally have a Cu-W flange, whose CTE is matched to Si. Low cost Cu substrate material provides 2X high thermal conductivity, and along with a AuSi eutectic solder is recommended for optimal thermal performance. However, the CTE mismatch between Cu and Si can lead to failure of the semiconductor as a result of die fracture, due to thermal stresses developed during the soldering step of the manufacturing process. Introducing a Ag ductile layer is very important in minimizing such thermal stresses and preventing catastrophic failure of the semiconductor. Ag is a ductile material electroplated on the Cu substrate to absorb stresses developed during manufacturing due to the CTE mismatch between Si and Cu. The Ag layer thickness affects the magnitude of the resulting thermal stresses. This study attempts to measure the yield strength of the Ag layer, and examines the optimal layer thickness to minimize die stresses and prevent failure. The yield stress of the ductile layer deposited on a Cu flange was measured by nanoindentation. The Oliver and Pharr method was applied to obtain modulus of elasticity and yield depth of Ag. A finite element analysis of the package was performed in order to map die stress distribution for various ductile layer thicknesses. The analysis showed that increasing the ductile layer thickness up to 0.01 - 0.02 mm, decreases the Si die stresses.
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Chan, C. W., Yeganeh Bonyadi, Philip A. Mawby, and Peter M. Gammon. "Si/SiC Substrates for the Implementation of Linear-Doped Power LDMOS Studied with Device Simulation." Materials Science Forum 858 (May 2016): 844–47. http://dx.doi.org/10.4028/www.scientific.net/msf.858.844.

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In this study, a 600 V LDMOSFET using a silicon-on-silicon carbide (Si/SiC) substrate is presented. An SOI counterpart is established with a linear-doped drift region the same as that of the Si/SiC transistor. Simulation results show that they perform similar off-state behaviours, both with a significant tunneling leakage emerging above 450 V at 300 K. In the on-state, the proposed structure has advantages over the SOI, namely lower resistance, higher saturation current and improved self-heating effect. Turn-off performance is also enhanced owing to substantial reduction of the drain-substrate capacitance. These are realised by an “IOS” (Insulator on Silicon) setup embedded in the Si/SiC structure.
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Chang, F. L., M. J. Lin, C. W. Liaw, and H. C. Cheng. "Low-Temperature Power Device: A New Poly-Si High-Voltage LDMOS With Excimer Laser Crystallization." IEEE Electron Device Letters 25, no. 8 (August 2004): 547–49. http://dx.doi.org/10.1109/led.2004.831590.

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Gammon, P. M., C. W. Chan, and P. A. Mawby. "Simulation of a new hybrid Si/SiC power device for harsh environment applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, HiTEN (January 1, 2015): 000190–94. http://dx.doi.org/10.4071/hiten-session5-paper5_5.

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A new power device structure is proposed, conceived to operate in a high temperature, harsh environment, for example within a motor drive application down hole, as an inverter in the engine bay of an electric car, or as a solar inverter in space. The lateral silicon power device resembles a laterally diffused MOSFET (LDMOS), such as those implemented within silicon on insulator (SOI) substrates. However, unlike SOI, the Si thin film has been transferred directly onto a semi-insulating 6H silicon carbide (6H-SiC) substrate via a wafer bonding process. Thermal simulations of the hybrid Si/SiC substrate have shown that the high thermal conductivity of the SiC will have a junction-to-case temperature approximately 4 times less that an equivalent SOI device, reducing the effects of self-heating. Electrical simulations of a 600 V power device, implemented entirely with the silicon thin film, suggest that it will retain the ability of SOI to minimise leakage at high temperature, but does so with 50% less conduction losses.
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Dissertations / Theses on the topic "Si-LDMOS"

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Lotfi, Sara. "Design and Characterization of RF-LDMOS Transistors and Si-on-SiC Hybrid Substrates." Doctoral thesis, Uppsala universitet, Fasta tillståndets elektronik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-215390.

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With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.
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Doudorov, Grigori. "Evaluation of Si-LDMOS transistors for RF Power Amplifier in 2-6 GHz frequency range." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1837.

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In this thesis the models of Si-LDMOS transistors have been investigated with Agilent EEsof ADS version 2002a for operation in the 2-6 GHz frequency range. The first one is the Motorola’s (MRF21010) model based on a 30 mm prototype of a Si-LDMOS transistor. The second one is a model based on a 1 mm prototype of Si-LDMOS transistor developed at Chalmers University. Large-signal simulations of Chalmers’ model have demonstrated results, which lead to the conclusion that,this model cannot be efficiently utilised for design for a PA in the 2-6 GHz frequency range. However, additional simulations with reduced Rd (drain losses) show the deep impact of this parameter on the main properties of the designed PA. Hence, it is important to take it into account during new processes of Si-LDMOS as well as to improve the CAD model. The final conclusion regarding Si-LDMOS cannot be made just based on these simulation results, since they are not in accordance with the published ones. The next step should be aimed at improving the model and further investigation of Si-LDMOS to prove their ability to operate in the 2-6 GHz frequency range.

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Syed, Asad Abbas. "Large Signal Physical Simulations of Si LD-MOS transistor for RF application." Thesis, Linköping University, The Department of Physics, Chemistry and Biology, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2627.

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The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz.

In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current

The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.

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Allam-Ouyahia, Samia. "Amplificateurs de puissance à très haut rendement, pour les systèmes radar basés sur les technologies LDMOS Si et HEMT Gan." Cergy-Pontoise, 2006. http://www.theses.fr/2006CERG0331.

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L'objectif de ce travail est d'évaluer de nouvelles technologies de puissance pour les émetteurs des systèmes radar de Thalès Air Defence. Le problème majeur dans les amplificateurs de puissance dans les modules émission réception est l'évacuation de la chaleur produite. Pour résoudre cette problématique nous avons évalué les potentialités de chaque technologie ainsi que l'optimisation de leurs rendements. Notamment nous avons cherché à évaluer les performances qui peuvent être obtenues sur les deux technologies considérées, à savoir le GaN et Silicium LDMOS. Concernant la technologie LDMOS, nous avons fait la conception et la réalisation de deux amplificateurs en bande L. Les mesures du premier amplificateur montrent un PAE de 71. 8% associé à une puissance de sortie de 13. 5W à 1 GHz. Dans le deuxième amplificateur, nous nous sommes intéressés à l'élargissement de la bande à 15% (bande radar). La solution que nous avons proposé a permis la réalisation d'un amplificateur qui fournit une puissance de sortie supérieure à 10W associée à un PAE supérieur à 60% dans toute la bande de fréquence
The objective of this work is to evaluate power technologies and high efficiency classes (F and inverse F ) for L-band TIR module in phase array radar of Thalès Air Defence. The rapid development of active antennas systems has put power amplifier (PA) efficiency in focus. The combination of high PAE and high power density is very important in new radar generations. We evaluated the performances of two technologies considered HEMT GaN and Silicon LDMOS. For GaN, we evaluated the performances of HEMT AIGaN/GaN by multiharmonic simulations. A 71% PAE is achieved for class F and 74% for inverse class F for output power of 4W. For LDMOS technology, two inverse Class F power amplifiers are designed. The first amplifier allows evaluation of the LDMOS potential for inverse Class F operation. It demonstrates 73. 7% drain e_ciency, 13. 2W output power and 16dB power gain at 1 GHz and for 2dB gain compression. The second one was designed with wider bandwidth as additional criterion. Measurements show high output power and drain efficiency over 170MHz bandwidth (0. 9 to 1. 07 GHz). These performances, compared to reported results for single stage inverse Class F power amplifiers are in the state of the art
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BROCH, JEAN-FRANCOIS. "Conception d'amplificateurs de puissance large bande uhf a base de mesfet en carbure de silicium. Comparaison des performances avec la technologie si - ldmos." Paris 11, 1998. http://www.theses.fr/1998PA112389.

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L'objet de cette these est d'evaluer les potentialites en amplification de puissance des transistors a effet de champ en carbure de silicium (sic). La caracterisation des transistors mesfet en carbure de silicium de thomson - lcr confirme les performances interessantes publiees dans la litterature. Elle demontre pour le sic : une densite de puissance elevee et des impedences qui facilitent l'adaptation. Le developpement d'une methodologie s'inspirant des techniques de mesures existantes (load-pull) et des travaux theoriques sur la conception de circuits d'adaptation (methode analytique), a permis la realisation d'amplificateurs si et sic large bande en classe a. Les mesures realisees sur ces amplificateurs ont montre les performances interessantes du sic pour l'amplification large bande de puissance : une puissance de 10 w et un gain de 13 db sur la bande uhf. Elles montrent aussi une grande marge d'evolution comparee au silicium.
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Chetibi-RIah, Mouna. "Caractérisation et modélisation électrothermique non linéaire des transistors hyperfréquences de puissance « RF Si-LDMOSFETs pour l’étude de la fiabilité." Rouen, 2009. http://www.theses.fr/2009ROUES015.

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Ce travail traite de la modélisation électrothermique du transistor LDMOS de puissance pour l’étude de sa fiabilité dans une application Radar. Dans une première partie, nous avons présenté les particularités des transistors MOS, et en particulier le LDMOS, par rapport aux transistors bipolaires. Nous avons étudié aussi l’influence de l’élévation de la température dans les composants semiconducteurs sur leurs grandeurs physiques pertinentes. Enfin, nous avons exposé les notions de base de la fiabilité des transistors de puissance et nous avons abordé les modes et les mécanismes de défaillance ainsi que les principales lois d’accélération de défaillance (température, densité de courant, injection des porteurs chauds). Dans une seconde partie, l’ensemble du processus d’extraction du modèle électrothermique d’un LDMOS est présenté en détails. Cette étude a été basée sur le MET modèle considéré comme le plus approprié pour les transistor RF LDMOS de puissance. Le banc de fiabilité utilisé pour effectuer les tests de vieillissement accélérés a été décrit au troisième chapitre. Le but recherché concerne la compréhension de la dégradation la fiabilité de ce type de composant en mode pulsé. Ainsi, toutes les dérives des paramètres électriques et RF après un vieillissement accélérés sont étudiées et discutées
This work deals with electrothermal modelling of LDMOS power transistor for the study of reliability in radar applications. In a first part, we presented the characteristics of MOS transistors, and particularly the LDMOS, compared to bipolar transistors. We studied the influence of the temperature rise in semiconductor components on their relevant physical quantities. Finally, we explained the basics of the reliability of power transistors and we discussed ways and mechanisms of failure and the main laws of acceleration of failure (temperature, current density, injection of hot carriers). In a second part, the whole process of extraction of electrothermal model of an LDMOS is presented in detail. This study was based on the MET model deemed most appropriate for RF LDMOS power transistor. The reliability bench used to perform accelerated ageing tests has been described in chapter three. The goal is the understanding of the degradation of the reliability of such components in pulsed mode. Thus, all the electrical and RF parameters drifts after accelerated ageing tests have been studied and discussed
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Book chapters on the topic "Si-LDMOS"

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Mohammed, B. A., N. A. Abduljabbar, M. A. G. Al-Sadoon, K. Hameed, A. S. Hussaini, S. M. R. Jones, F. Elmegri, R. W. Clark, and R. Abd-Alhameed. "A 15.5 W Si-LDMOS Balanced Power Amplifier with 53% Ultimate PAE for High Speed LTE." In Wireless and Satellite Systems, 193–201. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-53850-1_19.

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Conference papers on the topic "Si-LDMOS"

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Rakluea, Paitoon, and Jintana Nakasuwan. "A 3.5 GHz WiMAX power amplifier using Si-LDMOS." In 2008 International Conference on Control, Automation and Systems (ICCAS). IEEE, 2008. http://dx.doi.org/10.1109/iccas.2008.4694478.

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Everett, John P., Michael J. Kearney, Hernan A. Rueda, Eric M. Johnson, Peter H. Aaen, John Wood, and Christopher M. Snowden. "Fast physical models for Si LDMOS power transistor characterization." In 2011 IEEE/MTT-S International Microwave Symposium - MTT 2011. IEEE, 2011. http://dx.doi.org/10.1109/mwsym.2011.5972839.

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Bathich, Khaled, Henrique Portela, and Georg Boeck. "A high efficiency Si LDMOS Doherty power amplifier with optimized linearity." In 2009 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (IMOC). IEEE, 2009. http://dx.doi.org/10.1109/imoc.2009.5427635.

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Saavedra-Gomez, H. J., J. L. Del Valle, J. R. Loo-Yau, and A. Garcia-Osorio. "A 4W UHF Si-LDMOS class AB PA for RFID applications." In 2008 5th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE). IEEE, 2008. http://dx.doi.org/10.1109/iceee.2008.4723437.

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Nunes, Luis C., Pedro M. Cabral, and Jose C. Pedro. "AM/PM distortion physical origins in Si LDMOS Doherty power amplifiers." In 2016 IEEE/MTT-S International Microwave Symposium (IMS). IEEE, 2016. http://dx.doi.org/10.1109/mwsym.2016.7539986.

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Sorge, R., A. Fischer, A. Mai, P. Schley, J. Schmidt, Ch Wipf, R. Pliquett, and R. Barth. "Integrated Si-LDMOS transistors for 11 GHz X-Band power amplifier applications." In 2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM. IEEE, 2010. http://dx.doi.org/10.1109/bipol.2010.5667935.

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Staudinger, Joseph, Paul Hart, and Damon Holmes. "Behavioral modeling of Si LDMOS pre-matched devices with application to Doherty power amplifiers." In 2012 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR). IEEE, 2012. http://dx.doi.org/10.1109/pawr.2012.6174935.

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Arnous, MHD Tareq, and Georg Boeck. "4 Watt, 45% bandwidth Si-LDMOS high linearity power amplifier for modern wireless communications systems." In 2012 2nd International Conference on Advances in Computational Tools for Engineering Applications (ACTEA). IEEE, 2012. http://dx.doi.org/10.1109/ictea.2012.6462846.

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Burns, Christopher T., Allen Chang, and David W. Runton. "A 900 MHz, 500 W Doherty Power Amplifier Using Optimized Output Matched Si LDMOS Power Transistors." In 2007 IEEE/MTT-S International Microwave Symposium. IEEE, 2007. http://dx.doi.org/10.1109/mwsym.2007.380577.

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Gruner, D., R. Sorge, O. Bengtsson, A. Z. Markos, and G. Boeck. "A 1 W Si-LDMOS power amplifier with 40 % drain efficiency for 6 GHz WLAN applications." In 2010 IEEE/MTT-S International Microwave Symposium - MTT 2010. IEEE, 2010. http://dx.doi.org/10.1109/mwsym.2010.5514799.

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You might also be interested in the extended bibliographies on the topic 'Si-LDMOS' for particular source types:
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