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Journal articles on the topic 'Si-LDMOS'

Author: Grafiati

Published: 4 June 2021

Last updated: 16 February 2022

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1

Tsai, Jhen-Yu, and Hsin-Hui Hu. "Novel Poly-Si SJ-LDMOS for System-on-Panel Applications." IEEE Transactions on Electron Devices 63, no. 6 (June 2016): 2482–87. http://dx.doi.org/10.1109/ted.2016.2554609.

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2

Tsai, Jhen-Yu, Hsin-Hui Hu, Yung-Chun Wu, Yi-Rue Jhan, Kun-Ming Chen, and Guo-Wei Huang. "A Novel Hybrid Poly-Si Nanowire LDMOS With Extended Drift." IEEE Electron Device Letters 35, no. 3 (March 2014): 366–68. http://dx.doi.org/10.1109/led.2014.2299811.

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3

Tsai, Jhen-Yu, and Hsin-Hui Hu. "New Super-Junction LDMOS Based on Poly-Si Thin-Film Transistors." IEEE Journal of the Electron Devices Society 4, no. 6 (November 2016): 430–35. http://dx.doi.org/10.1109/jeds.2016.2600253.

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4

Mohammed, B. A., N. A. Abduljabbar, A. S. Hussaini, R. Abd-Alhameed, S. M. R. Jones, B. A. L. Gwandu, and J. Rodriguez. "A Si-LDMOS Doherty Power Amplifier for 2.620–2.690 GHz Applications." Advanced Science Letters 23, no. 5 (May 1, 2017): 3874–78. http://dx.doi.org/10.1166/asl.2017.8243.

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5

Chung, Y., and J. Jones. "Si-LDMOS high power amplifier RFIC with integrated analogue pre-distorter." Electronics Letters 44, no. 5 (2008): 361. http://dx.doi.org/10.1049/el:20083085.

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6

Wang, Yulong, Baoxing Duan, Licheng Sun, Xin Yang, Yunjia Huang, and Yintang Yang. "Breakdown point transfer theory for Si/SiC heterojunction LDMOS with deep drain region." Superlattices and Microstructures 151 (March 2021): 106810. http://dx.doi.org/10.1016/j.spmi.2021.106810.

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7

Fragoudakis, Roselita, Michael A. Zimmerman, and Anil Saigal. "Application of a Ag Ductile Layer in Minimizing Si Die Stresses in LDMOS Packages." Key Engineering Materials 605 (April 2014): 372–75. http://dx.doi.org/10.4028/www.scientific.net/kem.605.372.

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Lateral Diffused Metal Oxide Semiconductors (LDMOS) normally have a Cu-W flange, whose CTE is matched to Si. Low cost Cu substrate material provides 2X high thermal conductivity, and along with a AuSi eutectic solder is recommended for optimal thermal performance. However, the CTE mismatch between Cu and Si can lead to failure of the semiconductor as a result of die fracture, due to thermal stresses developed during the soldering step of the manufacturing process. Introducing a Ag ductile layer is very important in minimizing such thermal stresses and preventing catastrophic failure of the semiconductor. Ag is a ductile material electroplated on the Cu substrate to absorb stresses developed during manufacturing due to the CTE mismatch between Si and Cu. The Ag layer thickness affects the magnitude of the resulting thermal stresses. This study attempts to measure the yield strength of the Ag layer, and examines the optimal layer thickness to minimize die stresses and prevent failure. The yield stress of the ductile layer deposited on a Cu flange was measured by nanoindentation. The Oliver and Pharr method was applied to obtain modulus of elasticity and yield depth of Ag. A finite element analysis of the package was performed in order to map die stress distribution for various ductile layer thicknesses. The analysis showed that increasing the ductile layer thickness up to 0.01 - 0.02 mm, decreases the Si die stresses.

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8

Chan, C. W., Yeganeh Bonyadi, Philip A. Mawby, and Peter M. Gammon. "Si/SiC Substrates for the Implementation of Linear-Doped Power LDMOS Studied with Device Simulation." Materials Science Forum 858 (May 2016): 844–47. http://dx.doi.org/10.4028/www.scientific.net/msf.858.844.

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In this study, a 600 V LDMOSFET using a silicon-on-silicon carbide (Si/SiC) substrate is presented. An SOI counterpart is established with a linear-doped drift region the same as that of the Si/SiC transistor. Simulation results show that they perform similar off-state behaviours, both with a significant tunneling leakage emerging above 450 V at 300 K. In the on-state, the proposed structure has advantages over the SOI, namely lower resistance, higher saturation current and improved self-heating effect. Turn-off performance is also enhanced owing to substantial reduction of the drain-substrate capacitance. These are realised by an “IOS” (Insulator on Silicon) setup embedded in the Si/SiC structure.

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9

Chang, F. L., M. J. Lin, C. W. Liaw, and H. C. Cheng. "Low-Temperature Power Device: A New Poly-Si High-Voltage LDMOS With Excimer Laser Crystallization." IEEE Electron Device Letters 25, no. 8 (August 2004): 547–49. http://dx.doi.org/10.1109/led.2004.831590.

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10

Gammon, P. M., C. W. Chan, and P. A. Mawby. "Simulation of a new hybrid Si/SiC power device for harsh environment applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, HiTEN (January 1, 2015): 000190–94. http://dx.doi.org/10.4071/hiten-session5-paper5_5.

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A new power device structure is proposed, conceived to operate in a high temperature, harsh environment, for example within a motor drive application down hole, as an inverter in the engine bay of an electric car, or as a solar inverter in space. The lateral silicon power device resembles a laterally diffused MOSFET (LDMOS), such as those implemented within silicon on insulator (SOI) substrates. However, unlike SOI, the Si thin film has been transferred directly onto a semi-insulating 6H silicon carbide (6H-SiC) substrate via a wafer bonding process. Thermal simulations of the hybrid Si/SiC substrate have shown that the high thermal conductivity of the SiC will have a junction-to-case temperature approximately 4 times less that an equivalent SOI device, reducing the effects of self-heating. Electrical simulations of a 600 V power device, implemented entirely with the silicon thin film, suggest that it will retain the ability of SOI to minimise leakage at high temperature, but does so with 50% less conduction losses.

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11

Li, Qi, Leilei Yuan, Fabi Zhang, Haiou Li, Gongli Xiao, Yonghe Chen, Tangyou Sun, Xingpeng Liu, and Tao Fu. "Novel SiC/Si heterojunction LDMOS with electric field modulation effect by reversed L-shaped field plate." Results in Physics 16 (March 2020): 102837. http://dx.doi.org/10.1016/j.rinp.2019.102837.

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12

Lee, Yong-Sub, Mun-Woo Lee, and Yoon-Ha Jeong. "Experimental analysis of GaN HEMT and Si LDMOS in analog predistortion power amplifiers for WCDMA applications." Microwave and Optical Technology Letters 50, no. 2 (February 2008): 393–96. http://dx.doi.org/10.1002/mop.23134.

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13

Mohammed, B., A. Hussaini, R. Abd-Alhameed, I. Danjuma, A. Asharaa, I. Elfergani, and J. Rodriguez. "Towards a 15.5W Si-LDMOS Energy Efficient Balanced RF Power Amplifier for 5G-LTE Multi-carrier Applications." EAI Endorsed Transactions on Creative Technologies 5, no. 15 (April 10, 2018): 155858. http://dx.doi.org/10.4108/eai.10-4-2018.155858.

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14

Sheikh, A., C. Roff, J. Benedikt, P. J. Tasker, B. Noori, J. Wood, and P. H. Aaen. "Peak Class F and Inverse Class F Drain Efficiencies Using Si LDMOS in a Limited Bandwidth Design." IEEE Microwave and Wireless Components Letters 19, no. 7 (July 2009): 473–75. http://dx.doi.org/10.1109/lmwc.2009.2022138.

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15

Yintang, Yang, and Duan Baoxing. "The application of the electric field modulation and charge shielding effects to the high-voltage Si LDMOS." IETE Technical Review 29, no. 4 (2012): 276. http://dx.doi.org/10.4103/0256-4602.101307.

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16

Nunes, Luis Cotimos, Pedro M. Cabral, and Jose C. Pedro. "AM/AM and AM/PM Distortion Generation Mechanisms in Si LDMOS and GaN HEMT Based RF Power Amplifiers." IEEE Transactions on Microwave Theory and Techniques 62, no. 4 (April 2014): 799–809. http://dx.doi.org/10.1109/tmtt.2014.2305806.

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17

Chung, Younkyu. "Effect of gate-to-source capacitance of high-power Si-LDMOS FET on the asymmetrical intermodulation and modulation bandwidth of base-station amplifiers." Microwave and Optical Technology Letters 51, no. 10 (July 23, 2009): 2448–51. http://dx.doi.org/10.1002/mop.24597.

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18

Sharma, Prateek, Stanislav Tyaginov, Markus Jech, Yannick Wimmer, Florian Rudolf, Hubert Enichlmair, Jong-Mun Park, Hajdin Ceric, and Tibor Grasser. "The role of cold carriers and the multiple-carrier process of Si–H bond dissociation for hot-carrier degradation in n- and p-channel LDMOS devices." Solid-State Electronics 115 (January 2016): 185–91. http://dx.doi.org/10.1016/j.sse.2015.08.014.

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19

Johnson, Wayne, Sameer Singhal, Allen Hanson, Robert Therrien, Apurva Chaudhari, Walter Nagy, Pradeep Rajagopal, et al. "GaN-on-Si HEMTs: From Device Technology to Product Insertion." MRS Proceedings 1068 (2008). http://dx.doi.org/10.1557/proc-1068-c04-01.

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ABSTRACTIn the last decade, GaN-on-Si has progressed from fundamental crystal growth studies to product realization and reliability demonstration. GaN-on-Si HEMTs addressing cellular, WiMAX, and broadband RF applications are now commercially available and offer GaN performance attributes in a cost-competitive platform. This presentation will briefly describe the underlying GaN-on-Si material, process, and packaging technology, then focus primarily on performance of these products in both commercial and military applications.All Nitronex NRF1 GaN-on-Si products are grown by MOCVD on 100 mm float-zone Si (111) substrates. A proprietary, strain-compensating (Al,Ga)N transition layer and an amorphous SixAl1-xNy nucleation layer are employed to accommodate lattice and thermal expansion mismatch between the substrate and the epilayers. The wafer fabrication process employs Ti/Al-based ohmic contacts, ion implant device isolation, 0.5 um dielectrically-defined gates, gold airbridge interconnects, and through-wafer source vias. Typical inline DC parametrics include 2DEG sheet resistance of 490 ohms/sq., on-resistance of 3 ohm-mm, peak drain current density of 830 mA/mm, and breakdown voltage of >100V. Packaging solutions include traditional LDMOS-style air cavity outlines with thermally-enhanced flange materials and low-cost plastic SOIC.A family of devices addressing emerging OFDM-based applications such as WiMAX has been developed. WiMAX amplifiers require several watts of linear output power with frequency band allocations ranging from 2.3 to 5.8 GHz and instantaneous bandwidth up to ∼15%. Translated to the transistor level, this implies simultaneous high frequency and high voltage capability – attributes well-suited to the inherent advantages of GaN-based devices. The flagship product in this family is NPT25100, delivering 125W of peak envelope power at 2.5 GHz. Under 2.5 GHz single-carrier OFDM modulation and 10 MHz channel bandwidth, this device produces 10W linear power at 2.0% EVM with 16.5dB associated gain and 26% drain efficiency. The excellent bandwidth of NRF1 devices enables the same device to operate at cellular frequencies from 2.11 - 2.17 GHz, producing >20W average power at an adjacent channel power ratio of -35 dBc.Primary military insertion opportunities include communications (e.g., JTRS - Joint Tactical Radio System) and electronic warfare (e.g., jammers). For EW applications, broadband operation reduces system-level component count and decreases weight / footprint. A family of 48V GaN-on-Si broadband HEMTs has been developed to deliver power levels from 40W - 180W in a compact package. In the highest power case, packaged “power density” (defined as peak output power divided by package volume) reaches ∼650 W/cm3. These power levels – in an outline suitable for highly portable systems – enable improved communications transmit distance and extend the umbrella size of electronic protection units.

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