Relevant bibliographies by topics / SiGe source and drain

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'SiGe source and drain'

Author: Grafiati
Published: 4 June 2021
Last updated: 4 February 2022

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Journal articles on the topic "SiGe source and drain"

1

Lauwers, A., M. J. H. van Dal, P. Verheyen, et al. "Study of silicide contacts to SiGe source/drain." Microelectronic Engineering 83, no. 11-12 (2006): 2268–71. http://dx.doi.org/10.1016/j.mee.2006.10.017.

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Claeys, C., M. Bargallo Gonzalez, G. Eneman, et al. "Leakage Current Control in Recessed SiGe Source/Drain Junctions." Journal of The Electrochemical Society 154, no. 9 (2007): H814. http://dx.doi.org/10.1149/1.2756370.

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Wang, You, Yu Mao, Qizheng Ji, Ming Yang, Zhaonian Yang, and Hai Lin. "Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET." Electronics 10, no. 4 (2021): 454. http://dx.doi.org/10.3390/electronics10040454.

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Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure curre
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Zhong, Min, Yu Hang Zhao, Shou Mian Chen, Ming Li, Shao Hai Zeng, and Wei Zhang. "TCAD Study of the Raised SiGe Source/Drain in 40nm PMOS." Key Engineering Materials 645-646 (May 2015): 70–74. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.70.

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An embedded SiGe layer was applied in the source/drain areas (S/D) of a field-effect transistor to boost the performance in the p channels. Raised SiGe S/D plays a critical role in strain engineering. In this study, the relationship between the SiGe overfilling and the enhancement of channel stress was investigated. Systematic technology computer aided design (TCAD) simulations of the SiGe overfill height in a 40 nm PMOS were performed. The simulation results indicate that a moderate SiGe overfilling induces the highest stress in the channel. Corresponding epitaxial growth experiments were don
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Miyanami, Yuki, Kazunobu Ota, Takashi Shinyama, et al. "Novel Process Development for Bilayer Embedded SiGe Source/Drain Formation." ECS Transactions 3, no. 7 (2019): 501–8. http://dx.doi.org/10.1149/1.2355847.

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Yang, Zhaonian, Yuan Yang, Ningmei Yu, and Juin Liou. "Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET." Micromachines 9, no. 12 (2018): 657. http://dx.doi.org/10.3390/mi9120657.

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Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with SiGe source/drain (S/D) regions is proposed, and its ESD characteristics are evaluated using technology computer aided design (TCAD) simulations. Under a transmission line pulsing (TLP) stressing condition, the triggering voltage of the SiGe S/D TFET is reduced by 35% and the failure cur
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Zhong, Min, Shou Mian Chen, and David Wei Zhang. "Investigation of In Situ Boron-Doping in SiGe Source/Drain Layer Growth for PMOS Devices." Journal of Nanomaterials 2015 (2015): 1–6. http://dx.doi.org/10.1155/2015/537696.

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Embedded SiGe (eSiGe) source/drain (S/D) was studied to enhance PMOS performance. Detailed investigations concerning the effect of GeH4and B2H6gas flow rate on the resultant Boron-doping of the SiGe layer (on a 40 nm patterned wafer) were carried out. Various SiGeB epitaxial growth experiments were realized under systematically varying experimental conditions. Key structural and chemical characteristics of the SiGeB layers were investigated using Secondary Ion Mass Spectroscopy (SIMS), nanobeam diffraction mode (NBD), and Transmission Electron Microscopy (TEM) itself. Furthermore,Ion/Ioffperfo
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Qin, Changliang, Huaxiang Yin, Guilei Wang, et al. "Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs." Microelectronic Engineering 181 (September 2017): 22–28. http://dx.doi.org/10.1016/j.mee.2017.07.001.

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Raghunathan, Shyam, Tejas Krishnamohan, and Krishna C. Saraswat. "Novel SiGe Source/Drain for Reduced Parasitic Resistance in Ge NMOS." ECS Transactions 33, no. 6 (2019): 871–76. http://dx.doi.org/10.1149/1.3487617.

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Qi, Y., J. Peng, H. C. Lo, et al. "In-Situ Boron Doped SiGe Epitaxy Optimization for FinFET Source/Drain." ECS Transactions 75, no. 8 (2016): 265–72. http://dx.doi.org/10.1149/07508.0265ecst.

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Dissertations / Theses on the topic "SiGe source and drain"

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Isheden, Christian. "Source and drain engineering in SiGe-based pMOS transistors." Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-96.

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Christensen, Björn. "Fabrication and characterization of gate last Si MOSFETs with SiGe source and drain." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-211547.

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The continuous evolution of digital technology we enjoy today is the result of ever shrinking, faster and cheaper transistors that make up the ubiquitous integrated circuits of our devices. Over the decades, the industry has gone from purely geometrical scaling to innovative solutions like high-k dielectrics combined with metal gates and FinFETs. A possible future is the use of high mobility materials such as Germanium for the active areas of a transistor instead of Silicon. As a step towards building devices on Ge, we characterize a gate last process with epitaxial deposition of Si0.75Ge0.25
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Daubriac, Richard. "Caractérisation de techniques d'implantations ioniques alternatives pour l'optimisation du module source-drain de la technologie FDSOI 28nm." Thesis, Toulouse, INSA, 2018. http://www.theses.fr/2018ISAT0031/document.

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Durant ces dernières années, l’apparition de nouvelles architectures (FDSOI, FinFETs ou NW-FETs) et l’utilisation de nouveaux matériaux (notamment SiGe) ont permis de repousser les limites des performances des dispositifs MOS et de contourner l’effet canal court inhérent à la miniaturisation des composants. Cependant, pour toutes ces nouvelles architectures, la résistance de contact se dégrade au fil des nœuds technologiques. Celle-ci dépend fortement de deux paramètres physiques : la concentration de dopants actifs proches de la surface du semi-conducteur et de la hauteur de barrière Schottky
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Ogier, Jean-Luc. "Optimisation de structures et de technologies pour la réalisation de drain-source de transistors MOS submicroniques." Université Joseph Fourier (Grenoble), 1993. http://www.theses.fr/1993GRE10167.

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Afin de reduire les effets de canaux courts et de porteurs chauds, nous avons etudie differentes solutions technologiques concernant les drain/source de transistors metal oxyde silicium (mos) submicroniques. Cette etude a ete realisee dans le cadre de filieres cmos (mos complementaires) submicroniques (0. 7-0. 5-0. 35 micron). Concernant le transistor nmos, notre etude vise a reduire les phenomenes de degradations par porteurs chauds qui affectent la fiabilite du dispositif. Nous nous interessons uniquement a la partie faiblement dopee du drain (ldd). Nous presentons dans un premier temps les
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Zhang, Zhikuan. "Source/drain engineering for extremely scaled MOSFETs /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20ZHANG.

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Hakanen, Jani. "Modeling of nanostructures with complex source and drain." Thesis, Linköping University, The Department of Physics, Chemistry and Biology, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4285.

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<p>In this thesis we report on calculations for open quantum mechanical and certain microwave systems. The models refer to a quantum point contact and an electron cavity. We model this open system with an imaginary potential as source and drain, and use the finite difference method to make our calculations. We report on general features of the model we have found, and compare our calculations with measurements made on microwave cavities.</p>
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Waite, Andrew Michael. "Elevated source/drain MOSFETs for deep submicron VLSI." Thesis, University of Southampton, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299702.

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Zhang, Zhikuan. "A novel MOSFET's with source/drain on insulator /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20ZHANG.

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Luo, Jun. "Integration of metallic source/drain contacts in MOSFET technology." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-13136.

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The continuous and aggressive downscaling of conventional CMOS devices has been driving the vast growth of ICs over the last few decades. As the CMOS downscaling approaches the fundamental limits, novel device architectures such as metallic source/drain Schottky barrier MOSFET (SB-MOSFET) and SB-FinFET are probably needed to further push the ultimate downscaling. The ultimate goal of this thesis is to integrate metallic Ni1-xPtx silicide (x=0~1) source/drain into SB-MOSFET and SB-FinFET, with an emphasis on both material and processing issues related to the integration of Ni1-xPtx silicides to
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Gudmundsson, Valur. "Fabrication, characterization, and modeling of metallic source/drain MOSFETs." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-49184.

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As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant as
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Books on the topic "SiGe source and drain"

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Wang, Guilei. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6.

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Li, Zhiqiang. The Source/Drain Engineering of Nanoscale Germanium-based MOS Devices. Springer Berlin Heidelberg, 2016. http://dx.doi.org/10.1007/978-3-662-49683-1.

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International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS (3rd 2007 Chicago, Ill.). Advanced gate stack, source/drain and channel engineering for Si-based CMOS 3: New materials, processes and equipment. Edited by Öztürk Mehmet C, Electrochemical Society. Electronics and Photonics Division., Electrochemical Society. Dielectric Science and Technology Division., Electrochemical Society. High Temperature Materials Division., and Electrochemical Society Meeting. Electrochemical Society, 2007.

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International, Symposium on Advanced Gate Stack Source/Drain and Channel Engineering for Si-based CMOS (2nd 2006 Cancún Mexico). Advanced gate stack, source/drain, and channel engineering for Si-based CMOS 2: New materials, processes and equipment. Electrochemical Society, 2006.

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International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS (3rd 2007 Chicago, Ill.). Advanced gate stack, source/drain and channel engineering for Si-based CMOS 3: New materials, processes and equipment. Edited by Öztürk Mehmet C, Electrochemical Society. Electronics and Photonics Division., Electrochemical Society. Dielectric Science and Technology Division., Electrochemical Society. High Temperature Materials Division., and Electrochemical Society Meeting. Electrochemical Society, 2007.

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Wang, Guilei. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer, 2019.

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Li, Zhiqiang. The Source/Drain Engineering of Nanoscale Germanium-based MOS Devices. Springer, 2018.

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Maguire, Paul Damien Mary. The characteristics of field effect transistors with Schottky barrier source and drain electrodes. 1986.

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(Editor), Evgeni P. Gusev, Lih-Juann Chen (Editor), Hiroshi Iwai (Editor), et al., eds. Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment 2005: Proceedings Of The International Symposium. Electrochemical Society, 2005.

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Pinho, Patricia de Santana. Mapping Diaspora. University of North Carolina Press, 2018. http://dx.doi.org/10.5149/northcarolina/9781469645322.001.0001.

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Brazil, like some countries in Africa, has become a major destination for African American tourists seeking the cultural roots of the black Atlantic diaspora. Drawing on over a decade of ethnographic research as well as textual, visual, and archival sources, Patricia de Santana Pinho investigates African American roots tourism, a complex, poignant kind of travel that provides profound personal and collective meaning for those searching for black identity and heritage. It also provides, as Pinho’s interviews with Brazilian tour guides, state officials, and Afro-Brazilian activists reveal, econo
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Book chapters on the topic "SiGe source and drain"

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Mohapatra, E., T. P. Dash, J. Jena, S. Das, J. Nanda, and C. K. Maiti. "Performance Analysis of Si-Channel Nanosheet FETs with Strained SiGe Source/Drain Stressors." In Advances in Electrical Control and Signal Systems. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-5262-5_23.

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Wang, Guilei. "Epitaxial Growth of SiGe Thin Films." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_3.

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Wang, Guilei. "SiGe S/D Integration and Device Verification." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_4.

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Wang, Guilei. "Pattern Dependency of SiGe Layers Selective Epitaxy Growth." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_5.

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Thakur, Anchal, and Rohit Dhiman. "A Threshold Voltage Model for SiGe Source/Drain Silicon-Nanotube-Based Junctionless Field-Effect Transistor." In Energy Systems in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7937-0_6.

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Wang, Guilei. "Introduction." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_1.

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Wang, Guilei. "Strained Silicon Technology." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_2.

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Wang, Guilei. "Conclusions and Prospects." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_6.

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Patel, Jyoti, Priyanka Suman, Alemienla Lemtur, and Dheeraj Sharma. "Performance Booster Electrical Drain SiGe Nanowire TFET (EDD-SiGe-NW-TFET) with DC Analysis and Optimization." In Information and Communication Technology for Intelligent Systems. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1747-7_55.

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Hellings, Geert, and Kristin De Meyer. "Source/Drain Junctions in Germanium: Experimental Investigation." In High Mobility and Quantum Well Transistors. Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6340-1_2.

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Conference papers on the topic "SiGe source and drain"

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LEE, Doohwan, Masao SAKURABA, Junichi MUROTA та Toshiaki TSUCHIYA. "0.1 μm pMOSFETs with SiGe-Channel and B-Doped SiGe Source/Drain Layers". У 2002 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2002. http://dx.doi.org/10.7567/ssdm.2002.c-9-1.

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Radamson, H. H., J. Hallstedt, and M. Ostling. "Integration of Selective SiGe Epitaxy for Source/Drain Application in MOSFETs." In 2006 International SiGe Technology and Device Meeting. IEEE, 2006. http://dx.doi.org/10.1109/istdm.2006.246504.

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Choi, Munkang, Victor Moroz, Lee Smith, and Oleg Penzin. "14 nm FinFET Stress Engineering with Epitaxial SiGe Source/Drain." In 2012 International Silicon-Germanium Technology and Device Meeting (ISTDM). IEEE, 2012. http://dx.doi.org/10.1109/istdm.2012.6222469.

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Yee-Chia Yeo. "Enhancing CMOS Transistor Performance Using Lattice-Mismatched Materials in Source/Drain Regions." In 2006 International SiGe Technology and Device Meeting. IEEE, 2006. http://dx.doi.org/10.1109/istdm.2006.246557.

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Jianqin Gao, Jun Tan, Haifeng Zhou, Jingxun Fang, and Albert Pang. "Research of silicon cap for epitaxy sige in source/drain regions." In 2015 China Semiconductor Technology International Conference (CSTIC). IEEE, 2015. http://dx.doi.org/10.1109/cstic.2015.7153413.

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Augendre, E., S. Maitrejean, B. De Salvo, et al. "Impact of source/drain silicon cap on FDSOI SiGe pMOSFET performance." In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2015. http://dx.doi.org/10.1109/s3s.2015.7333544.

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Fukuda, M., Y. Shimamune, M. Nakamura, et al. "Stress variability control by defects suppression of SiGe Source/Drain using novel SiGe epitaxial growth technique." In 2009 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2009. http://dx.doi.org/10.7567/ssdm.2009.a-3-5l.

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Togo, M., J. W. Lee, L. Pantisano, et al. "Phosphorus doped SiC Source Drain and SiGe channel for scaled bulk FinFETs." In 2012 IEEE International Electron Devices Meeting (IEDM). IEEE, 2012. http://dx.doi.org/10.1109/iedm.2012.6479064.

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Peng, Min-Ru, Mu-Chun Wang, Liang-Ru Ji, et al. "Characteristics and hot-carrier effects of strained pMOSFETs with SiGe channel and embedded SiGe source/drain stressor." In 2013 IEEE International Nanoelectronics Conference (INEC). IEEE, 2013. http://dx.doi.org/10.1109/inec.2013.6466020.

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Mu-Chun Wang, Min-Ru Peng, Liang-Ru Ji, et al. "Strained pMOSFETs with SiGe channel and embedded SiGe source/drain stressor under heating and hot-carrier stresses." In 2013 2nd International Symposium on Next-Generation Electronics (ISNE 2013). IEEE, 2013. http://dx.doi.org/10.1109/isne.2013.6512370.

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Reports on the topic "SiGe source and drain"

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Atkinson, Dan, and Alex Hale, eds. From Source to Sea: ScARF Marine and Maritime Panel Report. Society of Antiquaries of Scotland, 2012. http://dx.doi.org/10.9750/scarf.09.2012.126.

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The main recommendations of the panel report can be summarised under four headings: 1. From Source to Sea: River systems, from their source to the sea and beyond, should form the focus for research projects, allowing the integration of all archaeological work carried out along their course. Future research should take a holistic view of the marine and maritime historic environment, from inland lakes that feed freshwater river routes, to tidal estuaries and out to the open sea. This view of the landscape/seascape encompasses a very broad range of archaeology and enables connections to be made w
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Clausen, Jay, D. Moore, L. Cain, and K. Malinowski. VI preferential pathways : rule or exception. Engineer Research and Development Center (U.S.), 2021. http://dx.doi.org/10.21079/11681/41305.

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Trichloroethylene (TCE) releases from leaks and spills next to a large government building occurred over several decades with the most recent event occurring 20 years ago. In response to a perceived conventional vapor intrusion (VI) issue a sub-slab depressurization system (SSDS) was installed 6 years ago. The SSDS is operating within design limits and has achieved building TCE vapor concentration reductions. However, subsequent periodic TCE vapor spikes based on daily HAPSITE™ measurements indicate additional source(s). Two rounds of smoke tests conducted in 2017 and 2018 involved introductio
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