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Dissertations / Theses on the topic 'SiGe source and drain'

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Published: 4 June 2021
Last updated: 4 February 2022

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1

Isheden, Christian. "Source and drain engineering in SiGe-based pMOS transistors." Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-96.

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2

Christensen, Björn. "Fabrication and characterization of gate last Si MOSFETs with SiGe source and drain." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-211547.

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The continuous evolution of digital technology we enjoy today is the result of ever shrinking, faster and cheaper transistors that make up the ubiquitous integrated circuits of our devices. Over the decades, the industry has gone from purely geometrical scaling to innovative solutions like high-k dielectrics combined with metal gates and FinFETs. A possible future is the use of high mobility materials such as Germanium for the active areas of a transistor instead of Silicon. As a step towards building devices on Ge, we characterize a gate last process with epitaxial deposition of Si0.75Ge0.25
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3

Daubriac, Richard. "Caractérisation de techniques d'implantations ioniques alternatives pour l'optimisation du module source-drain de la technologie FDSOI 28nm." Thesis, Toulouse, INSA, 2018. http://www.theses.fr/2018ISAT0031/document.

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Durant ces dernières années, l’apparition de nouvelles architectures (FDSOI, FinFETs ou NW-FETs) et l’utilisation de nouveaux matériaux (notamment SiGe) ont permis de repousser les limites des performances des dispositifs MOS et de contourner l’effet canal court inhérent à la miniaturisation des composants. Cependant, pour toutes ces nouvelles architectures, la résistance de contact se dégrade au fil des nœuds technologiques. Celle-ci dépend fortement de deux paramètres physiques : la concentration de dopants actifs proches de la surface du semi-conducteur et de la hauteur de barrière Schottky
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4

Ogier, Jean-Luc. "Optimisation de structures et de technologies pour la réalisation de drain-source de transistors MOS submicroniques." Université Joseph Fourier (Grenoble), 1993. http://www.theses.fr/1993GRE10167.

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Afin de reduire les effets de canaux courts et de porteurs chauds, nous avons etudie differentes solutions technologiques concernant les drain/source de transistors metal oxyde silicium (mos) submicroniques. Cette etude a ete realisee dans le cadre de filieres cmos (mos complementaires) submicroniques (0. 7-0. 5-0. 35 micron). Concernant le transistor nmos, notre etude vise a reduire les phenomenes de degradations par porteurs chauds qui affectent la fiabilite du dispositif. Nous nous interessons uniquement a la partie faiblement dopee du drain (ldd). Nous presentons dans un premier temps les
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5

Zhang, Zhikuan. "Source/drain engineering for extremely scaled MOSFETs /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20ZHANG.

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6

Hakanen, Jani. "Modeling of nanostructures with complex source and drain." Thesis, Linköping University, The Department of Physics, Chemistry and Biology, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4285.

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<p>In this thesis we report on calculations for open quantum mechanical and certain microwave systems. The models refer to a quantum point contact and an electron cavity. We model this open system with an imaginary potential as source and drain, and use the finite difference method to make our calculations. We report on general features of the model we have found, and compare our calculations with measurements made on microwave cavities.</p>
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7

Waite, Andrew Michael. "Elevated source/drain MOSFETs for deep submicron VLSI." Thesis, University of Southampton, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299702.

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8

Zhang, Zhikuan. "A novel MOSFET's with source/drain on insulator /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20ZHANG.

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9

Luo, Jun. "Integration of metallic source/drain contacts in MOSFET technology." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-13136.

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The continuous and aggressive downscaling of conventional CMOS devices has been driving the vast growth of ICs over the last few decades. As the CMOS downscaling approaches the fundamental limits, novel device architectures such as metallic source/drain Schottky barrier MOSFET (SB-MOSFET) and SB-FinFET are probably needed to further push the ultimate downscaling. The ultimate goal of this thesis is to integrate metallic Ni1-xPtx silicide (x=0~1) source/drain into SB-MOSFET and SB-FinFET, with an emphasis on both material and processing issues related to the integration of Ni1-xPtx silicides to
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10

Gudmundsson, Valur. "Fabrication, characterization, and modeling of metallic source/drain MOSFETs." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-49184.

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As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant as
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11

Yin, Chunshan. "Source/drain and gate design of advanced MOSFET devices /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20YIN.

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12

Baptistat, Nicolas. "Etude et corrélation de l’influence des paramètres électriques sur la compatibilité électromagnétique." Thesis, Bordeaux, 2020. http://www.theses.fr/2020BORD0179.

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Les progrès des techniques de fabrication des systèmes électroniques permettent de réduire considérablement la taille des composants tout en augmentant les performances des circuits intégrés d'un point de vue rapidité ainsi que de consommation pour n'en citer que quelques-unes. Toutefois, cette révolution technologique génère davantage de problèmes de compatibilité électromagnétique (CEM). Pour pallier cela, les ingénieurs qui conçoivent les circuits électroniques réalisent différents tests de simulations et mesures CEM.Cependant, ces tests peuvent paraître insuffisants du fait qu'ils ne tienn
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13

Pearman, Dominic. "Electrical Characterisation and Modelling of Schottkybarrier metal source/drain MOSFETs." Thesis, University of Warwick, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.502175.

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The motivation for the work- presented in this thesis originates in the semiconductor industry's drive to create increasingly scaled transistors. In view of current device dimensions approaching fundamental atomic scales, the industry is looking to alternative structures to provide continued scaling capabilities. The use of metal, usually silicide. source and drain regions to create Schottky barrier (SB-)MOSFETs is one such approach. Previous work on static and RF electrical characterisation as well as simulations has shown this device to provide a number of scaling benefits to the planar MOSF
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14

Smith, Casey Eben Reidy Richard F. "Advanced technology for source drain resistance reduction in nanoscale FinFETs." [Denton, Tex.] : University of North Texas, 2008. http://digital.library.unt.edu/permalink/meta-dc-6052.

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15

Smith, Casey Eben. "Advanced Technology for Source Drain Resistance Reduction in Nanoscale FinFETs." Thesis, University of North Texas, 2008. https://digital.library.unt.edu/ark:/67531/metadc6052/.

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Dual gate MOSFET structures such as FinFETs are widely regarded as the most promising option for continued scaling of silicon based transistors after 2010. This work examines key process modules that enable reduction of both device area and fin width beyond requirements for the 16nm node. Because aggressively scaled FinFET structures suffer significantly degraded device performance due to large source/drain series resistance (RS/D), several methods to mitigate RS/D such as maximizing contact area, silicide engineering, and epitaxially raised S/D have been evaluated.
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16

Zhang, Zhen. "Integration of silicide nanowires as Schottky barrier source/drain in FinFETs." Doctoral thesis, Stockholm : Informations- och kommunikationsteknik, Kungliga Tekniska högskolan, 2008. http://www.diva-portal.org/kth/theses/abstract.xsql?dbid=4628.

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17

Adjaye, John. "Influence of source/drain residual implant lattice damage traps on silicon carbide metal semiconductor field effect transistor drain I-V characteristics." Diss., Mississippi State : Mississippi State University, 2007. http://sun.library.msstate.edu/ETD-db/theses/available/etd-09242007-081525.

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18

Maguire, Paul. "The characteristics of field effect transistors with Schottky barrier source and drain electrodes." Thesis, Queen's University Belfast, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.329351.

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19

Krom, Raymond T. "Gate-to-channel parasitic capacitance minimization and source-drain leakage evaluation in germanium PMOS /." Online version of thesis, 2008. http://hdl.handle.net/1850/9981.

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20

Chowdhury, Murshed M. "Physical analysis, modeling, and design of nanoscale double-gate MOSFETs with gate-source/drain underlap." [Gainesville, Fla.] : University of Florida, 2006. http://purl.fcla.edu/fcla/etd/UFE0015675.

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21

Kiani, Ahmed. "Analysis of metal oxide thin film transistors with high-k dielectrics and source/drain contact metals." Thesis, University of Cambridge, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.648586.

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22

Kim, Hyeok. "Improving charge injection in organic field-effect transistors by surface modification of source and drain electrodes." Sorbonne Paris Cité, 2015. http://www.theses.fr/2015USPCC089.

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La perspective de l'électronique flexible nécessite le développement de transistors à effet de champ organiques (OFET) ouvrant la voie à des dispositifs de grande surface, parmi lesquels des écrans flexibles, des cartes à puce intelligentes et des capteurs. Pour améliorer les performances électriques des OFET, un problème majeur est celui de l'injection des porteurs de charge à l'interface entre les électrodes et le semi-conducteur organique. Cette sujet de cette thèse est dédié à l'optimisation de l'injection des porteurs de charge par la modification des électrodes au moyen de couches auto-a
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23

ROSTOLL, MARIE-LAURENCE. "Etude de la metallisation auto-alignee des contacts source/drain : consequences sur l'architecture des transistors mos submicroniques." Rennes 1, 1996. http://www.theses.fr/1996REN10024.

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Avec la miniaturisation des transistors mos, et en particulier, la reduction de la profondeur de jonction dans les transistors submicroniques, l'integrite de ces jonctions devient de plus en plus fragile. En outre, certaines etapes technologiques sont de plus en plus delicates a realiser, une de ces etapes etant la siliciuration. La siliciuration est la premiere etape de metallisation des contacts source/drain et grille. Elle est habituellement realisee par reaction directe d'un film de metal (generalement le titane) avec le silicium a nu, qu'il soit mono- ou polycristallin. C'est la technique
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24

Mo, Hongxiang. "FORMATION OF LOW-RESISTIVITY GERMANOSILICIDE CONTACTS TO PHOSPHORUS DOPED SILICON-GERMANIUM ALLOY SOURCE/DRAIN JUNCTIONS FOR NANOSCALE CMOS." NCSU, 2003. http://www.lib.ncsu.edu/theses/available/etd-12182003-143823/.

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Conventional source/drain junction and contact formation processes can not meet the stringent requirements of future nanoscale complimentary metal oxide silicon (CMOS) technologies. The selective Si<sub>1-x</sub>Ge<sub>x</sub> source/drain technology was proposed in this laboratory as an alternative to conventional junction and contact schemes. The technology is based on selective chemical vapor deposition of in-situ boron or phosphorus doped Si<sub>1-x</sub>Ge<sub>x</sub> in source/drain areas. The fact that the dopant atoms occupy substitutional sites during growth make the high temperature
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25

Maury, Delphine. "Siliciuration par depot en phase vapeur pour les technologies cmos avancees : tisi#2 selectif et drain/source sureleves." Toulouse, INSA, 1997. http://www.theses.fr/1997ISAT0001.

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Avec la miniaturisation des circuits integres, certaines etapes technologiques deviennent de plus en plus delicates a realiser et en particulier l'etape de siliciuration, c'est a dire la metallisation des contacts source/drain et grille. La technique la plus couramment utilisee aujourd'hui est appelee salicide (self-aligned silicide): un film de tisi#2 est obtenu par reaction directe d'un film de titane (depose par pulverisation) avec le silicium du substrat. Elle presente cependant de serieuses limitations pour les technologies inferieures a 0,35 m. Nous avons pour cette raison etudie trois s
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26

Ji, Liang-Ru, and 紀良儒. "Characteristics and Hot-Carrier Effect of Strained pMOSFETs with SiGe Channel and SiGe Source/Drain Stressors." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/n8hyd3.

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碩士<br>國立臺北科技大學<br>機電整合研究所<br>100<br>The embedded SiGe S/D stressor involves etching out the source/drain silicon and replacing it with SiGe. It uses the lattice mismatch between silicon and germanium atoms which makes the silicon channel generating compressive strain. The compressive stress enhances hole mobility, and the pMOSFETs performance can be enhanced. Previous literatures have investigated the effects of pMOSFETs with embedded SiGe S/D stressor, but devices incorporated with biaxial strain and embedded SiGe S/D has not been clearly investigated. In this work, we research the characteri
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27

Huang, Wei-Luen, and 黃偉倫. "Carrier Mobility for MOSFET Using SiGe-Source/Drain on (110) Wafer Surface." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/93rxe4.

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碩士<br>國立臺北科技大學<br>機電整合研究所<br>98<br>In many strained methods, the process of SiGe-S/D has been worth applying. Nevertheless, the mechanism and characteristic were not so clear by applying on (110) wafer surfaces. For past five years, some studies of the temperature dependence on MOSFET devices have been investigated. Moreover, the scattering mechanism has been investigated to the strained MOSFETs. However, the SiGe-S/D with temperature dependence of channel lengths were less mentioned in the previous references. Therefore, it would use the devices of SiGe-S/D, Si-S/D, and control to discuss
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28

Lin, Sheng-Jung, and 林聖融. "Characteristics of SiGe Source/Drain Strained PMOSFETs with Different Si-Cap Thickness." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/9tt3zj.

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碩士<br>國立臺北科技大學<br>機電整合研究所<br>99<br>SiGe source/drain strained-Si technology involves etching out the source/drain area of a pMOSFET and replacing it with SiGe. The device performance can be improved due to the lattice mismatch between silicon and germanium which makes the silicon in channel generating compressive strain. Previous literatures have revealed the effect of MOSFETs with different gate length with uni-axial SiGe-S/D strain. But the studies of pMOSFETs having bi-axial strain using very thin Si-cap thickness and SiGe-S/D simultaneously haven’t been much investigated yet. In this w
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29

Cheng, Chung-Yun, and 鄭眾允. "Studies of SiGe Strain Impact on Layout Dependence, Stress-induced Defects and Reliability for 45nm PMOSFETs with SiGe Source/Drain." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/38214133565866475837.

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博士<br>國立成功大學<br>微電子工程研究所碩博士班<br>97<br>For the advanced CMOS technology, the use of the strained SiGe in PMOSFET S/D regions is one of the most important strain engineering technologies to enhance device performances. The resulting compressive stress in the channel increases the carrier mobility and hence the drive current. However, strain engineering would inevitably raise concerns such as: strain induced defect density, geometry, LOD effects, and reliability problems (e.g. NBTI, PBTI and Hot Carrier effects etc.). The primary research topic is to explore pathways to maximize the desired strai
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30

Hsiang-Jen, Huang, and 黃祥瑾. "Fabrication and Characterization of P type SiGe Raised Source and Drain MOSFET Grown by Ultra HighVacuum Chemical Molecular Epitaxy System." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/67464123671680926103.

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博士<br>國立交通大學<br>電子工程系<br>88<br>As the transistors continue to scale down, the characteristics of Co/Si1-xGex junction have received lots of attention because of its potential applications to heterojunction bipolar transistors. We have fabricated Co/Si1-xGex junction using room-temperature and high-temperature (i.e., at 450oC) sputtered Co on top of strained Si0.86Ge0.14 and Si0.91Ge0.09 layers prepared by ultra high vacuum chemical molecular epitaxy (UHVCME). The relative composition of Ge in Ge-rich Si1-zGez precipitate and the solid solution of ternary phase silicide of Co-Si-Ge system were
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31

Liang, Weng-Yeng, and 梁文彥. "Study on SONOS Flash Memory with Zener Junction at Source/Drain Side." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/80248943519696144380.

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碩士<br>國立交通大學<br>電子工程系所<br>96<br>The topic of the paper is the floating gate non-volatile flash memory which is extensively used in the present. For the non-volatile flash memory, there are two problems： First, when the thickness of tunneling oxide is scaled down to 10 nano-meter, the programming speed of flash memory is improved, but the retention time is decreased. Second, after the programming and erasing operation cycles, it will cause the tunneling oxide damage and make the oxide quality degradation. The oxide damage would generate a leakage path which will cause the charges stored in floa
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32

Tsai, Kai-Shiang, and 蔡凱翔. "Embedded SiGe Source/Drain Induced-Compressive Strain on Low Frequency Noise in 28nm High-K/Metal Gate P-Channel Metal-Oxide-Semiconductor Transistors." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/94482419693221028385.

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碩士<br>正修科技大學<br>電子工程研究所<br>102<br>In this work, introduction of a SiGe material into source/drain (S/D) regions provides uniaxial compressive strain on low frequency noise (LFN) in high-k/metal gate (HK/MG) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFET). We use high dielectric constant material (hafnium oxide ,HfO2) and titanium nitride (TiN) material in barrier layer and metal gate (MG) electrodes to produced P-type metal oxide semiconductor field effect transistor. The introduction of a SiGe material into source/drain (S/D) regions provides uniaxial compressive strain
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33

YANG, CHIH-HUNG, and 楊志鴻. "A Study of ESD Robustness by Bulk-/Source-/Drain-Side Layout Modulations in HV 40V/60V (n/p) LDMOS Components." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/18910748922947805510.

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碩士<br>國立聯合大學<br>電子工程學系碩士班<br>105<br>Nowadays, the high voltage (HV) device has been used extensively for diversified function consumer electronic product. But the high voltage device has worse Electrostatic discharge (ESD) robustness with non-uniformly trigger and current discharge inefficiently. However, integrated circuit was usually harmed by ESD/EOS zapping in semiconductor industries. Meanwhile, the HV device was sensitive to latch-up effect (LU) in high voltage application. Nevertheless, the latch-up immunity and ESD robustness contradict each other. Therefore, it is hard to design for t
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34

CHANG, CHIA-HSIEN, and 張家憲. "Channel length reduction and source/drain resistance of FinFETs under source/drain extensions." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/ma7kc6.

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碩士<br>明新科技大學<br>電子工程系碩士班<br>106<br>The applications of FinFET device with advanced nano-node process are more and more adopted in the commercial electronic products, especially in high-performance and high-density products. In order to obtain the optimal electrical characteristics and controllable process window for the desired devices, the electrical parameters for devices must be strictly monitored and verified. In this work, one set of 90nm lithographical masks with hard masks were applied to form the FinFET devices with the adjustment of exposure energy in lithography and the control o
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35

Ma, Lei. "Gallium nitride heterogeneous source drain MOSFET." 2007. http://www.lib.ncsu.edu/theses/available/etd-05072007-111606/unrestricted/etd.pdf.

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36

Lo, Yu-cheng, and 羅郁程. "Compact Modeling for Drain Current of Short-Channel MOSFETs Including Source/Drain Resistance Effect." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/99138119884238500835.

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碩士<br>國立雲林科技大學<br>電子與資訊工程研究所<br>93<br>In this thesis, the DC characteristics of MOSFETs are investigated by means of an analytical approach with considerations of the source-drain parasitic resistance. Experimental data of MOS devices for DRAM design and results of TCAD simulation are used to verify the accuracy of theoretical calculation. It is found that both the source and drain resistances can induce a large reduction in the drain current in the linear region, but only the source resistance can cause a large reduction in the drain current in the saturation region. Moreover, the drain curre
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37

Yuan, Wei-Yo, and 袁瑋佑. "Source/Drain and Contact Engineering for Ge MOSFETs." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/69314899495336797347.

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碩士<br>國立暨南國際大學<br>電機工程學系<br>103<br>There are two sections of this thesis. First, we used the monolayer doping to form an ultra shallow junction with no damage on the germanium substrate. Second, we used the low work function metal element, ytterbium, to form the metal germanide. We expected to reduce Fermi level pinning effect by using the high deposition temperature of ytterbium thin film. In the part of monolayer doping, the SIMS profile and diode characteristic was used to examine the shallow junction formation. However, the p type dopant, boron, was hard to diffuse into germanium substrate
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Lu, Chia-Yu, and 呂嘉裕. "Fabrication and Development of Schottky Source/Drain SOI MOSFET." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/70971964426233369960.

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碩士<br>國立交通大學<br>電子工程系<br>89<br>In this thesis, we have fabricated Schottky barrier (SB) MOSFET on SOI wafers. SB MOSFET employs silicide source/drain in lieu of ion implanted source/drain. So it is simple in processing, well suited for low temperature process. Further, it can operate both as n- and p-channel transistors (i.e., ambipolar). However, traditional SB MOSFET suffers from extremely large leakage current inherent in metal-semiconductor Schottky junction and therefore poor on/off current ratio, which severely restricted its application to mainstream integrated circuits. In t
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39

Chang, Ching-Nan, and 張景南. "Study Low Drain-Source On-State Resistance of Power MOSFET." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/jm3q5a.

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碩士<br>國立臺北科技大學<br>化學工程研究所<br>97<br>In this study, we modify the process of Power MOSFET to improve the device electricity characteristics. We propose the Power MOSFET with the Drain to Source breakdown voltage and Gate Threshold Voltage close in the same chip size condition for the low Drain-Source On-state Resistance optimization design. We reduce the conductive and power loss by the low Drain-Source On-state Resistance. We will utilize: 1. Adjust EPI layer resistance and thickness 2. Adjust Gate Trench depth 3. Adjust the Gate Oxide thickness 4. Adjust the Gate Poly implant dose and drivi
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Hou, Chiahsin, and 侯家信. "Gas Source MBE for SiGe : Design and Set up." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/00614125334246312226.

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41

洪至平. "High Performance Double Gate Poly-Si TFTs with Gate Overlapped Lightly Doped Drain and Raised Source Drain Design." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/56721561210878083052.

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42

Chen, Chien-Ming, and 陳建銘. "The High Performance Poly-Si Thin Film Transistors with Gate-Overlapped Lightly Doped Drain and Raised Source/Drain Design." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/51114419694487048992.

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碩士<br>逢甲大學<br>電子工程學系<br>102<br>Recently years, polycrystalline silicon thin film transistors have been widely used in many kinds of electronics-related fields, such as active matrix liquid crystal displays, solar cells and the realization of three-dimensional integrated circuits, or the pixel array and integrated peripheral circuits and driving circuits on a single glass panel(system on panel，SOP), the most important reason is the polycrystalline silicon thin film transistors have high driving current and high carrier mobility. However, the conventional polycrystalline sil
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Hou, Fu Ju, and 侯福居. "Fabrication and Characterization of SOI FinFETs with Schottky Barrier Source/Drain." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/05591667974984877700.

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碩士<br>國立交通大學<br>電資學院學程碩士班<br>90<br>In this thesis, we proposed and demonstrated a novel nano-scale silicon-on-insulator (SOI) FinFET device. The new device features a metallic silicided source/drain and field-induced S/D extensions. For the device fabrication, the patterning of nano-scale Si lines using electron-beam lithography with NEB-22 or hydrogen silsesquioxane (HSQ) resist was examined firstly. Since the HSQ resist has the advantages of high contrast and less line width fluctuation up to 1nm, the sub-50nm silicon lines can be more easily achieved. Nevertheless, the required high dosage
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Liu, Hsiao-Han, and 劉筱函. "Analysis of Source/Drain Resistance of Modified Schottky Barrier (MSB) FETs." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/37749911446097760337.

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碩士<br>國立交通大學<br>電子工程系所<br>96<br>As CMOS device scaling to nanometer regime, the conventional device would meet many challenges to scaling. The Schottky barrier (SB) FET becomes one of the promising structures and has better scalability. However, the on-current of SB FETs is limited by the Schottky barrier at source side. The Modified-Schottky-Barrier (MSB) FETs have been proposed to improve the SB FETs performance. Therefore, the effects of the parameters of the MSB region on device performance and series resistance optimization were simulated by TCAD tools. According to the simulation results
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Lu, Yu-Jiun, and 盧昱君. "The Characteristics of Junctionless Field Effect Transistor with Raised Source/Drain." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/48383y.

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碩士<br>逢甲大學<br>電子工程學系<br>105<br>This thesis studies the electrical characteristics of Junctionless FET (JLFET) with raised source/drain. The channel material of JLFET device is polysilicon. The device structure is TiN/Al2O3/Poly-Si. This work investigates the device electrical characteristics, including threshold voltage (Vth), subthreshold swing (S.S.), drain induced barrier lowering (DIBL) and device driving current on/off ratio (Ion/Ioff). Additionally, the raised source/drain JLFET with localized anti-channel doping, spacer capping, and the performance comparison of long and short channel d
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Lin, Jia-Wei, and 林家緯. "Study on the Source/Drain Engineering of InGaAs MOSFETs and FinFETs." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/zzspx2.

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碩士<br>國立交通大學<br>電子研究所<br>106<br>III–V compound semiconductors have been considered as the new channel materials for the future extremely scaled complementary metal oxide semiconductor (CMOS) devices due to their expected high injection velocity and electron mobility. However, one of the key challenges in realizing high performance III–V nMOSFETs is the reduction of source/drain (S/D) resistance (RSD). Due to nature low dopant solid solubility and high diffusivity of III-V based materials, a high RSD is disappointing the performance of III-V based MOSFET devices. In this study, we propose two m
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Han, Tsung-Yu, and 韓宗佑. "Fabrication of GaAs channel MOSFETs with Hetero-Epitaxial Ge Source/Drain." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/c9sd59.

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碩士<br>國立交通大學<br>電子研究所<br>106<br>In this thesis, we had optimized the hetero-epitaxy of Ge on GaAs surface by systematically investigated the effects of substrate orientation and surface preparation. Hence, we proposed a new structure of GaAs MOSFET having Ge source/drain (S/D) to tackle the intrinsic issues of the low solid solubility of dopants and low density of states (DOS) in GaAs material and also possess high electron mobility and thermal velocity to boost the current drive capability, compared to conventional Si MOSFETs. To achieve high quality Ge epitaxy of recessed S/D region, the eff
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Tsai, Hsianglin, and 蔡享霖. "The Study Of Organic Thin-Film Transistors With Transparent Source/Drain Electrodes." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/02608533784084775852.

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碩士<br>義守大學<br>電子工程學系<br>100<br>In this work, we applied a transparent electrode as the source/drain electrodes in organic thin-film transistors (OTFTs). The transparent electrode consisted of a low resistance metal, silver, which was sandwiched by high transmittance oxides, WO3. The optimum structure of transparent electrodes could be obtained by tuning the thickness in each layer of transparent electrode, which had a sheet resistance of 6.2 Ω/sq and an optical transmittance of 70% in the visible wavelength range of 380–780 nm. Utilizing the optimum structure of transparent electrode as the so
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Kuo, Po-Yi, and 郭柏儀. "Study of Selective Tungsten Raised-Source/Drain Polycrystalline Silicon Thin Film Transistors." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/27058365403991492207.

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碩士<br>國立交通大學<br>電子工程系<br>90<br>In this study, we have fabricated and characterized tungsten-raised source/drain polycrystalline silicon thin film transistors (W-TFTs). Tungsten film is selectively deposited at 300 ºC on an exposed poly-Si source/drain region to form a raised source/drain structure. As a result, the parasitic source/drain resistance is greatly reduced, and the drain current is dramatically improved as compared to conventional oxide-spacer counterpart. To suppress the floating body effect, W-TFTs with ultrathin channel thickness (30 nm) are also fabricated. While comp
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Ming, Chih, and 陳志明. "A Nano MOSFET with Spacer-like Silicide Source/Drain and Halo Implantation." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/31468877820882918071.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>92<br>In deep submicron region, scaling the sizes of devices and chips down is indispensable. The silicide at ultra-shallow extension area is used in order to keep low sheet resistance while junction depth is scaled. To introduce the implant between source and channel keeps high saturation current. Furthermore, we put two blocks of oxide between source and channel to suppress the short channel effect, which are able to resist depletions. We also demonstrate the capacitor-less memory cell. We use the variation of the charge and bias replacing the real capacitor. T
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