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Journal articles on the topic 'SiGe source and drain'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

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1

Lauwers, A., M. J. H. van Dal, P. Verheyen, et al. "Study of silicide contacts to SiGe source/drain." Microelectronic Engineering 83, no. 11-12 (2006): 2268–71. http://dx.doi.org/10.1016/j.mee.2006.10.017.

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2

Claeys, C., M. Bargallo Gonzalez, G. Eneman, et al. "Leakage Current Control in Recessed SiGe Source/Drain Junctions." Journal of The Electrochemical Society 154, no. 9 (2007): H814. http://dx.doi.org/10.1149/1.2756370.

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3

Wang, You, Yu Mao, Qizheng Ji, Ming Yang, Zhaonian Yang, and Hai Lin. "Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET." Electronics 10, no. 4 (2021): 454. http://dx.doi.org/10.3390/electronics10040454.

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Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

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4

Zhong, Min, Yu Hang Zhao, Shou Mian Chen, Ming Li, Shao Hai Zeng, and Wei Zhang. "TCAD Study of the Raised SiGe Source/Drain in 40nm PMOS." Key Engineering Materials 645-646 (May 2015): 70–74. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.70.

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An embedded SiGe layer was applied in the source/drain areas (S/D) of a field-effect transistor to boost the performance in the p channels. Raised SiGe S/D plays a critical role in strain engineering. In this study, the relationship between the SiGe overfilling and the enhancement of channel stress was investigated. Systematic technology computer aided design (TCAD) simulations of the SiGe overfill height in a 40 nm PMOS were performed. The simulation results indicate that a moderate SiGe overfilling induces the highest stress in the channel. Corresponding epitaxial growth experiments were done and the obtained experimental data was in good agreement with the simulation results. The effect of the SiGe overfilling is briefly discussed. The results and conclusions presented within this paper might serve as useful references for the optimization of the embedded SiGe stressor for 40 nm logic technology node and beyond.

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5

Miyanami, Yuki, Kazunobu Ota, Takashi Shinyama, et al. "Novel Process Development for Bilayer Embedded SiGe Source/Drain Formation." ECS Transactions 3, no. 7 (2019): 501–8. http://dx.doi.org/10.1149/1.2355847.

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6

Yang, Zhaonian, Yuan Yang, Ningmei Yu, and Juin Liou. "Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET." Micromachines 9, no. 12 (2018): 657. http://dx.doi.org/10.3390/mi9120657.

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Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with SiGe source/drain (S/D) regions is proposed, and its ESD characteristics are evaluated using technology computer aided design (TCAD) simulations. Under a transmission line pulsing (TLP) stressing condition, the triggering voltage of the SiGe S/D TFET is reduced by 35% and the failure current is increased by 17% in comparison with the conventional Si S/D TFET. Physical insights relevant to the ESD enhancement of the SiGe S/D TFET are provided and discussed.

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7

Zhong, Min, Shou Mian Chen, and David Wei Zhang. "Investigation of In Situ Boron-Doping in SiGe Source/Drain Layer Growth for PMOS Devices." Journal of Nanomaterials 2015 (2015): 1–6. http://dx.doi.org/10.1155/2015/537696.

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Embedded SiGe (eSiGe) source/drain (S/D) was studied to enhance PMOS performance. Detailed investigations concerning the effect of GeH4and B2H6gas flow rate on the resultant Boron-doping of the SiGe layer (on a 40 nm patterned wafer) were carried out. Various SiGeB epitaxial growth experiments were realized under systematically varying experimental conditions. Key structural and chemical characteristics of the SiGeB layers were investigated using Secondary Ion Mass Spectroscopy (SIMS), nanobeam diffraction mode (NBD), and Transmission Electron Microscopy (TEM) itself. Furthermore,Ion/Ioffperformances of 40 nm PMOS transistors are also measured by the Parametric Test Systems for the semiconductor industry. The results indicate that the ratio between GeH4and B2H6gas flow rates influences not only the Ge and Boron content of the SiGeB layer, but also the PMOS channel strain and the morphology of the eSiGe S/D regions which directly affect PMOS performance. In addition, the mechanism of Boron-doping during SiGe layer growth on the pattern wafer is briefly discussed. The results and discussion presented within this paper are expected to contribute to the optimization of eSiGe stressor, aimed for advanced CMOS devices.

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8

Qin, Changliang, Huaxiang Yin, Guilei Wang, et al. "Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs." Microelectronic Engineering 181 (September 2017): 22–28. http://dx.doi.org/10.1016/j.mee.2017.07.001.

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9

Raghunathan, Shyam, Tejas Krishnamohan, and Krishna C. Saraswat. "Novel SiGe Source/Drain for Reduced Parasitic Resistance in Ge NMOS." ECS Transactions 33, no. 6 (2019): 871–76. http://dx.doi.org/10.1149/1.3487617.

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10

Qi, Y., J. Peng, H. C. Lo, et al. "In-Situ Boron Doped SiGe Epitaxy Optimization for FinFET Source/Drain." ECS Transactions 75, no. 8 (2016): 265–72. http://dx.doi.org/10.1149/07508.0265ecst.

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11

Simoen, Eddy, Mireia Bargallo Gonzalez, Bertrand Vissouvanadin, et al. "Factors Influencing the Leakage Current in Embedded SiGe Source/Drain Junctions." IEEE Transactions on Electron Devices 55, no. 3 (2008): 925–30. http://dx.doi.org/10.1109/ted.2007.914843.

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12

Cui, Wei, Shi Lu Xu, Ping Li, Ting Ma, and Yong Hui Yang. "A Novel Amorphous SiGe Material Used in CMOS Device." Advanced Materials Research 291-294 (July 2011): 465–68. http://dx.doi.org/10.4028/www.scientific.net/amr.291-294.465.

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In this paper, we propose a novel material- amorphous silicon germanium(a-SiGe). The a-SiGe film was formed by PECVD at a low temperature and a low frequency. By adjusting the fraction x of Ge in Si1-xGex, optimal SiGe bandgap was achieved. We used amorphous silicon germanium alloy as MOSFET source/drain. The parameter of MOSFET shows that, as the fraction increases, the drain-to-source breakdown voltage increases. With reduction of the minority carrier inject ratio, the current gain β of parasitic BJT in MOSFET was reduced greatly, which eliminates the limit of the breakdown voltage of the device.

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13

Demeurisse, C., P. Verheyen, K. Opsomer, C. Vrancken, P. Absil, and A. Lauwers. "Thermal stability of NiPt- and Pt-silicide contacts on SiGe source/drain." Microelectronic Engineering 84, no. 11 (2007): 2547–51. http://dx.doi.org/10.1016/j.mee.2007.05.065.

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14

Ohyama, H., N. Naka, K. Takakura, et al. "Evaluation of electron irradiated embedded SiGe source/drain diodes by Raman spectroscopy." Microelectronic Engineering 88, no. 4 (2011): 484–87. http://dx.doi.org/10.1016/j.mee.2010.11.006.

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15

Loo, Roger, Peter Verheyen, Geert Eneman, et al. "Characteristics of selective epitaxial SiGe deposition processes for recessed source/drain applications." Thin Solid Films 508, no. 1-2 (2006): 266–69. http://dx.doi.org/10.1016/j.tsf.2005.06.108.

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16

Simoen, Eddy R., Mireia Bargallo Gonzalez, Geert Eneman, et al. "Diode Analysis of Electrically Active Defects in Recessed SiGe Source/Drain Diodes." ECS Transactions 3, no. 7 (2019): 655–65. http://dx.doi.org/10.1149/1.2355861.

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17

Ikeda, K., Y. Yamashita, A. Endoh, T. Fukano, K. Hikosaka, and T. Mimura. "50-nm gate Schottky source/drain p-MOSFETs with a SiGe channel." IEEE Electron Device Letters 23, no. 11 (2002): 670–72. http://dx.doi.org/10.1109/led.2002.805007.

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18

Bazizi, E. M., A. Zaka, G. Dilliway, et al. "Investigation of Embedded SiGe Source/Drain for 28nm HKMG PFET Performance Enhancement." ECS Transactions 53, no. 3 (2013): 27–32. http://dx.doi.org/10.1149/05303.0027ecst.

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19

Ohyama, H., T. Nagano, K. Takakura, et al. "Effects of electron and proton irradiation on embedded SiGe source/drain diodes." Materials Science in Semiconductor Processing 11, no. 5-6 (2008): 310–13. http://dx.doi.org/10.1016/j.mssp.2008.09.009.

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20

Khandelwal, Sourabh, Juan Pablo Duarte, Aditya Medury, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu. "Modeling SiGe FinFETs With Thin Fin and Current-Dependent Source/Drain Resistance." IEEE Electron Device Letters 36, no. 7 (2015): 636–38. http://dx.doi.org/10.1109/led.2015.2437794.

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21

Zhang, Da, Ted White, and Bich-Yen Nguyen. "Embedded Source/Drain SiGe Stressor Devices on SOI: Integrations, Performance, and Analyses." IEEE Transactions on Electron Devices 53, no. 12 (2006): 3020–24. http://dx.doi.org/10.1109/ted.2006.885534.

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22

Peng, Du Zen, Ting-Chang Chang, Po-Sheng Shih, et al. "Polycrystalline silicon thin-film transistor with self-aligned SiGe raised source/drain." Applied Physics Letters 81, no. 25 (2002): 4763–65. http://dx.doi.org/10.1063/1.1528727.

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23

Ko, Eunjung, Juhee Lee, Seung-Wook Ryu, Hyunsu Shin, Seran Park, and Dae-Hong Ko. "Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain." Coatings 11, no. 6 (2021): 654. http://dx.doi.org/10.3390/coatings11060654.

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Silicon german ium (SiGe) has attracted significant attention for applications in the source/drain (S/D) regions of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs). However, in SiGe, as the Ge concentration increases, high-density defects are generated, which limit its applications. Therefore, several techniques have been developed to minimize defects; however, these techniques require relatively thick epitaxial layers and are not suitable for gate-all-around FETs. This study examined the effect of Ge concentration on the embedded SiGe source/drain region of a logic p-MOSFET. The strain was calculated through nano-beam diffraction and predictions through a simulation were compared to understand the effects of stress relaxation on the change in strain applied to the Si channel. When the device performance was evaluated, the drain saturation current was approximately 710 µA/µm at an off current of 100 nA/µm with a drain voltage of 1 V, indicating that the current was enhanced by 58% when the Ge concentration was optimized.

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24

Wang, Mu Chun, Shea Jue Wang, Heng Sheng Huang, et al. "Characteristics and hot-carrier effects of strained pMOSFETs with SiGe channel and embedded SiGe source/drain stressors." International Journal of Nanotechnology 11, no. 1/2/3/4 (2014): 62. http://dx.doi.org/10.1504/ijnt.2014.059810.

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25

Hamaya, Kohei, Yuichiro Ando, Taizoh Sadoh, and Masanobu Miyao. "Source–Drain Engineering Using Atomically Controlled Heterojunctions for Next-Generation SiGe Transistor Applications." Japanese Journal of Applied Physics 50, no. 1R (2011): 010101. http://dx.doi.org/10.7567/jjap.50.010101.

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26

Tong, K. Y., Emil V. Jelenkovic, W. Liu, S. G. Wang, and J. Y. Dai. "Polysilicon thin film transistors using sputtered HfO2 gate dielectric and SiGe source/drain." Semiconductor Science and Technology 22, no. 5 (2007): 574–76. http://dx.doi.org/10.1088/0268-1242/22/5/020.

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27

Jin, L., H. Tu, Y. He, Y. He, and J. Wu. "A Comprehensive Study of SiGe Source/ Drain Local Stress by Nano Beam Diffraction." ECS Transactions 52, no. 1 (2013): 33–37. http://dx.doi.org/10.1149/05201.0033ecst.

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28

Wang, Lin-Lin, Jian-Chi Zhang, and Yu-Long Jiang. "Optimization of Ni(Pt)/Si-cap/SiGe Silicidation for pMOS Source/Drain Contact." IEEE Transactions on Electron Devices 64, no. 5 (2017): 2067–71. http://dx.doi.org/10.1109/ted.2017.2682163.

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29

Hamaya, Kohei, Yuichiro Ando, Taizoh Sadoh, and Masanobu Miyao. "Source–Drain Engineering Using Atomically Controlled Heterojunctions for Next-Generation SiGe Transistor Applications." Japanese Journal of Applied Physics 50 (January 20, 2011): 010101. http://dx.doi.org/10.1143/jjap.50.010101.

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30

Vanlalawmpuia, K., Brinda Bhowmick, and Madhuchhanda Choudhury. "Optimisation of fully depleted SiGe channel with raised source/drain buried oxide nMOSFET." International Journal of Nanoparticles 11, no. 2 (2019): 80. http://dx.doi.org/10.1504/ijnp.2019.099180.

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31

Vanlalawmpuia, K., Madhuchhanda Choudhury, and Brinda Bhowmick. "Optimisation of fully depleted SiGe channel with raised source/drain buried oxide nMOSFET." International Journal of Nanoparticles 11, no. 2 (2019): 80. http://dx.doi.org/10.1504/ijnp.2019.10020324.

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32

Isheden, C., P. E. Hellström, H. H. Radamson, S. L. Zhang, and M. Östling. "MOSFETs with Recessed SiGe Source/Drain Junctions Formed by Selective Etching and Growth." Electrochemical and Solid-State Letters 7, no. 4 (2004): G53. http://dx.doi.org/10.1149/1.1646833.

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33

Simoen, Eddy Roger, Mireia Bargallo Gonzalez, Geert Eneman, et al. "Germanium content dependence of the leakage current of recessed SiGe source/drain junctions." Journal of Materials Science: Materials in Electronics 18, no. 7 (2007): 787–91. http://dx.doi.org/10.1007/s10854-006-9102-7.

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34

Loo, Roger, Peter Verheyen, Rita Rooyackers, et al. "Selective Epitaxy of Si/SiGe to Improve pMOS Devices by Recessed Source/Drain and/or Buried SiGe Channels." ECS Transactions 3, no. 7 (2019): 453–65. http://dx.doi.org/10.1149/1.2355843.

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35

Tsai, Shih-Chang, San-Lein Wu, Jone-Fang Chen, et al. "Investigation of Low-Frequency Noise Characterization of 28-nm High-k pMOSFET with Embedded SiGe Source/Drain." Journal of Nanomaterials 2014 (2014): 1–6. http://dx.doi.org/10.1155/2014/787132.

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We have studied the low-frequency noise characterizations in 28-nm high-k (HK) pMOSFET with embedded SiGe source/drain (S/D) through1/f noise and random telegraph noise measurements simultaneously. It is found that uniaxial compressive strain really existed in HK pMOSFET with embedded SiGe S/D. The compressive strain induced the decrease in the tunneling attenuation length reflecting in the oxide trap depth from Si/SiO2interface to the HK layer, so that the oxide traps at a distance from insulator/semiconductor interface cannot capture carrier in the channel. Consequently, lower1/f noise level in HK pMOSFET with embedded SiGe S/D is observed, thanks to the less carrier fluctuations from trapping/detrapping behaviors. This result represents an intrinsic benefit of HK pMOSFET using embedded SiGe S/D in low-frequency noise characteristics.

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36

Radamson, Henry H., Jun Luo, Changliang Qin, et al. "Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs." International Journal of High Speed Electronics and Systems 26, no. 01n02 (2017): 1740003. http://dx.doi.org/10.1142/s0129156417400031.

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In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 1020 cm−3. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

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37

Qi, Cheng, Yaswanth Rangineni, Gary Goncher, Raj Solanki, Kurt Langworthy, and Jay Jordan. "SiGe Nanowire Field Effect Transistors." Journal of Nanoscience and Nanotechnology 8, no. 1 (2008): 457–60. http://dx.doi.org/10.1166/jnn.2008.083.

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Si0.5Ge0.5 nanowires have been utilized to fabricate source-drain channels of p-type field effect transistors (p-FETs). These transistors were fabricated using two methods, focused ion beam (FIB) and electron beam lithography (EBL). The electrical analyses of these devices show field effect transistor characteristics. The boron-doped SiGe p-FETs with a high-k (HfO2) insulator and Pt electrodes, made via FIB produced devices with effective hole mobilities of about 50 cm2V−1s−1. Similar transistors with Ti/Au electrodes made via EBL had effective hole mobilities of about 350 cm2V−1s−1.

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38

Naumann, Andreas, Stephan Kronholz, Anthony Mowry, et al. "Novel enhanced stressors with graded encapsulated SiGe embedded in the source and drain areas." Materials Science and Engineering: B 154-155 (December 2008): 95–97. http://dx.doi.org/10.1016/j.mseb.2008.09.024.

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39

Gonzalez, M. Bargallo, E. Simoen, B. Vissouvanadin, et al. "Electric field dependence of trap-assisted-tunneling current in strained SiGe source/drain junctions." Applied Physics Letters 94, no. 23 (2009): 233507. http://dx.doi.org/10.1063/1.3149707.

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40

Pollet, Olivier, Nicolas Possémé, Vincent Ah-Leung, and Maxime Garcia Barros. "Thin Layer Etching of Silicon Nitride: Comparison of Downstream Plasma, Liquid HF and Gaseous HF Processes for Selective Removal after Light Ion Implantation." Solid State Phenomena 255 (September 2016): 69–74. http://dx.doi.org/10.4028/www.scientific.net/ssp.255.69.

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For technology nodes beyond 14nm silicon nitride spacer etching has become a major challenge. Conventional plasma etching techniques based on CHF3/O2 cannot achieve thorough nitride removal on horizontal surfaces without inducing either CD loss or Si/SiGe source/drain recess. This leads to either gate leakage increase or poor raised source/drain epitaxy. To overcome atomic scale control issues faced with continuous plasma processes, several techniques aiming at achieving atomic layer etching or thin layer etching were recently described [1]. An original etching approach has been reported which consists in modifying the silicon nitride through H2 ion implantation by plasma (ICP or CCP) and then selectively removing the modified fraction of the layer thanks to chemical etching [2]. Layer modification depth is controlled thanks to plasma parameters (bias voltage and process time). This unconventional technique was demonstrated on 14nm FDSOI logic device and showed less than 1nm spacer CD loss, less than 0.6nm SiGe recess which enabled defect-free source/drain epitaxy [2]. Mechanisms for silicon nitride modifications and selective removal are discussed in this article by comparing downstream plasma, liquid-phase HF and gas-phase HF as removal techniques.

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41

Kar, G. S., S. Kiravittaya, U. Denker, B. Y. Nguyen, and O. G. Schmidt. "Strain distribution in a transistor using self-assembled SiGe islands in source and drain regions." Applied Physics Letters 88, no. 25 (2006): 253108. http://dx.doi.org/10.1063/1.2214150.

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42

Nishiyama, Akira, Osamu Arisumi, Mamoru Terauchi, et al. "Formation of SiGe Source/Drain Using Ge Implantation for Floating-Body Effect Resistant SOI MOSFETs." Japanese Journal of Applied Physics 35, Part 1, No. 2B (1996): 954–59. http://dx.doi.org/10.1143/jjap.35.954.

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43

Jung, Eun Sik, Ji Chel Bea, and Young Jae Lee. "Ultra-shallow junction with elevated SiGe source∕drain fabricated by laser-induced atomic layer doping." Electronics Letters 38, no. 16 (2002): 926. http://dx.doi.org/10.1049/el:20020512.

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44

Lee, Byongseog, Minwon Kim, Ji-Hun Kim, et al. "Doping-Less Tunnel Field Effect Transistor Using Compact-Si-Drain, SiGe-Channel, and Ge-Source." ECS Meeting Abstracts MA2020-02, no. 14 (2020): 1352. http://dx.doi.org/10.1149/ma2020-02141352mtgabs.

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45

Chang, J., X. Ji, L. Ma, et al. "Impact of various silicide techniques on SiGe source–drain series resistance and mobility of pMOSFETs." Semiconductor Science and Technology 28, no. 11 (2013): 115009. http://dx.doi.org/10.1088/0268-1242/28/11/115009.

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46

Hartmann, J. M., F. Gonzatti, F. Fillot, and T. Billon. "Growth kinetics and boron doping of very high Ge content SiGe for source/drain engineering." Journal of Crystal Growth 310, no. 1 (2008): 62–70. http://dx.doi.org/10.1016/j.jcrysgro.2007.10.003.

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47

Dash, T. P., S. Dey, S. Das, J. Jena, E. Mahapatra, and C. K. Maiti. "Source/Drain Stressor Design for Advanced Devices at 7 nm Technology Node." Nanoscience & Nanotechnology-Asia 10, no. 4 (2020): 447–56. http://dx.doi.org/10.2174/2210681209666190809101307.

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Background:: In nano and microelectronics, device performance enhancement is limited by downscaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. This paper explores the key design challenges of stress-engineered FinFETs based on the epitaxial SiGe S/D at 7 nm Technology node. Objective:: To study the mechanical stress evolution in a tri-gate FinFET at 7 nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the devices through device simulation. Methods: 3D sub-band Boltzmann transport analysis for tri-gate PMOS FinFETs was used, with 2D Schrödinger solution in the fin cross-section and 1D Boltzmann transport along the channel. Results:: Using stress maps, the mechanical stress impact on the transfer characteristics of the device through device simulation has been analyzed. Conclusion:: Suitability of predictive TCAD simulations to explore the potential of innovative strain-engineered FinFET structures for future generation CMOS technology is demonstrated.

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48

Chien, Feng-Tso, Jing Ye, Wei-Cheng Yen, Chii-Wen Chen, Cheng-Li Lin, and Yao-Tsung Tsai. "Raised Source/Drain (RSD) and Vertical Lightly Doped Drain (LDD) Poly-Si Thin-Film Transistor." Membranes 11, no. 2 (2021): 103. http://dx.doi.org/10.3390/membranes11020103.

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The raised source/drain (RSD) structure is one of thin film transistor designs that is often used to improve device characteristics. Many studies have mentioned that the high impact ionization rate occurring at a drain side can be reduced, owing to a raised source/drain area that can disperse the drain electric field. In this study, we will discuss how the electric field at the drain side of an RSD device is reduced by a vertical lightly doped drain (LDD) scheme rather than a RSD structure. We used different raised source/drain forms to simulate the drain side electric field for each device, as well as their output characteristics, using Integrated Systems Engineering (ISE-TCAD) simulators. Different source and drain thicknesses and doping profiles were applied to verify the RSD mechanism. We found that the electric fields of a traditional device and uniform doping RSD structures are almost the same (~2.9 × 105 V/cm). The maximum drain electric field could be reduced to ~2 × 105 V/cm if a vertical lightly doped drain RSD scheme was adopted. A pure raised source/drain structure did not benefit the device characteristics if a vertical lightly doped drain design was not included in the raised source/drain areas.

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49

Tang, Zhao Huan, Kai Zhou Tan, Wei Cui та Bin Wang. "μ_MAX Enhanced 190% of a Strained NMOS Based on SiGe Virtual Substrate". Advanced Materials Research 756-759 (вересень 2013): 154–57. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.154.

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Based on SiGe virtual substrate technology, a high-performance strained NMOS is obtained. By growing 2~3μm SiGe relaxed layer, 100~200nm strained SiGe layer and 20nm strained silicon layer, and also forming a P-well by multiple implantation technology, a surface strained NMOS is fabricated. Finally, Measured results shown that drain-source current and the low field maximal mobility of the strained NMOS are enhancement of up to 190% at Vgs=3.5V, which is almost three times to the value of common Silicon NMOS and is also better than the 170% reported in public.

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Lee, Chia-Feng, Ren-Yu He, Kuan-Ting Chen, Shu-Ying Cheng, and Shu-Tong Chang. "Strain engineering for electron mobility enhancement of strained Ge NMOSFET with SiGe alloy source/drain stressors." Microelectronic Engineering 138 (April 2015): 12–16. http://dx.doi.org/10.1016/j.mee.2015.01.013.

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