Relevant bibliographies by topics / Sigma-delta modulator

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Sigma-delta modulator'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 June 2024

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Journal articles on the topic "Sigma-delta modulator"

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Ren, Ming Yuan, Tuo Li, and Chang Chun Dong. "Design of a Fourth-Order Sigma-Delta Modulator for Audio Application." Applied Mechanics and Materials 380-384 (August 2013): 3580–83. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3580.

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Based on requirements on high performance and high resolution of modulators, a fourth-order Sigma-Delta modulator for audio application is developed in this paper. The modulator is designed under the commercial 0.5μm CMOS process and the circuits are given simulations by Spectre. The sampling frequency of sigma-delta modulator is 11.264 MHz, and OSR is 256 within the 22 kHz signal bandwidth. Measure performance shows that Sigma-Delta modulator enables its maximum SNR to achieve 103.5dB, and the accuracy of Sigma-Delta modulator is up to 16 bit.
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NERURKAR, SHAILESH B., and KHALID H. ABED. "A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 407–29. http://dx.doi.org/10.1142/s0218126609005149.

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This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.
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Beigh, Nadeem Tariq, Prince Nagar, Aamir Bin Hamid, Faizan Tariq Beigh, and Faroze Ahmad. "2nd Order Sigma Delta Modulator Design using Delta Sigma Toolbox." Asian Journal of Electrical Sciences 7, no. 2 (November 5, 2018): 41–45. http://dx.doi.org/10.51983/ajes-2018.7.2.2161.

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This paper discusses the block level design of 2nd order sigma delta using the Delta Sigma Toolbox and Simulink .An optimized modulator is designed with scaled coefficients, giving a low power, low frequency and high OSR modulator. The modulator presented has an OSR of 256, bandwidth of 200Hz, SNR of 100dB, SNDR of 96 dB, ENOB of 16 bits (approx.).The designed modulator is ideal for low power and low frequency applications, as in case of conversion of brain wave signals which are in the frequency range of 10-100Hz.This work provides the baseline for the design of the same modulator using switched capacitor in CMOS technology of 0.18μm TMSC CMOS technology with VDD of 1.8V.The coefficient values a, b, g, c are the ratios of capacitors in switched capacitor level design.
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Mishra, Samir Kumar, Rajendra Kuamr, and Hari Om Sharan. "Advancements in VLSI Technology for Enhanced Signal Processing and Power Management in Electronic Systems." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 11, no. 1 (August 31, 2020): 1139–54. http://dx.doi.org/10.61841/turcomat.v11i1.14591.

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This research investigates the application of Delta-Sigma Modulator controlled switch-mode power supplies to address the challenges associated with conventional PWM-controlled DC-DC Buck Converters. By exploiting the noise-shaping capabilities of Delta-Sigma modulation, in-band tones in the output are mitigated. The study encompasses three phases: initial design and performance evaluation of PWM-controlled converters, transition to Delta-Sigma Modulator control, and refinement of the design to enhance efficiency and noise performance. Notable achievements include reducing inductor values and integrating on-chip capacitors, leading to a peak efficiency of 91% at a 200MHz sampling frequency. Post-layout simulations further validate the superiority of Delta-Sigma Modulator controlled switch-mode power supplies over PWM-controlled counterparts.
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Lee, Kye-Shin. "Macro Model for Discrete-Time Sigma‒Delta Modulators." Electronics 11, no. 23 (December 2, 2022): 3994. http://dx.doi.org/10.3390/electronics11233994.

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This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since the macro model is a true representation of the actual transistor level circuit, a moderately good accuracy can be obtained. In addition, the proposed macro model includes the major amplifier, comparator, and switch‒capacitor non-idealities of the sigma‒delta modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, and switch-on resistance. The results show the simulation time of the proposed macro model sigma‒delta modulator is only 6.43% of the transistor level circuit with comparable accuracy. As a result, the proposed macro model can facilitate the circuit design and leverage non-ideality analysis of discrete-time sigma‒delta modulators. As a practical design example, a second order discrete-time sigma‒delta modulator with a five-level quantizer is realized using the propose macro model for GSM and WCDMA applications.
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Ioka, Eri, Nozomi Watanabe, Ryo Makishima, and Yasuyuki Matsuya. "Noise Characteristic of the Chaotic Double Loop Delta Sigma Modulator." International Journal of Bifurcation and Chaos 26, no. 11 (October 2016): 1650178. http://dx.doi.org/10.1142/s0218127416501789.

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The chaotic delta sigma modulator is a way to suppress the limit cycle oscillation caused by the input of a null or constant signal. By changing integrator gains, the output sequence becomes chaotic and the noise characteristic of the output is changed. This noise characteristic is an important factor for evaluating the performance of delta sigma modulation. The aim of this study is to analyze the noise characteristic of chaotic double loop delta sigma modulation when the null signal is input. We use a bifurcation diagram and FFT analysis to obtain the parameter dependence of the output state and noise characteristic, respectively. The output status of the chaotic double loop delta sigma modulation can be guessed from a bifurcation diagram with the brute force method. We also investigate the noise characteristic of the output signal of the chaotic modulator with FFT analysis and classify the various noise characteristics by changing the integrator gains of the double loop delta sigma modulator. We use FFT and the bifurcation diagram to classify these noise characteristics into three categories: suppressed tone (affected by the chaos), divergence, and the appearance of the limit cycle oscillation. We also confirm the existence of an unusual noise-shaping characteristic caused by the intermittent chaos.
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Xu, Chi, Yu Jin, and Duli Yu. "A Novel Sigma-Delta Modulator with Fractional-Order Digital Loop Integrator." Mathematical Problems in Engineering 2017 (2017): 1–7. http://dx.doi.org/10.1155/2017/9861383.

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This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, thus extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field. The proposed fractional-order Sigma-Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; moreover the signal-to-noise ratio (SNR) is improved remarkably. In particular, a 2nd-order digital loop integrator and a digital PIλDμ controller are combined to work as the fractional-order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional-order Sigma-Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional-order Sigma-Delta modulator.
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LEE, HO-YIN, CHEN-MING HSU, SHENG-CHIA HUANG, YI-WEI SHIH, and CHING-HSING LUO. "DESIGNING LOW POWER OF SIGMA DELTA MODULATOR FOR BIOMEDICAL APPLICATION." Biomedical Engineering: Applications, Basis and Communications 17, no. 04 (August 25, 2005): 181–85. http://dx.doi.org/10.4015/s1016237205000287.

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This paper discusses the design of micro power Sigma-delta modulator with oversampling technology. This Sigma-delta modulator design is paid special attention to its low power application of portable electronic system in digitizing biomedical signals such as Electro-cardiogram (ECG), Electroencephalogram (EEG) etc. [1]. A high performance, low power second order Sigma-delta modulator is more useful in analog signal acquisition system. Using Sigma-delta modulator can reduce the power consumption and cost in the whole system. The original biomedical signal can be reconstructed by simply applying the digital bit stream from the modulator output through a low-pass filter. The loop filter of this modulator has been implemented by using switch capacitor (SC) integrators and using simple circuitry consists of OpAmps, Comparator and DAC. In general, the resolution of modulator is about 10 bits for biomedical application. In this two order Sigma-delta modulator simulation results of the 1.8V sigma delta modulator show a 68 dB signal-to-noise-and-distortion ratio (SNDR) in 4 kHz biomedical signal bandwidth and a sampling frequency equal to 1 MHz in the 0.18 μ m CMOS technology. The power consumption is 400 μ W. It is very suitable for low power application of biomedical instrument design.
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Temenos, Nikos, Anastasis Vlachos, and Paul P. Sotiriadis. "Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals." Technologies 10, no. 1 (January 20, 2022): 14. http://dx.doi.org/10.3390/technologies10010014.

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This work presents a soft-filtering digital signal processing architecture based on sigma-delta modulators and stochastic computing. A sigma-delta modulator converts the input high-resolution signal to a single-bit stream enabling filtering structures to be realized using stochastic computing’s negligible-area multipliers. Simulation in the spectral domain demonstrates the filter’s proper operation and its roll-off behavior, as well as the signal-to-noise ratio improvement using the sigma-delta modulator, compared to typical stochastic computing filter realizations. The proposed architecture’s hardware advantages are showcased with synthesis results for two FIR filters using FPGA and synopsys tools, while comparisons with standard stochastic computing-based hardware realizations, as well as with conventional binary ones, demonstrate its efficacy.
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Sommarek, Johan, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, and Kari Halonen. "Digital Modulator with Bandpass Delta-Sigma Modulator." Analog Integrated Circuits and Signal Processing 43, no. 1 (April 2005): 81–86. http://dx.doi.org/10.1007/s10470-005-6573-z.

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Dissertations / Theses on the topic "Sigma-delta modulator"

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Pereira, Angelo W. D. "A floating-gate delta-sigma modulator." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04072004-180136/unrestricted/pereira%5Fangelo%5Fw%5F200312%5Fms.pdf.

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Ravichandran, Vasudha. "BINARY HYSTERETIC/PROTERETIC DELTA SIGMA MODULATOR." OpenSIUC, 2013. https://opensiuc.lib.siu.edu/theses/1150.

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A new type of delta-sigma modulator which operates in reverse hysteresis (proteresis) mode is proposed. In this mode, it brings in attractive advantages for reduced feedback delay and ultra high speed optical implementations. We have investigated the switching periods of the hysteretic delta-sigma modulator under the impact of positive feedback and impact of positive delay on the system. A comparison between these two systems and the reverse HDSM (proteresis DSM) is established. We derive the theoretical analysis of all the important parameters. The HDSM and reverse HDSM (proteresis DSM) architecture demonstrates high speed A/D conversion under some special specifications such as : (1) all signals within the modulator are nonnegative for a given bounded input; (2) no sample-and-hold switch required because of utilizing a bi-stable switch with hysteresis; (3) the input signal has almost a linear relationship with the time-averaged output. The system performances are evaluated by simulations and the results are compared with the theoretical analysis
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Yuan, Xiaolong. "Wideband Sigma-Delta Modulators." Licentiate thesis, KTH, Communication Systems, CoS, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-13212.

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Sigma-delta modulators (SDM) have come up as an attractive candidatefor analog-to-digital conversion in single chip front ends thanks to the continuousimproving performance. The major disadvantage is the limited bandwidthdue to the need of oversampling. Therefore, extending these convertersto broadband applications requires lowering the oversampling ratio (OSR) inorder. The aim of this thesis is the investigation on the topology and structureof sigma-delta modulators suitable for wideband applications, e.g. wireline orwireless communication system applications having a digital baseband aboutone to ten MHz.It has recently become very popular to feedforward the input signal inwideband sigma-delta modulators, so that the integrators only process quantizationerrors. The advantage being that the actual signal is not distorted byopamp and integrator nonlinearities. An improved feedforward 2-2 cascadedstructure is presented based on unity-gain signal transfer function (STF). Theimproved signal-to-noise-ratio (SNR) is obtained by optimizing zero placementof the noise transfer function (NTF) and adopting multi-bit quantizer.The proposed structure has low distortion across the entire input range.In high order single loop continuous-time (CT) sigma-delta modulator, excessloop delay may cause instability. Previous techniques in compensation ofinternal quantizer and feedback DAC delay are studied especially for the feedforwardstructure. Two alternative low power feedforward continuous-timesigma-delta modulators with excess loop delay compensation are proposed.Simulation based CT modulator synthesis from discrete time topologies isadopted to obtain the loop filter coefficients. Design examples are given toillustrate the proposed structure and synthesis methodology.Continuous time quadrature bandpass sigma-delta modulators (QBSDM)efficiently realize asymmetric noise-shaping due to its complex filtering embeddedin the loops. The effect of different feedback waveforms inside themodulator on the NTF of quadrature sigma-delta modulators is presented.An observation is made that a complex NTF can be realized by implementingthe loop as a cascade of complex integrators with a SCR feedback digital-toanalogconverter (DAC), which is desirable for its lower sensitivity to loopmismatch. The QBSDM design for different bandpass center frequencies relativeto the sampling frequency is illustrated.The last part of the thesis is devoted to the design of a wideband reconfigurablesigma-delta pipelined modulator, which consists of a 2-1-1 cascadedmodulator and a pipelined analog-to-digital convertor (ADC) as a multi-bitquantizer in the last stage. It is scalable for different bandwidth/resolutionapplication. The detail design is presented from system to circuit level. Theprototype chip is fabricated in TSMC 0.25um process and measured on thetest bench. The measurement results show that a SNR over 60dB is obtainedwith a sampling frequency of 70 MHz and an OSR of ten.

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Yang, Wei. "A 1.8V 2nd-order [sigma delta] modulator." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0004/MQ45999.pdf.

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Hsu, Stephanie C. "A fourth order [Sigma] [Delta] bandpass modulator." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/61312.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
In title on title page, "[Sigma]" and "[Delta]" appear as upper-case Greek letters. Cataloged from PDF version of thesis.
Includes bibliographical references (p. 57).
A fourth order bandpass [Sigma] [Delta] modulator is proposed to digitize signals from a MEMS gyroscope. The modulator samples the amplitude-modulated signal at eight times the carrier frequency and achieves an SNR of 82dB with a sampling frequency of 640kHz and a bandwidtn o 1.oKnz. ms document snows that bandpass [Sigma] [Delta] modulation offers the advantage of a high oversampling rate without the need to demodulate the signal for lowpass [Sigma] [Delta] modulation.
by Stephanie C. Hsu.
M.Eng.
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Simic, Emilija. "A bandpass sigma delta modulator IF receiver." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/43475.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
Includes bibliographical references (leaves 170-173).
by Emilija Simic.
M.Eng.
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TAFAZOLI, MEHRJERDI MOHAMAD. "ALL-OPTICAL DELTA-SIGMA MODULATOR DESIGN AND IMPLEMENTATION." OpenSIUC, 2015. https://opensiuc.lib.siu.edu/dissertations/1116.

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In this research an approach to design and implement all-optical delta-sigma modulator (ODSM) has been expanded. The two main blocks of this modulator are “leaky integrator” and “bi-stable switch” designed and implemented by using active element like semiconductor optical amplifier (SOA) and other passive elements like optical filter, isolator and coupler. All experiments are done on optical table and proper results achieved. Thus the new bi-stable switch is designed and implemented by using “inverted bistable switch” and “non-inverted bi-stable switch”. This switch is made by five ring lasers. Right wavelengths have chosen for each ring laser to achieve a novel characteristic called “Proteresis”. All control parameters of this switch was investigated The major impact of this research will be in the area communication system, which need high resolution and fast modulation speed with less noise in their systems.
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Althomali, Raed. "THEORETICAL INVESTIGATION AND PERFORMANCE ASSESSMENT OF REVERSED HYSTERESIS DELTA SIGMA MODULATOR DESIGN." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/794.

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This dissertation studies a unique delta sigma modulator (DSM), known as reversed hysteresis delta sigma modulator (R-HDSM). This modulator is appropriate for ultra-high speed analog-to-digital converters, which can be used for communications and signal processing systems and their applications. Furthermore, the procedure to design the binary delta sigma modulator (BDSM) with a delay is developed and then parameters deltaOFF and deltaON ; are calculated for the system. In addition, analysis of the BDSM with a delay is achieved and the theoretical and simulated values compared. The reversed hysteresis delta sigma modulators are also analyzed, and the theoretical and the simulated values compared. The dissertation evaluates the performance measure for the suggested systems with continuous DSM and BDSM in terms of the spurious free dynamic range (SFDR), the signal to noise ratio (SNR), and the root mean square error (RMS). It studies the second-order R-HDSM. Finally, it compares the first-order R- HDSM and the second-order R-HDSM in terms of the signal to noise ratio (SNR).
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Allen, Daniel J. "A programmable delta-sigma modulator using floating gates." Thesis, Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-03292004-141813/unrestricted/allen%5Fdaniel%5Fj%5F200312%5Fms.pdf.

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Jonsson, Fredrik. "Ultra Wide Band Sigma-Delta modulator in CMOS090." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2172.

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Today the frequency spectrum is full of wireless standards. The most common technique being used is the frequency modulation. To take advantage of this and the technology improvement a new wireless communication standard is being developed. This standard is using a low power impulse modulation method, allowing it to overlap with other standards. The proposed standard called IEEE802.15.3a is applied at an Ultra Wide Band and has potential to be used both in interchip and intrasystem communication, since it allows a very high data density.

In this thesis the analog to digital converter is designed, which is one part of a communication system. Although the signal bandwidth is very wide the converter is designed as a Sigma-Delta modulator, which is most suitable for low-speed applications. Its main advantages over high-speed converters are less area and less power consumption. The goal of this project is to investigate if the CMOS090 process technology will be sufficient for reaching a signal-to-noise ratio, SNR, of 30 dB in a signal band of 264 MHz.

The main limiting factor during the design of the modulator is the excess feedback delay. This delay degrades the SNR and can even make the system unstable. At a feedback delay of 83 ps and a sampling frequency of 6.336 GHz, the maximum SNR achieved was 27 dB. At this high frequency the modulator is close to instability. Hence, to ensure stability a maximum sampling frequency of 4.224 GHz is chosen, achieving a SNR of 19 dB.

The effect of the feedback delay can be reduced either by using a different structure or by using compensation methods, either of them would probably allow a SNR above 30 dB.

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Books on the topic "Sigma-delta modulator"

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Yang, Wei. A 1.8V 2nd-order [Sigma Delta] modulator. Ottawa: National Library of Canada, 1999.

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Owen, Bryn Robert. The design of delta-sigma modulator based IIR filters. Ottawa: National Library of Canada, 1993.

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Maskey, Liam. Digital filtering of sigma-delta modulator data using FPGA's. (s.l: The Author), 2000.

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Ma, Stanley Jeh-Chun. A low-power low-voltage second-order sigma delta modulator. Ottawa: National Library of Canada, 1998.

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Hein, Søren, and Avideh Zakhor. Sigma Delta Modulators. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3138-8.

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van Engelen, Jurgen, and Rudy van de Plassche. Bandpass Sigma Delta Modulators. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-4586-3.

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Hosseini, Kaveh. Minimizing spurious tones in digital delta-sigma modulators. New York: Springer, 2011.

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1929-, Temes Gabor C., ed. Understanding delta-sigma data converters. Piscataway, NJ: IEEE Press, 2005.

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Janssen, Erwin, and Arthur van Roermund. Look-Ahead Based Sigma-Delta Modulation. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-1387-1.

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Janssen, Erwin. Look-Ahead Based Sigma-Delta Modulation. Dordrecht: Springer Science+Business Media B.V., 2011.

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Book chapters on the topic "Sigma-delta modulator"

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van Veldhoven, Robert H. M., and Arthur H. M. van Roermund. "ΣΔ Modulator Robustness." In Robust Sigma Delta Converters, 91–174. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0644-6_6.

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van Veldhoven, Robert H. M., and Arthur H. M. van Roermund. "ΣΔ Modulator Flexibility." In Robust Sigma Delta Converters, 175–87. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0644-6_7.

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van Veldhoven, Robert H. M., and Arthur H. M. van Roermund. "ΣΔ Modulator Efficiency." In Robust Sigma Delta Converters, 189–211. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0644-6_8.

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van Veldhoven, Robert H. M., and Arthur H. M. van Roermund. "ΣΔ Modulator Algorithmic Accuracy." In Robust Sigma Delta Converters, 71–89. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0644-6_5.

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Bolatkale, Muhammed, Lucien J. Breems, and Kofi A. A. Makinwa. "Continuous-Time Delta-Sigma Modulator." In Analog Circuits and Signal Processing, 9–35. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-05840-5_2.

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van Veldhoven, Robert H. M., and Arthur H. M. van Roermund. "ΣΔ Modulator Implementations and the Quality Indicators." In Robust Sigma Delta Converters, 213–61. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0644-6_9.

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Arnaldi, Isacco. "The First-Order Sigma-Delta Modulator." In Design of Sigma-Delta Converters in MATLAB®/Simulink®, 21–50. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91539-5_2.

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Arnaldi, Isacco. "The Second-Order Sigma-Delta Modulator." In Design of Sigma-Delta Converters in MATLAB®/Simulink®, 51–78. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91539-5_3.

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Xu, Tao, and Marissa Condon. "MASH Digital Delta–Sigma Modulator with Multi-Moduli." In Lecture Notes in Electrical Engineering, 13–24. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-8776-8_2.

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Peluso, Vincenzo, Michiel Steyaert, and Willy Sansen. "∆Σ Modulator Topologies." In Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters, 7–28. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-2978-8_2.

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Conference papers on the topic "Sigma-delta modulator"

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Chung-Ming Hsieh and Hung-Wei Chiu. "Sigma Delta Modulator Design Automation." In 2007 5th International Conference on Communications, Circuits and Systems. IEEE, 2007. http://dx.doi.org/10.1109/icccas.2007.4348223.

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Almeida, W. R. M., R. C. S. Freire, S. Y. C. Catunda, and H. Aboushady. "CMOS sigma-delta thermal modulator." In 2010 IEEE Instrumentation & Measurement Technology Conference Proceedings. IEEE, 2010. http://dx.doi.org/10.1109/imtc.2010.5488054.

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Mahajan, Divya, Vippan Kakkar, and Amit Kumar Singh. "Analysis of Delta Sigma Modulator." In 2011 International Conference on Computational Intelligence and Communication Networks (CICN). IEEE, 2011. http://dx.doi.org/10.1109/cicn.2011.36.

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Abhirami, S., D. Vishnu, S. Sreelal, A. Sajeena, and Anu Assis. "Second-order Oversampled Delta-sigma Analog to Digital Converter." In 2nd International Conference on Modern Trends in Engineering Technology and Management. AIJR Publisher, 2023. http://dx.doi.org/10.21467/proceedings.160.18.

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The Delta Sigma modulation technology has been around for a while, but because of technological advancements, the devices are now more widely used and feasible. The work proposes a multi-bit Delta Sigma ADC of second order having a very low power consumption. MATLAB Simulink is used to develop both the Delta Sigma ADCs of first and second order and the digital output is passed through a digital filter to recreate the original signal. According to simulation results, at 100 KHz frequency of output sampling, the Delta-Sigma modulator exhibits a Spurious Free Dynamic Range of 95.38 dB, and also it demonstrates that the designed Delta-Sigma ADC is capable of achieving an ENOB (Effective Number of Bits) of 11.83 bits and an SNR of 72.99 dB.
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Rosa, Valter da Conceicao, and Amauri Oliveira. "Transducer with thermal Sigma-Delta modulator." In 2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC). IEEE, 2014. http://dx.doi.org/10.1109/i2mtc.2014.6860715.

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Reeves, Erin, Yiye Jin, Pablo Costanzo-Caso, and Azad Siahmakoun. "Fiber-optic asynchronous delta-sigma modulator." In 2010 Photonics Global Conference. IEEE, 2010. http://dx.doi.org/10.1109/pgc.2010.5706110.

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Reeves, Erin, Pablo Costanzo-Caso, and Azad Siahmakoun. "Asynchronous fiber-optic delta-sigma modulator." In 2011 IEEE Intl. Topical Meeting on Microwave Photonics (MWP 2011) jointly held with the 2011 Asia-Pacific Microwave Photonics Conference (APMP). IEEE, 2011. http://dx.doi.org/10.1109/mwp.2011.6088739.

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Sobot, Robert, Shawn Stapleton, and Marek Syrzycki. "Fractional Sigma-Delta Modulator in SiGe." In 2007 Canadian Conference on Electrical and Computer Engineering. IEEE, 2007. http://dx.doi.org/10.1109/ccece.2007.138.

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Sayeh, Mohammad R., and Azad Siahmakoun. "All optical binary delta-sigma modulator." In Photonics North 2005, edited by Peter Mascher, Andrew P. Knights, John C. Cartledge, and David V. Plant. SPIE, 2005. http://dx.doi.org/10.1117/12.628708.

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Ozols, K., R. Shavelis, and M. Greitans. "Amplitude adaptive asynchronous Sigma-delta modulator." In 2013 8th International Symposium on Image and Signal Processing and Analysis (ISPA). IEEE, 2013. http://dx.doi.org/10.1109/ispa.2013.6703786.

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Reports on the topic "Sigma-delta modulator"

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Mahurin, Eric, and Ray Siford. GaAs Sigma-Delta Modulator Modeling for Analog to Digital Converters (ADCS). Fort Belvoir, VA: Defense Technical Information Center, December 1992. http://dx.doi.org/10.21236/ada263419.

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