Dissertations / Theses: 'Sigma-delta modulator'

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Pereira, Angelo W. D. "A floating-gate delta-sigma modulator." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04072004-180136/unrestricted/pereira%5Fangelo%5Fw%5F200312%5Fms.pdf.

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Ravichandran, Vasudha. "BINARY HYSTERETIC/PROTERETIC DELTA SIGMA MODULATOR." OpenSIUC, 2013. https://opensiuc.lib.siu.edu/theses/1150.

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A new type of delta-sigma modulator which operates in reverse hysteresis (proteresis) mode is proposed. In this mode, it brings in attractive advantages for reduced feedback delay and ultra high speed optical implementations. We have investigated the switching periods of the hysteretic delta-sigma modulator under the impact of positive feedback and impact of positive delay on the system. A comparison between these two systems and the reverse HDSM (proteresis DSM) is established. We derive the theoretical analysis of all the important parameters. The HDSM and reverse HDSM (proteresis DSM) architecture demonstrates high speed A/D conversion under some special specifications such as : (1) all signals within the modulator are nonnegative for a given bounded input; (2) no sample-and-hold switch required because of utilizing a bi-stable switch with hysteresis; (3) the input signal has almost a linear relationship with the time-averaged output. The system performances are evaluated by simulations and the results are compared with the theoretical analysis

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Yuan, Xiaolong. "Wideband Sigma-Delta Modulators." Licentiate thesis, KTH, Communication Systems, CoS, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-13212.

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Sigma-delta modulators (SDM) have come up as an attractive candidatefor analog-to-digital conversion in single chip front ends thanks to the continuousimproving performance. The major disadvantage is the limited bandwidthdue to the need of oversampling. Therefore, extending these convertersto broadband applications requires lowering the oversampling ratio (OSR) inorder. The aim of this thesis is the investigation on the topology and structureof sigma-delta modulators suitable for wideband applications, e.g. wireline orwireless communication system applications having a digital baseband aboutone to ten MHz.It has recently become very popular to feedforward the input signal inwideband sigma-delta modulators, so that the integrators only process quantizationerrors. The advantage being that the actual signal is not distorted byopamp and integrator nonlinearities. An improved feedforward 2-2 cascadedstructure is presented based on unity-gain signal transfer function (STF). Theimproved signal-to-noise-ratio (SNR) is obtained by optimizing zero placementof the noise transfer function (NTF) and adopting multi-bit quantizer.The proposed structure has low distortion across the entire input range.In high order single loop continuous-time (CT) sigma-delta modulator, excessloop delay may cause instability. Previous techniques in compensation ofinternal quantizer and feedback DAC delay are studied especially for the feedforwardstructure. Two alternative low power feedforward continuous-timesigma-delta modulators with excess loop delay compensation are proposed.Simulation based CT modulator synthesis from discrete time topologies isadopted to obtain the loop filter coefficients. Design examples are given toillustrate the proposed structure and synthesis methodology.Continuous time quadrature bandpass sigma-delta modulators (QBSDM)efficiently realize asymmetric noise-shaping due to its complex filtering embeddedin the loops. The effect of different feedback waveforms inside themodulator on the NTF of quadrature sigma-delta modulators is presented.An observation is made that a complex NTF can be realized by implementingthe loop as a cascade of complex integrators with a SCR feedback digital-toanalogconverter (DAC), which is desirable for its lower sensitivity to loopmismatch. The QBSDM design for different bandpass center frequencies relativeto the sampling frequency is illustrated.The last part of the thesis is devoted to the design of a wideband reconfigurablesigma-delta pipelined modulator, which consists of a 2-1-1 cascadedmodulator and a pipelined analog-to-digital convertor (ADC) as a multi-bitquantizer in the last stage. It is scalable for different bandwidth/resolutionapplication. The detail design is presented from system to circuit level. Theprototype chip is fabricated in TSMC 0.25um process and measured on thetest bench. The measurement results show that a SNR over 60dB is obtainedwith a sampling frequency of 70 MHz and an OSR of ten.

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Yang, Wei. "A 1.8V 2nd-order [sigma delta] modulator." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0004/MQ45999.pdf.

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Hsu, Stephanie C. "A fourth order [Sigma] [Delta] bandpass modulator." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/61312.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
In title on title page, "[Sigma]" and "[Delta]" appear as upper-case Greek letters. Cataloged from PDF version of thesis.
Includes bibliographical references (p. 57).
A fourth order bandpass [Sigma] [Delta] modulator is proposed to digitize signals from a MEMS gyroscope. The modulator samples the amplitude-modulated signal at eight times the carrier frequency and achieves an SNR of 82dB with a sampling frequency of 640kHz and a bandwidtn o 1.oKnz. ms document snows that bandpass [Sigma] [Delta] modulation offers the advantage of a high oversampling rate without the need to demodulate the signal for lowpass [Sigma] [Delta] modulation.
by Stephanie C. Hsu.
M.Eng.

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Simic, Emilija. "A bandpass sigma delta modulator IF receiver." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/43475.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
Includes bibliographical references (leaves 170-173).
by Emilija Simic.
M.Eng.

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TAFAZOLI, MEHRJERDI MOHAMAD. "ALL-OPTICAL DELTA-SIGMA MODULATOR DESIGN AND IMPLEMENTATION." OpenSIUC, 2015. https://opensiuc.lib.siu.edu/dissertations/1116.

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In this research an approach to design and implement all-optical delta-sigma modulator (ODSM) has been expanded. The two main blocks of this modulator are “leaky integrator” and “bi-stable switch” designed and implemented by using active element like semiconductor optical amplifier (SOA) and other passive elements like optical filter, isolator and coupler. All experiments are done on optical table and proper results achieved. Thus the new bi-stable switch is designed and implemented by using “inverted bistable switch” and “non-inverted bi-stable switch”. This switch is made by five ring lasers. Right wavelengths have chosen for each ring laser to achieve a novel characteristic called “Proteresis”. All control parameters of this switch was investigated The major impact of this research will be in the area communication system, which need high resolution and fast modulation speed with less noise in their systems.

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Althomali, Raed. "THEORETICAL INVESTIGATION AND PERFORMANCE ASSESSMENT OF REVERSED HYSTERESIS DELTA SIGMA MODULATOR DESIGN." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/794.

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This dissertation studies a unique delta sigma modulator (DSM), known as reversed hysteresis delta sigma modulator (R-HDSM). This modulator is appropriate for ultra-high speed analog-to-digital converters, which can be used for communications and signal processing systems and their applications. Furthermore, the procedure to design the binary delta sigma modulator (BDSM) with a delay is developed and then parameters deltaOFF and deltaON ; are calculated for the system. In addition, analysis of the BDSM with a delay is achieved and the theoretical and simulated values compared. The reversed hysteresis delta sigma modulators are also analyzed, and the theoretical and the simulated values compared. The dissertation evaluates the performance measure for the suggested systems with continuous DSM and BDSM in terms of the spurious free dynamic range (SFDR), the signal to noise ratio (SNR), and the root mean square error (RMS). It studies the second-order R-HDSM. Finally, it compares the first-order R- HDSM and the second-order R-HDSM in terms of the signal to noise ratio (SNR).

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Allen, Daniel J. "A programmable delta-sigma modulator using floating gates." Thesis, Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-03292004-141813/unrestricted/allen%5Fdaniel%5Fj%5F200312%5Fms.pdf.

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Jonsson, Fredrik. "Ultra Wide Band Sigma-Delta modulator in CMOS090." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2172.

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Today the frequency spectrum is full of wireless standards. The most common technique being used is the frequency modulation. To take advantage of this and the technology improvement a new wireless communication standard is being developed. This standard is using a low power impulse modulation method, allowing it to overlap with other standards. The proposed standard called IEEE802.15.3a is applied at an Ultra Wide Band and has potential to be used both in interchip and intrasystem communication, since it allows a very high data density.

In this thesis the analog to digital converter is designed, which is one part of a communication system. Although the signal bandwidth is very wide the converter is designed as a Sigma-Delta modulator, which is most suitable for low-speed applications. Its main advantages over high-speed converters are less area and less power consumption. The goal of this project is to investigate if the CMOS090 process technology will be sufficient for reaching a signal-to-noise ratio, SNR, of 30 dB in a signal band of 264 MHz.

The main limiting factor during the design of the modulator is the excess feedback delay. This delay degrades the SNR and can even make the system unstable. At a feedback delay of 83 ps and a sampling frequency of 6.336 GHz, the maximum SNR achieved was 27 dB. At this high frequency the modulator is close to instability. Hence, to ensure stability a maximum sampling frequency of 4.224 GHz is chosen, achieving a SNR of 19 dB.

The effect of the feedback delay can be reduced either by using a different structure or by using compensation methods, either of them would probably allow a SNR above 30 dB.

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Baskaran, Balakumaar, and Hari Shankar Elumalai. "High-Speed Hybrid Current mode Sigma-Delta Modulator." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80060.

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The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. Analog to Digital Converter (ADC), converts the continuous time signal to the discrete time signal. Most A/D converters are classified into two categories according to their sampling technique: nyquist rate ADC and oversampled ADC. The nyquist rate ADC operates at the sample frequency equal to twice the base-band frequency, whereas the oversampled ADC operates at the sample frequency greater than the nyquist frequency. The sigma delta ADC using the oversampling technique provides high resolution, low to medium speed, relaxed anti-aliasing requirements and various options for reconfiguration. On the contrary, resolution of the sigma delta ADC can be traded for high speed operation. Data sampling techniques plays a vital role in the sigma delta modulator and can be classified into discrete time sampling and continuous time sampling. Furthermore, the discrete time sampling technique can be implemented using the switched-capacitor (SC) integrator and the switched-current (SI) integrator circuits. The SC integrator technique provides high accuracy but occupies a larger area. Unlike the SC integrator, the SI integrator offers low input impedance and parasitic capacitance. This makes the SI integrator suitable for low supply voltage and high frequency applications. From a detailed literature study on the multi-bit sigma delta modulator, it is analyzed that, theneeds a highly linear digital to analogue converter (DAC) in its feedback path. The sigma delta modulators are very sensitive to linearity of the DAC which can degrade the performance without any attenuation. For this purpose T.C. Leslie and B. Singh proposed a Hybrid architecture using the multi-bit quantizer with a single bit DAC. The most significant bit is fed back to the DAC while the least significant bits are omitted. This omission requires a complex digital calibration to complete the analog to digital conversion process which is a small price to pay compared to the linearity requirements of the DAC. This project work describes the design of High-Speed Hybrid Current modeModulator with a single bit feedback DAC at the speed of 2.56GHz in a state-of-the-art 65 nm CMOS process. It comprises of both the analog and digital processing blocks, using T.C. Leslie and B. Singh architecture with the switched current integrator data sampling technique for low voltage, high speed operation. The whole system is verified mathematically in matlab and implemented using signal flow graphs and verilog a code. The analog blocks like switched current integrator, flash ADC and DAC are implemented in transistor level using a 65 nm CMOS technology and the functionality of each block is verified. Dynamic performance parameters such as SNR, SNDR and SFDR for different levels of abstraction matches the mathematical model performance characteristics.

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Ouyang, Jingwen M. Eng Massachusetts Institute of Technology. "A Comparator-Based Switched-Capacitor delta sigma modulator." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/61249.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2010.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 81).
Comparator-Based Switched-Capacitor (CBSC) is a relatively new topology that replaces op-amps in sampled-data systems with a comparator and a set of current mirrors. CBSC is expected to lower power consumption, and to avoid several delicate tradeoffs of op-amp circuits. In this paper, the original single-ended CBSC block is extended to a fully differential version. The differential CBSC is then applied to an industrial standard second order delta-sigma modulator originally based on op-amps. Due to the differences between CBSC and op-amp, a few architectural changes are necessary for the original modulator. Finally, the performance of transistor level simulation of this CBSC based modulator is evaluated.
by Jingwen Ouyang.
M.Eng.

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Zhang, Yue. "A fourth order current-mode sigma-delta modulator /." free to MU campus, to others for purchase, 1997. http://wwwlib.umi.com/cr/mo/fullcit?p9841350.

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Aizad, Noor. "Design and implementation of comparator for sigma delta modulator." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6965.

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Comparator is the main building block in an ADC architecture. Main purpose of the comparator is to compare a signal with a reference signal and produce an output depending on whether the input signal is greater or smaller than reference. Many architectures for comparators exist for various purposes. In this thesis, Latched comparator architecture is used for sigma delta modulator. This particular design has two main characteristics that are very important for sigma delta application. First characteristic is the cancellation of memory effect which increases the speed and reliability of the system and the second is, with this architecture, high sensitivity can be achieved.

The design and implementation of lathed comparator for sigma delta modulator is presented in this thesis work. Various non-linearities and performance parameters are discussed in detail. Practical implementation and circuit design issues are highlighted to achieve maximum sensitivity along with reasonable speed and accuracy.

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Pedersen, Trond Jarle. "Automated Self-Test of an Analog Delta-Sigma Modulator." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2007. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-16752.

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This project investigates the feasibility of automating the test of ΔΣ-modulators using circuitcomponents available on 8-bit microcontrollers, and by doing so reducing test costs.A Built-In-Self-Test (BIST) scheme, using a binary stream as stimuli and two differentsolutions for signal analysis is suggested and simulated in SPICE to investigate its suitability.The test can not lead to a large area increase, increasing area leads to an increase inproduction cost. The test has to reduce testing time. The extra area occupied by the testarchitecture has to be paid in shorter testing time and therefore a lower unit price. The test hasto remove or lower the requirements of the off-chip tester, and by doing so reducing cost.The proposed BIST requires a very small area and is capable of calculating offset, gain andSignal to Noise Ratio with a high degree of accuracy. The proposed solution enables on-chiptesting without the need for expensive external stimuli and signal analyzers, making testing onwafer possible thus improving production yield.The proposed test will not reduce test time by itself, however by integrating the test on-chipand allowing this to run in the background while other on-chip modules are tested total testtime can be reduced to the time required to shift the stimuli into the chip

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Çoban, Abdulkerim Levent. "A low-voltage high-resolution audio delta-sigma modulator." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/15514.

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Sukhon, Mohammad. "Double-sampled digital-feedforward second-order delta-sigma modulator." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=32527.

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A 12-bit 2.8-MHz delta sigma modulator intended for ADSL applications is presented in this thesis. The design process evolved over two stages, namely, a system-level design stage followed by a circuit-level design stage. During the first phase of the design, the systemlevel parameters are selected and analog-circuit specifications are derived. The circuitlevel stage involved the design of analog circuitry such as operational amplifiers capable of meeting the system-level specifications. The circuit design was carried out in 1-V 65- nm CMOS technology. Double-sampling was employed to make the switched-capacitor circuits more power efficient. Input-signal feedforward was used to lower the signal swing at the output of the opamps. Digital input feedforward is used and presented as an alternative to analog input feedforward.
Un modulateur delta sigma 12-bit 2.8-MHz conçu pour des applications ADSL est présenté dans ce mémoire. Le processus de conception est décrit en deux phases: la conception au niveau du système suivie de la réalisation au niveau du circuit. Lors de la première phase, les paramètres du système sont choisis et les spécifications analogiques du circuit sont dérivées. La phase de l'implémentation du circuit impliquait la conception de circuits analogiques tels que amplificateurs opérationnels respectant les spécifications du système. La conception du circuit a été réalisée sur la technologie 1-V 65-nm CMOS. Le doubleéchantillonnage a été employé afin que les circuits de condensateurs-commutés soient plus économiques en terme de puissance. La technique d'action directe (feedforward) a été utilisée sur le signal d'entrée afin de réduire l'amplitude à la sortie des amplificateurs. La technique d'action directe digitale sur le signal d'entrée est utilisée et présentée comme une alternative à son homologue analogique.

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Chandra, Naveen. "A top-down approach to delta-sigma modulator design /." Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=32955.

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This work presents the use of a new design methodology for the creation of analog integrated circuit components featuring optimization with Matlab and Simulink. This procedure allows circuit design to take place at the highest level of abstraction, and has the added advantage that designs can be implemented with currently used, and widely available tools. It results in building block requirements being specified prior to the undertaking of transistor level simulations, thereby saving much valued design time.
Also presented are the issues behind the design of an audio-band, single bit switched capacitor delta-sigma modulator with 16 bits of performance. This begins with the filtering function design, continues with the realization in a low voltage standard CMOS process, and concludes with experimental measurements to gauge performance. The creation of the modulator was carried out using the proposed top-down design methodology, and its experimental performance is used to help validate the procedure.
In addition, the design and fabrication of a multibit DeltaSigma modulator including a novel internal DAC was carried out. The multibit DAC is based on encoding DC levels into digital PDM bitstreams, which are then decoded by a single analog filter. The use of a single filtering path reduces mismatch effects in the DAC. The functionality, performance, and limitations are explored by examining the experimental results of a 2.5 V, audio-band, 2nd order, 3-bit DeltaSigma modulator in a 0.25 mum CMOS process.

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Kwan, Hing-kit, and 關興杰. "Design algorithms for delta-sigma modulator loop filter topologies." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B4150883X.

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Yang, Xi S. M. Massachusetts Institute of Technology. "Design of a continuous-time bandpass delta-sigma modulator." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/87939.

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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 103-105).
An 8th-order continuous-time (CT) bandpass delta-sigma modulator has been designed and simulated in a 65 nm CMOS process. This modulator achieves in simulation 25 MHz signal bandwidth at 250 MHz center frequency with a signal-to- noise ratio (SNR) of 75.5 dB. The modulator samples at 1 GS/s while consuming 319 mW. On the system level, the feedback topology secures stability for the 8th-order system, achieving a maximum stable input range of -1.9 dBFS. A 2.5-V/1.2-V dual-supply loop filter with a feed-forward coupling path has been proposed to suppress noise and distortion. On the transistor level, a 5th -order dual-supply feed-forward operational amplifier (op amp) and a 4th-order single-supply feed-forward op amp have been designed to enable high modulator linearity and coefficient accuracy.
by Xi Yang.
S.M.

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Syed, Azeemuddin. "Implementation of binary delta sigma modulator using ring lasers /." Available to subscribers only, 2008. http://proquest.umi.com/pqdweb?did=1594486401&sid=4&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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Kwan, Hing-kit. "Design algorithms for delta-sigma modulator loop filter topologies." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B4150883X.

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Tam, Yiu-Ming. "A tri-mode sigma-delta modulator for wireless receivers /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20TAM.

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Ghandoura, Abdulrahman M. "PROTERETIC OPTICAL BINARY DELTA-SIGMA MODULATOR USING RING LASER." OpenSIUC, 2018. https://opensiuc.lib.siu.edu/dissertations/1571.

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This dissertation concentrates on the investigation and design a new model and implementing of Optical Binary Delta-Sigma Modulator (Proteretic Switch) to improve the bandwidth limitation toward THz modulation frequency in the optical domain. The presented design of Proteretic Optical Binary Delta-Sigma Modulator contains two essential components, the leaky integrator and inverted bi-stable device with positive feedback which were designed and implemented according to the switching performance, to reach higher frequency by using ring laser technology, and semiconductor optical amplifier (SOA) based on cross-gain or phase gain modulation. All optical devices have been tested through VPI photonics circuit maker application, which could be fabricated on a single integrated photonic chip. The new bi-stable switch “Proteresis” model using active elements such as semiconductor optical amplifier (SOA) and passive elements such as optical bandpass filter, optical isolator, and coupler. The bi-stable switch “proteretic” properties model and parameters are studied, and simulation tested to confirm its performance. The contribution of this dissertation can help the communication technology that needs high-speed signal processing, high resolution, less noise, and the design showed the capability of achieving this objective.

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Zhong, Ming Carleton University Dissertation Engineering Electrical. "A 3[mu] m [sigma-delta] modulator and dual modulus divider for use in [sigma-delta] modulated fractional-n frequency synthesis." Ottawa, 1991.

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Svensson, Hanna. "Study on a second-order bandpass Σ∆-modulator for flexible AD-conversion." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12105.

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An important component in many communication system is the digital to analog converter. The component is needed in order to convert real world analog quantities to digital quantities which are easier to process. As the market for hand held devices with wireless communication with the outer world has increased new approaches for sharing the frequency spectrum are needed. Therefore it would be interesting to look at the possibility to design an analog to digital converter that, in runtime, can change the frequency band converted, and hence the used standard. This thesis study one of the possibilities to design such an ADC, as a Σ∆ modulator, and more precise the structure called Cascade of resonators with distributed feedback and input (CRFB). The order of the modulator in this study is two.

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Ucar, Alper. "A subsampling delta-sigma modulator for global navigation satellite systems." Thesis, University of Westminster, 2010. https://westminsterresearch.westminster.ac.uk/item/9018w/a-subsampling-delta-sigma-modulator-for-global-navigation-satellite-systems.

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Next-generation Global Navigation Satellite Systems (GNSS) receivers should be capable of processing multi-frequency signals in order to provide better positioning accuracy and signal availability to end-user. Nevertheless, the realization of such receivers with conventional receiver architectures leads to power-hungry devices and hinders monolithic integration of the receiver. Multi–frequency receivers can be realized with lower power and cost by performing sub-Nyquist sampling (subsampling) at Radio Frequency (RF). In practice, the use of subsampling receivers has been limited due to their poor noise performance. This is particularly a concern in applications of Code Division Multiple Access (CDMA) such as GNSS since subsampling may saturate the Analog-to-Digital Converter (ADC) as the thermal noise floor is above the signals of interest. Continuous-Time (CT) Delta-Sigma (ΔΣ) modulation is an attractive candidate for subsampling Analog-to-Digital (A/D) conversion as it provides noise-shaping and inherent Anti-Alias (AA) filtering. However, the attenuation of the RF alias in the feedback path of the modulator and the reduction of the effective Quality (Q-factor) of the loop filter prevent conventional CT-ΔΣ modulators to be utilized in subsampling receivers. This thesis proposes a novel CT-ΔΣ modulator at both the system and the circuit level that is capable of compensating for the effects of subsampling. These are achieved by modifying the feedback path of the conventional modulator architecture to accommodate for the RF alias and by enhancing the Q-factor of the loop filter. The proposed CT-ΔΣ has significant improvements over previously published subsampling modulators as it provides jitter and alias suppression and excess loop delay compensation to improve the dynamic range, thus enabling the modulator to be utilized in subsampling receivers when a relatively low sampling rate is desired. Based on the novel CT-ΔΣ modulator, this thesis also proposes a subsampling receiver architecture for multi-constellation GNSS applications. Simulations results indicate that the proposed receiver architecture can successfully acquire and track the civilian radionavigation signals with a high performance.

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Kode, Praveena. "Design techniques for high intermediate frequency bandpass (sigma/delta) modulator." Texas A&M University, 2008. http://hdl.handle.net/1969.1/86025.

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The focus of the present thesis is the circuit-level implementation of an excess loop delay compensation scheme which optimizes excess loop delay in Analog-to-Digital Converter(ADC) by using a programmable delay block and synchronizes the signal passing through Dynamic Element Matching block, used to mitigate mismatch effects of multi-bit Digital-to-Analog Converter(DAC). The proposed delay block has tuning range of T/10 to T/2 seconds, with a step size of T/30 seconds, where T is the time period (1.25 nanoseconds) of sampling signal (800 MHz) in high IF (200 MHz) Bandpass [sigma delta] ADC. The implementation details of the element rotation scheme used to calibrate the multi-bit DAC static error mismatch are also presented. Also presented is the design of high frequency highly linear Operational Transconductance Amplifier(OTA) targeted for continuous-time filters in a high resolution High Intermediate Frequency (200 MHz) Bandpass [sigma delta] ADC for Software Radio applications. Proposed OTA uses super source follower input stage to enhance its voltage-to-current conversion linearity. The design has been simulated using TSMC 0.18 μm CMOS process. The OTA has small signal transconductance of 0.9 mA/V, IM3 below -79 dB (for 0.3 Vpp input), Signal-to-Noise Ratio of 82 dB and power consumption of 6.8 mW, when tested in unity gain configuration.

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Ma, Stanley Jeh-Chun. "A low-power low-voltage second-order [Sigma Delta] modulator." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0028/MQ34136.pdf.

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Ding, Chongjun [Verfasser], and Yiannos [Akademischer Betreuer] Manoli. "Design study of high-speed continuous-time delta-sigma modulator." Freiburg : Universität, 2016. http://d-nb.info/1122647026/34.

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Puskarich, John Gerard. "An improved sigma-delta modulator for digitizing carrier band measurements." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/33334.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 97-99).
Draper Laboratory currently employs a third-order Sigma-Delta modulator to digitize the outputs from microelectromechanical sensors at the intermediate frequency prior to demodulation inside a field programmable gate array. This modulator, which is built on a .5[mu]m CMOS process, is to be used as a standalone chip or as a core for use in larger microelectromechanical sensor integrated circuits. In this document, I submit the design of an improved Sigma-Delta modulator, which has a noise floor of 40nV/ [square root of] Hz and a 5Vpp input range.
by John Gerard Puskarich.
M.Eng.

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楊淳皓. "Low Distortion Delta-Sigma Modulator." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/44740898799341638636.

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碩士
國立清華大學
電子工程研究所
95
Regarding the requirements for portable multi-media applications, it is concerned with high resolution A/D and low power consumption. Oversampling techniques based on delta-sigma modulation were widely used to implement the digital audio applications. This type of systems requires high dynamic range (i.e., 14~20bit) at bandwidth of 20khz. In this thesis, the third order low distortion modulator was designed to achieve the front interface of delta-sigma data converter. By using the characteristics of system to relax the operation amplifier specification. This modulator was integrated in TSMC 0.35 m CMOS technologies. The simulation result could be achieved a peak SNR of 86dB with signal bandwidth 20khz and oversampling ratio of 64. The power consumption was 5.54mW under normal condition.

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Hsieh, Chung-Ming, and 謝仲銘. "Sigma Delta Modulator Design Automation." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/gvcyxs.

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碩士
國立臺北科技大學
電腦與通訊研究所
95
Sigma Delta Modulator Design Automation from system to circuit is presented in this paper. The sigma delta modulator design flow can be separated into the system and circuit level design. It often adopts Matlab Simulink for the system level design and utilizes circuit simulator like Hspice or Spectre for the circuit level design. We propose a methodology which is realized by a script language PERL to control and link all these simulation tools. For the purpose of the automation, we also applied simulated annealing algorithm to optimize the system parameters in the script. 　　We have successfully implemented this automation flow for the switched-cap third-order feedback single loop single bit with the simulated annealing algorithm. The final SNDR of the automatically designed SDM ADC shows up to 87dB. Besides, this methodology can be applied to any architecture of the sigma delta modulators only if the system is modeled well in Matlab Simulink. Finally we compare with the results of a man designed low power low voltage SDM and the automation designed.

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34

Thomas, Daniel E. "Fast opamp-free delta sigma modulator." Thesis, 2001. http://hdl.handle.net/1957/29055.

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Switched-capacitor (SC) circuits are commonly used for analog signal processing because they can be used to realize precision filters and data converters on an integrated circuit (IC). However, for high speed applications SC circuit operating speeds are limited by the internally-compensated opamps found in SC integrators, a common building block of these circuits. This thesis studies gain stages that eliminate the internal compensation, thus allowing the SC circuits to operate at significantly higher operating speeds. An inverter-based SC integrator is presented. The proposed SC integrator is built with a pseudo-differential structure to improve its rejection of common-mode noise, such as charge injection and clock feedthrough. The proposed integrator also incorporates correlated double sampling (CDS) to boost its effective DC gain. Clock-boosting and switch bootstrapping techniques are not used in the proposed circuit, even though it uses a low supply voltage. To verify the speed advantage of the proposed circuit, a high speed delta sigma (Δ∑) modulator was designed in a 1.8V, 0.18μm CMOS technology. The designed Δ∑ modulator operates at a clock frequency of 500MHz. Circuit implementation and layout floorplan are described. The design is based on MATLAB and SpectreS simulations.
Graduation date: 2002

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35

Chen, Wei-Xian, and 陳威憲. "Fault Diagnosis for Delta-Sigma Modulator." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/22111101988478428648.

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碩士
國立交通大學
電子工程系所
93
In this thesis, we proposed a new test method to diagnose faults in the delta-sigma modulator by measuring output voltage of integrator without input test pattern. The theoretical and simulation results show that this method has a very high accuracy to determine operation amplifier offsets and capacitor ratios even when the circuit has multiple faults. Finally, we present an application of the delta-sigma modulator circuit as a code edge measurement circuit for DAC. It uses delta-sigma modulation property to accurately measure a DC voltage level which could be the output of a DAC-under-test by observing the output of the PCM code. Experimental results on an implemented circuit with UMC0.18 technology show that it can give this measuring circuit a 9-bits resolution for the DAC code edge. We also supply improved method can be effectively increased the resolution by connecting an amplifier stage at the output of the DAC-under-test.

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36

Tsai, Yi-Chieh, and 蔡一傑. "MATLAB-assisted Delta-Sigma Modulator Design." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/98639000345832836531.

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碩士
國立高雄海洋科技大學
微電子工程研究所
103
In this paper, By systematic adjusting model parameter values of delta-sigma modulator and feedback loop variables provided in the MATLAB toolbox, one can easily design a reasonably robust first order Δ-Σ modulator using TSMC 0.18μm technology. A modulator based on T-switch OTA (Operational Transconductance Amplifier) and dual power supplies (VDD = ± 0.9V) was designed. OTA simulated results show room temperature DC gain = 75dB, Phase Margin (PM) = 67∘, Unity Gain Band Width (UGBW) = 109 MHz and Common Mode Rejection Ratio (CMRR) = 108 dB. MATLAB was then used to read in HSPICE simulated modulator results and calculate signal-to-noise ratio. It was found that with the Oversampled Ratio (OSR) = 32, the achievable simulated Signal to Noise and Distortion Ratio (SNDR) = 54 dB and Power Dissipation = 1.1 mW, in contrast to measured results of SNDR = 25dB and power consumption = 2.1mW. The discrepancy is due mainly to the chip doesn't have nonoverlapping circuit when tapeout. we used OPA to design inverse signal for sampling frequency. Resulting in inaccurate sampling frequency . Note that both measured and simulated input signal frequency = 2.56KHz and bandwidth = 20KHz.

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LIN, CHIEN-HAO, and 林建豪. "VerilogA-assisted Delta Sigma Modulator design." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/15232333003441053572.

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碩士
國立高雄海洋科技大學
微電子工程研究所
103
As transistor numbers increases in a mixed-mode delta sigma modulator design, the HSPICE simulation time would also grows. In a typical first-order circuit-based Modulator with high oversample rate, the simulation time might take several hours. In order to speed up the overall design efficiency, we first utilize Verilog-based behavioral modeling approach to construct ideal modeling blocks to mimic real modulator operation. Each individual Verilog-A blocks was then turned into real circuit blocks using HSPICE sub-circuits. In the final design and validation steps we can easily replace ideal design blocks (Verilog-A blocks) with HSPICE sub-circuits and see how the overall output spectrum degrades as more ideal blocks was replaced. A first-order delta-sigma modulator was designed using approach described above and TSMC 0.18um technology. Simulated results show for a 20kHz input signal, bandwidth = 20 kHz and oversampled ratio = 32, the achievable SNDR = 43 dB, that is equivalent to ENOB = 7 bits with average power consumption = 0.38mW, in contrast to measured results of SNDR = 21.4 dB and power consumption = 0.41mW. The discrepancy is due mainly to the Sample Signal is too close Analog input Signal. It Cause that Analog Signal suffered to strong interference. We note that similar design approach can be used to construct higher-order delta-sigma modulator .

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38

Hung, Yang-Cheng, and 洪揚程. "Generalization of Discrete-Time Sigma-Delta Modulator Non-Ideality Power Models to Various Sigma-Delta Modulator Architectures." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/68049481827279158962.

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碩士
國立交通大學
電控工程研究所
100
The conventional high-level ΣΔM synthesis is mainly based on behavior simulation which is very time-consuming. Thus we propose model-based high-level ΣΔM synthesis. Model-based approach can be at the order of 104 times faster than simulation-based approach. Model-based method employs only mathematical models, which is set of ΣΔM non-ideality power models. Thus, the completeness of non-ideal power models is a must when we use model-based method to design ΣΔM. In this paper, major non-ideality power models of 2nd-order ΣΔM are discussed, and generalizations of those non-ideality power models to various ΣΔM topologies are also discussed. In addition, continuous-time ΣΔM is discussed in this paper, which incorporates comparison between discrete-time, continuous-time ΣΔM and loop filter design of continuous-time ΣΔM, and continuous-time ΣΔM behavioral model in MATLAB-Simulink environment.

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39

Behera, Khitish Chandra. "A Novel Higher Order Noise Shaping Sigma-Delta Modulator." Thesis, 2008. https://etd.iisc.ac.in/handle/2005/712.

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The thesis focuses on a higher order noise-shaping Δ ADC architecture which employs filtered quantization error as a dither signal. Furthermore, the work studies implementation challenges using Switched-Capacitor and Switched-Current techniques. Digitization in an IF conversion receiver can be accomplished either with a wide band Nyquist rate ADC or a BandPass Δ ADC. The use of the latter is the optimum solution since the bandwidth of the IF signals is typically much smaller than the carrier frequency and reducing the quantization noise in the entire nyquist band becomes superfluous. Instead by using BandPass Δ ADCs the quantization noise power is reduced only in a narrow band around IF location. We study state-of-the-art high dynamic range Δ data converter topologies suited for wide-band radio receivers. We propose a topology which achieves higher order noise shaping by employing filtered quantization error as a dither signal. We study implementation challenges for Δ converters in digital technology. Traditionally, Δ ADCs used Switched-Capacitor (SC) circuits to realize their building blocks. This analog sample-data technique is based on the idea that a periodically switched capacitor can emulate a resistor. The limiting factor that degrades the performance of SC circuits implemented in standard VLSI technologies is the continuous reduction of supply voltages, prompted by the continuous scaling-down process. This fact, which is advantageous for digital circuitry, makes the design of SC circuits difficult, which are forced to use clock boosting strategies for switches and to increase the power consumption in order to obtain high-speed and high dynamic range opamps with low voltage operation. In this scenario, the use of current-domain sampled data technique, also named Switched-Current (SI), instead of voltages results advantageous for several reasons. As the signal carriers are currents, the supply voltage does not limit the signal range as much as in SC circuits. Therefore, SI circuits are more suitable than SC for low-voltage operation. This work studies the feasibility and bottlenecks of implementing Δ modulator building blocks using SI technique. A BandPass filter, DAC and 1-bit quantizer have been designed in 0.18µm technology using SI technique. (For mathematical equations pl refer the pdf file)

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40

Behera, Khitish Chandra. "A Novel Higher Order Noise Shaping Sigma-Delta Modulator." Thesis, 2008. http://hdl.handle.net/2005/712.

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The thesis focuses on a higher order noise-shaping Δ ADC architecture which employs filtered quantization error as a dither signal. Furthermore, the work studies implementation challenges using Switched-Capacitor and Switched-Current techniques. Digitization in an IF conversion receiver can be accomplished either with a wide band Nyquist rate ADC or a BandPass Δ ADC. The use of the latter is the optimum solution since the bandwidth of the IF signals is typically much smaller than the carrier frequency and reducing the quantization noise in the entire nyquist band becomes superfluous. Instead by using BandPass Δ ADCs the quantization noise power is reduced only in a narrow band around IF location. We study state-of-the-art high dynamic range Δ data converter topologies suited for wide-band radio receivers. We propose a topology which achieves higher order noise shaping by employing filtered quantization error as a dither signal. We study implementation challenges for Δ converters in digital technology. Traditionally, Δ ADCs used Switched-Capacitor (SC) circuits to realize their building blocks. This analog sample-data technique is based on the idea that a periodically switched capacitor can emulate a resistor. The limiting factor that degrades the performance of SC circuits implemented in standard VLSI technologies is the continuous reduction of supply voltages, prompted by the continuous scaling-down process. This fact, which is advantageous for digital circuitry, makes the design of SC circuits difficult, which are forced to use clock boosting strategies for switches and to increase the power consumption in order to obtain high-speed and high dynamic range opamps with low voltage operation. In this scenario, the use of current-domain sampled data technique, also named Switched-Current (SI), instead of voltages results advantageous for several reasons. As the signal carriers are currents, the supply voltage does not limit the signal range as much as in SC circuits. Therefore, SI circuits are more suitable than SC for low-voltage operation. This work studies the feasibility and bottlenecks of implementing Δ modulator building blocks using SI technique. A BandPass filter, DAC and 1-bit quantizer have been designed in 0.18µm technology using SI technique. (For mathematical equations pl refer the pdf file)

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41

Dalal, Vineet R. "A switched-current bandpass delta-sigma modulator." Thesis, 1993. http://hdl.handle.net/1957/35637.

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42

Chia-Hau, Chang. "A 4th-Order Bandpass Sigma-Delta Modulator." 2001. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611313966.

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Chang, Chia-Hau, and 張家豪. "A 4th-Order Bandpass Sigma-Delta Modulator." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/53026796264779690882.

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碩士
元智大學
電機工程研究所
89
This paper presents a 4th-order bandpass sigma-delta oversampling modulator, which can be used in the digital wireless communication receiver. It converts analog signals to the digital domain at the intermediate frequency. The modulator is implemented in the UMC 0.5μm CMOS 2p2m process with power supply ±2.5V. The bandwidth is 200kHz centered at the 5Mhz.The sample frequency is 20MHz. The peak SNR is about 65 dB. The power consumption is 179.3mW. The modulator layout area is 792um*1076um. The chip area is 1800um*1800um。

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44

Tai, Pong-Kit, and 戴邦傑. "Sigma-Delta Modulator for Biomedical Signal Processing." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/08629449935241551547.

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碩士
國立中央大學
電機工程研究所碩士在職專班
99
Abstract Recently, the rapid expansion of the biomedical-electronic market has necessitated low-power and low-voltage biomedical systems [1], [2]. Since battery power is used for most of the portable biomedical devices. Expanding battery lifetime through the topology of low power dissipation systems is very crucial. In the digital hearing-aid applications, the battery is typically made of zinc–air and should offer a life span of at least two weeks at 10 hours use per day [3]. Moreover, the digital hearing aid requires wide dynamic range, high performance, more programmability, and small form factor. Hence, it is necessary to achieve low power dissipation, high performance, and programmability to expand battery lifetime and to offer convenient hearing to the users. Due to low-amplitude and non-stationary properties of biomedical signals, high resolution and low-power consumption are necessary for the analog-to-digital (A/D) convector (ADC). Sigma-Delta Modulator has good performance in the resolution and power consumption. In this thesis, Sigma-Delta Modulator (SDM) for a biomedical electronic system is proposed. Basically, the switched-capacitor (SC) technique and the Feedforward(FF) technique can be used to implement SDM. The proposed SDM was simulated with TSMC 0.18 ?m 1P6M CMOS technologies. The signal bandwidth is 10 KHz and its clock rate is 2.56 MHz i.e. the over-sampling ratio (OSR) is equal to 128. Hence, it can achieve 75.75 dB signal-to-noise and distortion ratio (SNDR), and higher than 10 bits resolution in 2nd orders SDM. Moreover, the power consumption is about 358 ?W in 12 bits resolution under normal operation and the dynamic range is 85 dB with a single 1.8V power supply. Basically, an SDM ADC consists of an Analog SDM and Digital Decimation filter. Therefore, we can take the advantage of low power consumption of the implanted SDM to integrate two SDM adaptively with one digital decimation filter. Then we can easily to monitor 1 or 2 biomedical signals at the sample time and save the total chip area.

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45

chen, Yan-chen, and 鄭彥誠. "Switched-capacitor second-order Sigma-Delta modulator." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/qakd3s.

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碩士
國立臺灣科技大學
電子工程系
94
Oversampling techniques based on delta-sigma modulation are widely used to implement the interface between analog and digital signals in VLSI systems, such as digital audio systems. This type of systems requires a large dynamic range (i.e., about 16 ~ 20 bits) at low-frequency bandwidth of 20 kHz. The delta-sigma modulation approach is relatively insensitive to imperfections in circuit components and offers numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters. In particular, oversampling architectures is a potentially power-efficient means of implementing high-resolution A/D converters because they reduce the number and complexity of the analog circuits in comparison Nyquist-rate converters. Furthermore, they allow the performance requirements, and thus most of the power dissipation, to be concentrated in the input stage of a converter. For a multibit ΔΣ modulator, the performance is directly related to the linearity of the internal multibit DAC in the feedback path. Various dynamic element-matching techniques have been proposed to circumvent the nonlinearity of the internal DAC. By using these techniques, the DAC noise is also shaped like quantization noise in delta-sigma modulators. This thesis describes the results of research into the design of the oversampling one-level delta-sigma modulators implemented by switch-capacitor circuits, digital audio applications. The experimental modulators described herein can deliver a high dynamic range over a 20 kHz bandwidth and have been fabricated in standard 0.35 μm CMOS technologies.

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46

Chen, Chin-Hsun, and 陳錦勳. "Oversampling with Second-Order Sigma-Delta Modulator." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/46209859353866805603.

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碩士
國立聯合大學
電子工程學系碩士班
94
The analog-to-digital converter (ADC) which provides the link analog signal between digital signal. An analog-to-digital converter has many applications likes sensor, voice etc. In this thesis, we present a second-order sigma-delta modulator analog-to-digital converter (SDM-ADC or ∆Σ ADC) for sensor application. This ∆Σ ADC has been designed with fully-differential switch-capacitor (SC) integrator and implemented with folded-cascode operation amplifier. The operation of this converter is single 3V power supply. The modulator achieves that peak Single-to-Noise Ratio (SNR) is about 66dB, dynamic range (DR) is 67dB under the condition that oversampling ratio (OSR) is 128. This modulator has been designed in the technology of TSMC 0.35µm 2P4M standard CMOS logic process and the active area is 628µm × 1006µm.

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47

Chen, Chih-hung, and 程智鴻. "1MHz Bandwidth Switched-Current Sigma Delta Modulator." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/84377117324293563830.

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碩士
國立中山大學
電機工程學系研究所
99
The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to pull down the input impedance and get high speed and high resolution. Oversampling and noise shaping are the two keys of Sigma Delta modulator. In structure, multistage is helpful for depressing noises and we use three stages to fulfill this 4-order proposed Sigma Delta modulator. The proposed Sigma Delta modulator uses TSMC 0.18μm CMOS process and it is a 4-order and three stages SI Sigma Delta modulator. The sampling rate is 32MHz, bandwidth is 1MHz, and oversampling ratio is 16.

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48

Lu, Cho-Ying. "Calibrated Continuous-Time Sigma-Delta Modulators." 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7914.

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To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry.

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49

Shen, Yi-Luen, and 沈逸倫. "THE DESIGN AND SIMULATION OF A 4-CHANNEL SI PARALLEL DELTA-SIGMA MODULATOR WITH A FOURTH-ORDER DELTA-SIGMA MODULATOR." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/84035341623729632713.

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碩士
大同工學院
電機工程研究所
87
Delta-Sigma modulation is a technique that is effective for the high resolution A/D conversion and tolerant for the process imperfection. Unfortunately, the need for high oversampling in Delta Sigma A/D converters has limited their use to primarily low -frequency applications. Parallel Delta Sigma modulators present an architecture wherein multiple Delta Sigma modulators are combined so that time oversampling is not necessary. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators. In this thesis, the resolution for four-channel and eight-channel Pi Delta Sigma modulators with first-, second- and fourth-order Delta Sigma modulators where sixteen times oversampling were measured. Additionally, the integrator of the modulator is made of the switched-current integrator. The design procedures and switched-current implementation are also provided. The modulator has been simulated by MATLAB and HSPICE (using UMC 0.5 um CMOS process parameters). The result shows that the four-channel Pi Delta Sigma modulator with a fourth-order Delta Sigma modulator and an oversampling ratio of 16 can achieve a signal-to-noise ratio of 71 dB.

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50

Pulincherry, Anurag. "A continuous time frequency translating delta Sigma Modulator." Thesis, 2002. http://hdl.handle.net/1957/30250.

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This thesis presents a continuous time bandpass delta sigma modulator with frequency translation inside the delta sigma loop. The input IF signal is down converted to baseband after amplification by a low Q, wideband bandpass resonator. The down converted IF signal is digitized by a continuous time, second order lowpass delta sigma modulator. The output of the lowpass delta sigma modulator is upconverted and fedback in to the low Q wideband bandpass resonator. Unlike the conventional delta sigma modulators, sinusoidal pulses are used for feedback. The system level design of the frequency translating delta sigma modulator is discussed. A prototype frequency translating delta sigma modulator to digitize IF signals at 100 MHz was designed in CMOS 0.35 μm process. Transistor level simulation shows that 80 dB SNR is achievable at a power dissipation of 100 mW. The frequency translating delta sigma modulator is less sensitive to time delay jitter in the DAC feedback pulse. If we use edge triggered sinusoid pulses for feedback, the DAC jitter performance of frequency translating delta sigma modulator will be better than that of conventional bandpass delta sigma modulator.
Graduation date: 2003

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