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Journal articles on the topic 'Sigma-delta modulator'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 June 2024

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1

Ren, Ming Yuan, Tuo Li, and Chang Chun Dong. "Design of a Fourth-Order Sigma-Delta Modulator for Audio Application." Applied Mechanics and Materials 380-384 (August 2013): 3580–83. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3580.

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Based on requirements on high performance and high resolution of modulators, a fourth-order Sigma-Delta modulator for audio application is developed in this paper. The modulator is designed under the commercial 0.5μm CMOS process and the circuits are given simulations by Spectre. The sampling frequency of sigma-delta modulator is 11.264 MHz, and OSR is 256 within the 22 kHz signal bandwidth. Measure performance shows that Sigma-Delta modulator enables its maximum SNR to achieve 103.5dB, and the accuracy of Sigma-Delta modulator is up to 16 bit.

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2

NERURKAR, SHAILESH B., and KHALID H. ABED. "A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 407–29. http://dx.doi.org/10.1142/s0218126609005149.

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This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.

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3

Beigh, Nadeem Tariq, Prince Nagar, Aamir Bin Hamid, Faizan Tariq Beigh, and Faroze Ahmad. "2nd Order Sigma Delta Modulator Design using Delta Sigma Toolbox." Asian Journal of Electrical Sciences 7, no. 2 (November 5, 2018): 41–45. http://dx.doi.org/10.51983/ajes-2018.7.2.2161.

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This paper discusses the block level design of 2nd order sigma delta using the Delta Sigma Toolbox and Simulink .An optimized modulator is designed with scaled coefficients, giving a low power, low frequency and high OSR modulator. The modulator presented has an OSR of 256, bandwidth of 200Hz, SNR of 100dB, SNDR of 96 dB, ENOB of 16 bits (approx.).The designed modulator is ideal for low power and low frequency applications, as in case of conversion of brain wave signals which are in the frequency range of 10-100Hz.This work provides the baseline for the design of the same modulator using switched capacitor in CMOS technology of 0.18μm TMSC CMOS technology with VDD of 1.8V.The coefficient values a, b, g, c are the ratios of capacitors in switched capacitor level design.

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4

Mishra, Samir Kumar, Rajendra Kuamr, and Hari Om Sharan. "Advancements in VLSI Technology for Enhanced Signal Processing and Power Management in Electronic Systems." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 11, no. 1 (August 31, 2020): 1139–54. http://dx.doi.org/10.61841/turcomat.v11i1.14591.

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This research investigates the application of Delta-Sigma Modulator controlled switch-mode power supplies to address the challenges associated with conventional PWM-controlled DC-DC Buck Converters. By exploiting the noise-shaping capabilities of Delta-Sigma modulation, in-band tones in the output are mitigated. The study encompasses three phases: initial design and performance evaluation of PWM-controlled converters, transition to Delta-Sigma Modulator control, and refinement of the design to enhance efficiency and noise performance. Notable achievements include reducing inductor values and integrating on-chip capacitors, leading to a peak efficiency of 91% at a 200MHz sampling frequency. Post-layout simulations further validate the superiority of Delta-Sigma Modulator controlled switch-mode power supplies over PWM-controlled counterparts.

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5

Lee, Kye-Shin. "Macro Model for Discrete-Time Sigma‒Delta Modulators." Electronics 11, no. 23 (December 2, 2022): 3994. http://dx.doi.org/10.3390/electronics11233994.

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This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since the macro model is a true representation of the actual transistor level circuit, a moderately good accuracy can be obtained. In addition, the proposed macro model includes the major amplifier, comparator, and switch‒capacitor non-idealities of the sigma‒delta modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, and switch-on resistance. The results show the simulation time of the proposed macro model sigma‒delta modulator is only 6.43% of the transistor level circuit with comparable accuracy. As a result, the proposed macro model can facilitate the circuit design and leverage non-ideality analysis of discrete-time sigma‒delta modulators. As a practical design example, a second order discrete-time sigma‒delta modulator with a five-level quantizer is realized using the propose macro model for GSM and WCDMA applications.

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6

Ioka, Eri, Nozomi Watanabe, Ryo Makishima, and Yasuyuki Matsuya. "Noise Characteristic of the Chaotic Double Loop Delta Sigma Modulator." International Journal of Bifurcation and Chaos 26, no. 11 (October 2016): 1650178. http://dx.doi.org/10.1142/s0218127416501789.

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The chaotic delta sigma modulator is a way to suppress the limit cycle oscillation caused by the input of a null or constant signal. By changing integrator gains, the output sequence becomes chaotic and the noise characteristic of the output is changed. This noise characteristic is an important factor for evaluating the performance of delta sigma modulation. The aim of this study is to analyze the noise characteristic of chaotic double loop delta sigma modulation when the null signal is input. We use a bifurcation diagram and FFT analysis to obtain the parameter dependence of the output state and noise characteristic, respectively. The output status of the chaotic double loop delta sigma modulation can be guessed from a bifurcation diagram with the brute force method. We also investigate the noise characteristic of the output signal of the chaotic modulator with FFT analysis and classify the various noise characteristics by changing the integrator gains of the double loop delta sigma modulator. We use FFT and the bifurcation diagram to classify these noise characteristics into three categories: suppressed tone (affected by the chaos), divergence, and the appearance of the limit cycle oscillation. We also confirm the existence of an unusual noise-shaping characteristic caused by the intermittent chaos.

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7

Xu, Chi, Yu Jin, and Duli Yu. "A Novel Sigma-Delta Modulator with Fractional-Order Digital Loop Integrator." Mathematical Problems in Engineering 2017 (2017): 1–7. http://dx.doi.org/10.1155/2017/9861383.

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This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, thus extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field. The proposed fractional-order Sigma-Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; moreover the signal-to-noise ratio (SNR) is improved remarkably. In particular, a 2nd-order digital loop integrator and a digital PIλDμ controller are combined to work as the fractional-order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional-order Sigma-Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional-order Sigma-Delta modulator.

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8

LEE, HO-YIN, CHEN-MING HSU, SHENG-CHIA HUANG, YI-WEI SHIH, and CHING-HSING LUO. "DESIGNING LOW POWER OF SIGMA DELTA MODULATOR FOR BIOMEDICAL APPLICATION." Biomedical Engineering: Applications, Basis and Communications 17, no. 04 (August 25, 2005): 181–85. http://dx.doi.org/10.4015/s1016237205000287.

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This paper discusses the design of micro power Sigma-delta modulator with oversampling technology. This Sigma-delta modulator design is paid special attention to its low power application of portable electronic system in digitizing biomedical signals such as Electro-cardiogram (ECG), Electroencephalogram (EEG) etc. [1]. A high performance, low power second order Sigma-delta modulator is more useful in analog signal acquisition system. Using Sigma-delta modulator can reduce the power consumption and cost in the whole system. The original biomedical signal can be reconstructed by simply applying the digital bit stream from the modulator output through a low-pass filter. The loop filter of this modulator has been implemented by using switch capacitor (SC) integrators and using simple circuitry consists of OpAmps, Comparator and DAC. In general, the resolution of modulator is about 10 bits for biomedical application. In this two order Sigma-delta modulator simulation results of the 1.8V sigma delta modulator show a 68 dB signal-to-noise-and-distortion ratio (SNDR) in 4 kHz biomedical signal bandwidth and a sampling frequency equal to 1 MHz in the 0.18 μ m CMOS technology. The power consumption is 400 μ W. It is very suitable for low power application of biomedical instrument design.

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9

Temenos, Nikos, Anastasis Vlachos, and Paul P. Sotiriadis. "Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals." Technologies 10, no. 1 (January 20, 2022): 14. http://dx.doi.org/10.3390/technologies10010014.

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This work presents a soft-filtering digital signal processing architecture based on sigma-delta modulators and stochastic computing. A sigma-delta modulator converts the input high-resolution signal to a single-bit stream enabling filtering structures to be realized using stochastic computing’s negligible-area multipliers. Simulation in the spectral domain demonstrates the filter’s proper operation and its roll-off behavior, as well as the signal-to-noise ratio improvement using the sigma-delta modulator, compared to typical stochastic computing filter realizations. The proposed architecture’s hardware advantages are showcased with synthesis results for two FIR filters using FPGA and synopsys tools, while comparisons with standard stochastic computing-based hardware realizations, as well as with conventional binary ones, demonstrate its efficacy.

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10

Sommarek, Johan, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, and Kari Halonen. "Digital Modulator with Bandpass Delta-Sigma Modulator." Analog Integrated Circuits and Signal Processing 43, no. 1 (April 2005): 81–86. http://dx.doi.org/10.1007/s10470-005-6573-z.

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11

Diwakar, K., C. Senthilpari, Lim Way Soong, and Ajay Kumar Singh. "Delta-Sigma Modulator based multiplier." IEICE Electronics Express 6, no. 6 (2009): 322–28. http://dx.doi.org/10.1587/elex.6.322.

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12

Jaggi, M. P., and C. V. Chakravarthy. "Instantaneously adaptive delta sigma modulator." Canadian Electrical Engineering Journal 11, no. 1 (January 1986): 3–6. http://dx.doi.org/10.1109/ceej.1986.6593145.

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13

Bulzacchelli, J. F., H.-S. Lee, J. A. Misewich, and M. B. Ketchen. "Superconducting bandpass delta-sigma modulator." Superconductor Science and Technology 12, no. 11 (November 1, 1999): 695–97. http://dx.doi.org/10.1088/0953-2048/12/11/301.

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14

Lewis, C. P., and T. G. Hesketh. "A laboratory sigma-delta modulator." Transactions of the Institute of Measurement and Control 13, no. 2 (April 1991): 64–67. http://dx.doi.org/10.1177/014233129101300202.

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15

Amornwongpeeti, Sarayut, Mongkol Ekpanyapong, and Chumnarn Punyasai. "Exploring of Third-Order Cascaded Multi-bit Delta- Sigma Modulator with Interstage Feedback Paths." ECTI Transactions on Electrical Engineering, Electronics, and Communications 9, no. 1 (July 28, 2010): 92–101. http://dx.doi.org/10.37936/ecti-eec.201191.172312.

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The emergence of mixed-signal integrated circuit results in the tremendous increase in the numbers of high performance data converters with the trend toward high resolution and large bandwidth. Delta-Sigma modulator, employing oversampling technique, provides high output precision by shaping the in-band quantization noise to the out-of-band. This paper explores characteristics of Thirdorder cascaded multibit Delta-Sigma modulator with interstage feedback paths using behavioural simulation. Comparisons between mathematical models with behavioural models are demonstrated for theoretical analysis. Simulation models with various non-ideal sources of Delta-Sigma modulator are presented. A comparative analysis ofnon-ideal effects including sampling jitter noise, integrator noise, integrator nonidealities, and capacitor mismatch on a cascaded architecture with interstage feedback paths of a Thirdorder multi-bit Delta-Sigma modulator are also discussed.

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16

Mladenov, Valeri, Panagiotis Karampelas, Georgi Tsenov, and Vassiliki Vita. "Approximation Formula for Easy Calculation of Signal-to-Noise Ratio of Sigma-Delta Modulators." ISRN Signal Processing 2011 (February 14, 2011): 1–7. http://dx.doi.org/10.5402/2011/731989.

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The signal-to-noise ratio (SNR) is one of the most significant measures of performance of the sigma-delta modulators. An approximate formula for calculation of signal-to-noise ratio of an arbitrary sigma-delta modulator (SDM) has been proposed. Our approach for signal-to-noise ratio computation does not require modulator modeling and simulation. The proposed formula is compared with SNR calculations based on output bitstream obtained by simulations, and the reasons for small discrepancies are explained. The proposed approach is suitable for fast and precise signal-to-noise ratio computation. It is very useful in the modulator design stage, where multiple performance estimates are required.

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17

Sidor, Tadeusz. "METROLOGICAL PROPERTIES OF A/D CONVERTERS UTILIZING HIGHER ORDER SIGMA–DELTA MODULATORS COMPARED WITH A/D CONVERTERS WITH MODULATORS OF FIRST ORDER." Metrology and Measurement Systems 21, no. 1 (March 1, 2014): 37–46. http://dx.doi.org/10.2478/mms-2014-0004.

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Abstract Time domain analysis is used to determine whether A/D converters that employ higher order sigma-delta modulators, widely used in digital acoustic systems, have superior performance over classical synchronous A/D converters with modulators of first order when taking into account their important metrological property which is the magnitude of the quantization error. It is shown that the quantization errors of delta-sigma A/D converters with higher order modulators are exactly on the same level as for converters with a first order modulator.

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18

An, Shengbiao, Shuang Xia, Yue Ma, Arfan Ghani, Chan Hwang See, Raed A. Abd-Alhameed, Chuanfeng Niu, and Ruixia Yang. "A Low Power Sigma-Delta Modulator with Hybrid Architecture." Sensors 20, no. 18 (September 16, 2020): 5309. http://dx.doi.org/10.3390/s20185309.

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Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

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19

Tao, Hai, and J. M. Khoury. "Direct-conversion bandpass sigma-delta modulator." Electronics Letters 33, no. 15 (1997): 1282. http://dx.doi.org/10.1049/el:19970888.

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20

Majd, Nasser Erfani, Hassan Ghafoorifard, and Abbas Mohammadi. "Bandwidth enhancement in delta sigma modulator transmitter using low complexity time-interleaved parallel delta sigma modulator." AEU - International Journal of Electronics and Communications 69, no. 7 (July 2015): 1032–38. http://dx.doi.org/10.1016/j.aeue.2015.04.001.

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21

Li, Bin, Xiang Ning Fan, and Wei Wei Zhu. "A Long Sequence Length, Reduced Complexity MASH 1-1-1 DDSM for Fractional-N Frequency Synthesizer." Applied Mechanics and Materials 130-134 (October 2011): 4286–90. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.4286.

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In this paper, a long sequence length, reduced complexity MASH 1-1-1 digital delta-sigma modulator (DDSM) suitable for fractional-N frequency synthesizer applications is presented. Good shaping of quantization noise is achieved by using the state of art MASH structure for a digital third-order delta-sigma modulator, meanwhile, the hardware required for this modulator is considerably reduced by recoding all carry output signal from accumulators. The functional operation of the modulator is confirmed by simulation.

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22

Ijaz, Khalid, Muhammad Adnan, Waqas Tariq Toor, Muhammad Asim Butt, Muhammad Idrees, Usman Ali, Izaz Hassan, et al. "A New Noise Shaping Approach for Sigma-Delta Modulators Using Two-Stage Feed-Forward Delays and Hybrid MASH-EFM." Electronics 12, no. 3 (February 1, 2023): 740. http://dx.doi.org/10.3390/electronics12030740.

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Sigma-delta modulators use a noise-shaping technique to curtail the noise power in the band of interest during digital-to-analog conversion. Error feedback modulator employs an efficient noise transfer function for time varying inputs than any other sigma-delta modulators. However, the efficiency of the conventional noise transfer function degrades and the quantizer saturation issue provokes when the input signal reaches to full scale. This work proposes a new noise transfer function which is a combination of transfer functions of two-stage Feed-forward delays and a novel Hybrid multi-stage noise shaping-error feedback sigma-delta modulator. The noise transfer function of two-stage Feed-forward delays mitigates the concern of quantizer saturation. The noise transfer function offered by the Hybrid multi-stage noise shaping-error feedback architecture provides sustainable solutions to limit cycles and idle tones. The simulation concludes that the proposed noise-shaping approach obtains comparatively high signal-to-quantization noise ratio than the conventional error feedback modulators. Other performance parameters like spurious-free dynamic range, effective number of bits and signal-to-noise plus distortion ratio are also significantly improved.

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23

Haimeng, Sun, R. Kochan, O. Kochan, and Su Jun. "INTEGRAL NONLINEARITY OF SECOND-ORDER SINGLE-BIT SIGMA-DELTA MODULATOR." Tekhnichna Elektrodynamika 2016, no. 6 (September 29, 2016): 63–68. http://dx.doi.org/10.15407/techned2016.06.063.

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24

Liu, Liang, Song Chen, Chong He, Liang Yin, and Xiao Wei Liu. "Design of Third-Order Single-Loop Full Feed-Forward Sigma Delta Modulator." Key Engineering Materials 609-610 (April 2014): 1176–80. http://dx.doi.org/10.4028/www.scientific.net/kem.609-610.1176.

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Sigma Delta modulator is widely used in ADC for kinds of micro inertial sensors, Sigma Delta ADC can be easily integrated with digital circuits. It possesses some performances of good linearity and high accuracy, while it has no such strict requirements for the match of device dimensions. In this paper, the design of third-order Sigma Delta modulator with a structure of single-loop full feed-forward is accomplished, meanwhile it uses local feedback for zero optimization to improve the shaping capacity of the modulator noise within the signal bandwidth. The OSR (over-sampling rate) of the modulator is 128 and the signal bandwidth is 10 kHz. By the system model building and simulation in the Simulink of MATALAB, the SNR is 96.3 dB and the ENOB is 15.71 bits. Then the modulator is implemented into transistor-level circuits with 0.5um process, by the simulation in Spectre of Cadence, the SNR is 88.5 dB and the ENOB is 14.41 bits. 搜

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Wang, Qianqian, Fei Liu, Liyin Fu, Qianhui Li, Jing Kang, Ke Chen, and Zongliang Huo. "A 22.3-Bit Third-Order Delta-Sigma Modulator for EEG Signal Acquisition Systems." Electronics 12, no. 23 (December 2, 2023): 4866. http://dx.doi.org/10.3390/electronics12234866.

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This paper presents a high resolution delta-sigma modulator for continuous acquisition of electroencephalography (EEG) signals. The third-order single-loop architecture with a 1-bit quantizer is adopted to achieve 22.3-bit resolution. The effects of thermal noise on the performance of the delta-sigma modulator are analyzed to reasonably allocate the switched-capacitor sizes for optimal signal to noise ratio (SNR) and minimum chip area. The coefficients in feedback path and input path are optimized to avoid the signal distortion under the full-scale input voltage range with almost no increase in total capacitance sizes. Fabricated in 0.5 µm CMOS technology and powered by a 5 V voltage supply, the proposed delta-sigma modulator can achieve 136 dB peak SNR with 16 Hz input and 137 dB dynamic range in 100 Hz signal bandwidth with an oversampling ratio of 512. The modulator dissipates 700 µA. The core chip area is 1.96 mm2. The modulator occupies 1.41 mm2 and the decimator occupies 0.55 mm2.

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26

Majd, Nasser Erfani, and Amin Aeenmehr. "Efficiency Improvement of Delta Sigma Modulator-Based Transmitter Using Complex Delta Sigma Modulator and Noise Reduction Loop." Journal of Circuits, Systems and Computers 29, no. 16 (July 18, 2020): 2050267. http://dx.doi.org/10.1142/s0218126620502679.

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This paper proposes an architecture to enhance coding efficiency (CE) of the Delta Sigma Modulator (DSM) transmitters. In this architecture, a complex–low pass delta sigma modulator (LPDSM) is used instead of existing Cartesian–LPDSM and polar–low pass envelope delta sigma modulator (LPEDSM). Simulation results show that for Uplink long-term evolution (LTE) signal with 1.92[Formula: see text]MHz bandwidth and 7.8-dB peak to average power ratio (PAPR), the CE for the complex–LPDSM-based transmitter is equal to 41.7% in compare to 9.7% CE for Cartesian–LPDSM transmitter. Also, due to the resolving of noise convolution problem, the complex–LPDSM-based transmitter baseband part needs lower oversampling ratio (OSR) and clock speed than polar–LPEDSM transmitter baseband part to achieve the same signal-to-noise and distortion ratio (SNDR). In the next step, a quantization noise reduction loop is implemented in this architecture. By using this technique for an Uplink LTE signal with 1.92[Formula: see text]MHz bandwidth, with the same PAPR and OSR of 16, the CE is improved from 41.7% to 56.1% with 40[Formula: see text]dB SNDR.

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Pandey, Neeta, Rajeshwari Pandey, Aseem Sayal, and Manan Tripathi. "Realization of DVCCTA Based Versatile Modulator." Active and Passive Electronic Components 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/342785.

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A Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) based versatile modulator is proposed which can work as an amplitude modulator, frequency modulator, delta modulator, and sigma delta modulator. The modulator operational scheme uses pulse generator as a core and its output is used as carrier signal. A DVCCTA based pulse generator is proposed first and subsequently configured as different modulators. Compact realization is the key feature of the proposed circuit as it uses two DVCCTA; a grounded resistor and a grounded capacitor hence are appropriate for IC realization. The functionality of the proposed circuit is verified through SPICE simulations using TSMC 0.25 μm CMOS process model parameters. The performance parameters such as power dissipation and noise for various modulator schemes are also obtained.

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28

Fakhoury, Hussein, Chadi Jabbour, and Van-Tam Nguyen. "A 40 MHz 11-Bit ENOB Delta Sigma ADC for Communication and Acquisition Systems." Sensors 23, no. 1 (December 20, 2022): 36. http://dx.doi.org/10.3390/s23010036.

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This paper describes a Delta Sigma ADC IC that embeds a 5th-order Continuous-Time Delta Sigma modulator with 40 MHz signal bandwidth, a low ripple 20 to 80 MS/s variable-rate digital decimation filter, a bandgap voltage reference, and high-speed CML buffers on a single die. The ADC also integrates on-chip calibrations for RC time-constant variation and quantizer offset. The chip was fabricated in a 1P7M 65 nm CMOS process. Clocked at 640 MHz, the Continuous-Time Delta Sigma modulator achieves 11-bit ENOB and 76.5 dBc THD up to 40 MHz of signal bandwidth while consuming 82.3 mW.

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29

Guo, Min, Hong Hui Deng, Bo Wen Ding, and Yong Sheng Yin. "Design of a Second-Order Sigma-Delta Modulator." Applied Mechanics and Materials 644-650 (September 2014): 3797–801. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3797.

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A second-order single bit Sigma - Delta modulator which can be applied to pressure sensor is designed in this paper.The modulator uses switched-capacitor circuit,and the operational amplifier adopts a differential folded-cascode structure with PMOS tube as input. Optimizes the coefficients at the system level design using Simulink tool. The schematic simulation and analysis is by the tools of Spectre and MATLAB with Global Foundry 0.35um CMOS technology. The modulator with oversampling rate of 256 is designed at the 3.3V power supply. Finally, this paper shows the circuit simulation results of the sigma-delta modulator whose signal-noise rate is 103.9dB and resolution is 16.97bits.

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30

Zorn, C., T. Brückner, M. Ortmanns, and W. Mathis. "State scaling of continuous-time sigma-delta modulators." Advances in Radio Science 11 (July 4, 2013): 119–23. http://dx.doi.org/10.5194/ars-11-119-2013.

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Abstract. In this paper, the common method of scaling the feedback coefficients of continuous time sigma delta modulators in order to stabilize the system is enhanced. The presented approach scales the different states of the system instead of the coefficients. The new corresponding coefficients are then calculated from the solution of the state space description. Therewith, it is possible to tune the maximum out-of-band gain directly in continuous time. In addition, the input amplitude distribution between each quantization level of multi bit sigma-delta modulator can be adapted.

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Qian, Ying Qi, Chang Chun Zhang, Zhong Chao Liu, Lei Lei Liu, Yu Rong Luan, Yu Ming Fang, and Yu Feng Guo. "A High-Performance Sigma-Delta Modulator in 0.18μm CMOS Technology." Applied Mechanics and Materials 519-520 (February 2014): 1085–88. http://dx.doi.org/10.4028/www.scientific.net/amm.519-520.1085.

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Sigma-Delta (∑∆) modulators are commonly used in high-resolution analog-to-digital converters (ADCs). In this paper, a high-performance modulator targeted for ultra-high-frequency (UHF) radio-frequency identification (RFID) zero-intermediate frequency (ZIF) receivers is designed in standard 0.18μm CMOS technology. The modulator has been designed with switched-capacitor (SC) integrators employing gain-boosted operational amplifiers, voltage comparators and nonoverlapping clock generators to satisfy such requirements as high gain, low voltage and wide bandwidth. The behavioral-level modeling and circuit-level design are carried out with MATLAB/Simulink and Cadence/SpectreRF, respectively. Ultimately, the high-speed and low-power realization of a second-order single-bit modulator with an oversampling ratio (OSR) of 32 is presented. Simulation results shown that, from a 1.8V supply, operated at a sampling frequency of 64MHz, a dynamic range of 53.4dB over a signal bandwidth of 1MHz is achieved.

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32

Liu, Xiao Wei, Qiang Li, Guan Nan Sun, and Wen Yan Liu. "A Fourth-Order MASH Sigma-Delta Modulator in Inertial Sensors." Key Engineering Materials 562-565 (July 2013): 311–16. http://dx.doi.org/10.4028/www.scientific.net/kem.562-565.311.

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The theory of a Sigma-Delta modulator is introduced in this paper. Based on this theory, a feedback 2-1-1 multi-stage-noise-shaping (MASH) sigma-delta modulator is designed, and the coefficients of the modulator are calculated. The system-level simulation results show that the effective number of bits (ENOB) is 24 bits when the signal bandwidth is 1 kHz and the over-sampling (OSR) rate is 128. Then the circuits of modulator are designed, including integrator, comparator, multi-phase clock and the noise cancelling logic. The whole modulator is simulated in Cadence, the signal to noise ratio (SNR) of the modulator is 125.4dB, and the ENOB is 21.1bits, which meet the technical requirements of the sensor.

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33

Lee, Kye-Shin. "Mixed CT/DT Cascaded Sigma-Delta Modulator." JSTS:Journal of Semiconductor Technology and Science 9, no. 4 (December 30, 2009): 233–39. http://dx.doi.org/10.5573/jsts.2009.9.4.233.

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Sonika, Ms, D. D. Neema, and R. N. Patel. "Designs of multi-bit sigma delta modulator." Radioelectronics and Communications Systems 59, no. 6 (June 2016): 237–43. http://dx.doi.org/10.3103/s0735272716060017.

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Colodro, F., A. Torralba, and J. L. Mora. "Robust dual-quantisation multibit Sigma-Delta modulator." Electronics Letters 39, no. 9 (2003): 702. http://dx.doi.org/10.1049/el:20030470.

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Vinoth Kumar, V., E. Balasubramanian, and S. Mano. "Stabilization of UAV using delta sigma modulator." International Journal of Engineering & Technology 7, no. 2.33 (May 31, 2018): 461. http://dx.doi.org/10.14419/ijet.v7i2.32.14810.

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The design development and control of Unmanned Aerial Vehicles (UAV’s) have stimulated great significance in the automatic control research for the past 2 decade. In specific, Quad rotor systems are promising platform in the area of UAV research, due to its simple in construction, maintenance, ability to hover, and their vertical takeoff and landing (VTOL) capability. The dynamics and control of quad rotor are highly non-linear and under actuated so it is consider as a test-rig to verify any new proposed nonlinear control algorithm. Different control algorithms were proposed and implemented to stabilize the UAV attitude, and altitude. Adaptive control and navigation algorithms also implemented in UAV platform to ensure the maneuvering against the internal and external disturbances. The proposed research paper explains the implementation of developed digital control algorithm Delta-sigma modulator (DSM) based controller for UAV to enhance the robustness.

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37

Oliaei, O. "Sigma-delta modulator with spectrally shaped feedback." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 50, no. 9 (September 2003): 518–30. http://dx.doi.org/10.1109/tcsii.2003.815023.

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Chen, Wei, and C. Papavassiliou. "Asynchronous sigma–delta modulator with noise shaping." Electronics Letters 49, no. 24 (November 2013): 1520–22. http://dx.doi.org/10.1049/el.2013.3407.

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Rezapour, Ali, and Hossein Shamsi. "Digital Noise Coupled MASH Delta-Sigma Modulator." IEEE Transactions on Circuits and Systems II: Express Briefs 66, no. 1 (January 2019): 41–45. http://dx.doi.org/10.1109/tcsii.2018.2837123.

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Jantzi, S. A., W. M. Snelgrove, and P. F. Ferguson. "A fourth-order bandpass sigma-delta modulator." IEEE Journal of Solid-State Circuits 28, no. 3 (March 1993): 282–91. http://dx.doi.org/10.1109/4.209995.

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Tafazoli, M., N. Davoudzadeh, and M. R. Sayeh. "All optical asynchronous binary delta–sigma modulator." Optics Communications 291 (March 2013): 228–31. http://dx.doi.org/10.1016/j.optcom.2012.11.022.

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Ye, Zhipeng, and Michael Peter Kennedy. "Reduced Complexity MASH Delta–Sigma Modulator." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 8 (August 2007): 725–29. http://dx.doi.org/10.1109/tcsii.2007.896940.

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Rui Yu and Yong-Ping Xu. "Electromechanical-Filter-Based Bandpass Sigma–Delta Modulator." IEEE Transactions on Circuits and Systems II: Express Briefs 56, no. 7 (July 2009): 550–54. http://dx.doi.org/10.1109/tcsii.2009.2022211.

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Wang, Q. Q., B. J. Ge, X. X. Feng, and X. A. Wang. "Digital noise shaping multibit delta-sigma modulator." Electronics Letters 46, no. 16 (2010): 1110. http://dx.doi.org/10.1049/el.2010.1598.

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Binjie, Ge, Wang Xin'an, Zhang Xing, Feng Xiaoxing, and Wang Qingqin. "Sigma–delta modulator modeling analysis and design." Journal of Semiconductors 31, no. 9 (September 2010): 095003. http://dx.doi.org/10.1088/1674-4926/31/9/095003.

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Lima, Evelyn Cristina de Oliveira, Antonio Wallace Antunes Soares, and Diomadson Rodrigues Belfort. "4th Order LC-Based Sigma Delta Modulators." Sensors 22, no. 22 (November 18, 2022): 8915. http://dx.doi.org/10.3390/s22228915.

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Due to the characteristic of narrow band conversion around a central radio frequency, the Sigma Delta Modulator (ΣΔM) based on LC resonators is a suitable option for use in Software-Defined Radio (SDR). However, some aspects of the topologies described in the state-of-the-art, such as noise and nonlinear sources, affect the performance of ΣΔM. This paper presents the design methodology of three high-order LC-Based single-block Sigma Delta Modulators. The method is based on the equivalence between continuous time and discrete time loop gain using a Finite Impulse Response Digital-to-Analog Converter (FIRDAC) through a numerical approach to defining the coefficients. The continuous bandpass LC ΣΔM simulations are performed at a center frequency of 432 MHz and a sampling frequency of 1.72 GHz. To the proposed modulators a maximum Signal-to-Noise Ratio (SNR) of 51.39 dB, 48.48 dB, and 46.50 dB in a 4 MHz bandwidth was achieved to respectively 4th Order Gm-LC ΣΔM, 4th Order Magnetically Coupled ΣΔM and 4th Order Capacitively Coupled ΣΔM.

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Ocampo-Hidalgo, Juan J., Javier Alducin-Castillo, Alberto Garcia-Ortiz, Jesus Ezequiel Molinar-Solis, Armando Gomez-Vieyra, and Ivan Vazquez-Alvarez. "A Low-Complexity Delta-Sigma Modulator ( $\Delta \Sigma $ ) for Low-Voltage, Low-Power Operation." Canadian Journal of Electrical and Computer Engineering 39, no. 2 (2016): 190–99. http://dx.doi.org/10.1109/cjece.2016.2542072.

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Joseph, Dileepan, Lionel Tarassenko, and Steve Collins. "Analysis and simulation of a cascaded delta delta–sigma modulator." Computer Standards & Interfaces 23, no. 2 (May 2001): 103–10. http://dx.doi.org/10.1016/s0920-5489(01)00063-0.

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Fan, Wen Jie, Qiu Ye Lv, Chong He, Liang Yin, and Xiao Wei Liu. "Architectural Design and Simulation of a Fourth-Order Sigma-Delta Modulator." Key Engineering Materials 609-610 (April 2014): 723–27. http://dx.doi.org/10.4028/www.scientific.net/kem.609-610.723.

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Sigma-delta ADC outperforms the Nyquist ADC in precision and robustness by using oversampling and noise shaping. A fourth-order sigma-delta modulator of input feedforward architecture is designed and simulated in system-level. Input feedforward architecture has advantages of low output swing of integrators and simple structure. Proper circuit parameters are also presented in this paper. The simulation revealed that the modulator achieves 109 dB dynamic range in a signal bandwidth of 1 KHz with a sampling frequency of 250 KHz.

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Fu, Qiang, Wei Ping Chen, Ying Kai Zhao, Liang Yin, and Xiao Wei Liu. "A 16 Bits Sigma-Delta Modulator Applied in Gyroscope." Key Engineering Materials 609-610 (April 2014): 1077–81. http://dx.doi.org/10.4028/www.scientific.net/kem.609-610.1077.

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In this paper, a 4th-order sigma-delta modulator applied in gyroscope is presented. This modulator adopts the 2-1-1 Multi stage noise shaping structure. The bandwidth of signal is 100 KHz, the over sample rate is 64, and sample frequency is 12.8MHz. By the MATLAB Simulink modeling and simulation, when the input signal is 100 KHz, the SNDR of the MASH ADC is 121.8dB, and the effective number of bit is 19.93 in ideal situation. After considering non-ideal factors, the SNDR is 111.6dB, the effective number of bit of ADC is 18.28. Compared with the ideal situation, the noise floor of PSD has increased 40dB. It explains that non-ideal factors have a significant effect on the performance of the sigma-delta ADC. The 4th-order MASH sigma-delta modulator has been implemented under 0.5 um CMOS process and simulated under Cadence. The final simulation results show that SNDR is 112.4 dB and effective number of bits (ENOB) is 18.6.

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