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Relevant bibliographies by topics / Signal processing use of VLSI

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Academic literature on the topic 'Signal processing use of VLSI'

Author: Grafiati

Published: 4 June 2021

Last updated: 7 February 2022

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Journal articles on the topic "Signal processing use of VLSI"

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Elias, John G. "Artificial Dendritic Trees." Neural Computation 5, no. 4 (1993): 648–64. http://dx.doi.org/10.1162/neco.1993.5.4.648.

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The electronic architecture and dynamic signal processing capabilities of an artificial dendritic tree that can be used to process and classify dynamic signals is described. The electrical circuit architecture is modeled after neurons that have spatially extensive dendritic trees. The artificial dendritic tree is a hybrid VLSI circuit and is sensitive to both temporal and spatial signal characteristics. It does not use the conventional neural network concept of weights, and as such it does not use multipliers, adders, look-up-tables, microprocessors, or other complex computational units to process signals. The weights of conventional neural networks, which take the form of numerical, resistive, voltage, or current values, but do not have any spatial or temporal content, are replaced with connections whose spatial location have both a temporal and scaling significance.

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Korneev, V. V., and I. E. Tarasov. "VLSI Architecture with a Configurable Pipeline." Programmnaya Ingeneria 11, no. 5 (2020): 270–76. http://dx.doi.org/10.17587/prin.11.270-276.

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The analysis carried out in the article shows the possibility of creating a problem-oriented VLSI, fabricated according to the technological standards of 28 nm or less, for at least one family of digital signal processing problems using similar computing nodes in structure. The use of distributed arithmetic allows one to apply a technique based on performing only those multiplication steps for which non-zero digits are set in the corresponding positions of the filter coefficients. Therefore, the performance of 200 nodes executing 2 steps at 1 GHz is equivalent to approximately 80 GMAC/s/mm2 for 16-bit coefficients. The VLSI architecture view opens up the possibility to study the effectiveness of implementing other families of tasks and refine the architectural parameters for their implementation. The proposed functionality of VLSI computing nodes allows them to be used in various fields of technology, which potentially increases the need for the release of such VLSI.

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Suresh, N., K. Subba Rao, and R. Vassoudevan. "Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques." Journal of Computational and Theoretical Nanoscience 17, no. 4 (2020): 1595–99. http://dx.doi.org/10.1166/jctn.2020.8407.

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Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

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Chiper, Doru Florin, and Laura-Teodora Cotorobai. "A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique." Electronics 10, no. 14 (2021): 1656. http://dx.doi.org/10.3390/electronics10141656.

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This paper aims at solving one challenging problem in designing VLSI chips, namely, the security of the hardware, by presenting a new design approach that incorporates the obfuscation technique in the VLSI implementation of some important DSP algorithms. The proposed method introduces a new approach in obtaining a unified VLSI architecture for computing type IV discrete cosine transform (DCT-IV) and type IV discrete sine transform (DST-IV), with an efficient integration of the obfuscation technique, while maintaining low overheads. The algorithms for these two transforms were restructured in such a way that their structures are fairly similar, and thus they can be implemented on the same VLSI chip and on the same hardware with very few modifications, with the latter being attributed to the pre-processing and post-processing stages. The design proposed uses the regular and modular structures, which are named quasi-correlation, and the architecture is inspired by the paradigm of the systolic array architecture. Thus, the introduced design benefits the security, for the hardware, and also the advantages introduced by the use of the regular and modular structures. A very efficient, unified VLSI architecture for type IV DCT/DST can be obtained, which allows the computation of the two algorithms on the same hardware, allowing an efficient incorporation of the obfuscation technique with very low overheads, and it can be very efficiently implemented, offering high-speed performances and low hardware complexity, with the latter being attributed to the efficient use of the hardware resources for the computation of these two algorithms.

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Venkatesh, G. K., S. Bhargavi, Basavaraj V. Hiremath, and C. Anil Kumar. "Design and Performance Analysis of Low Power and High Throughput of Analog Data Compression and Decompression using ANN in 32nm FinFET Technology." International Journal of Circuits, Systems and Signal Processing 15 (July 28, 2021): 730–44. http://dx.doi.org/10.46300/9106.2021.15.81.

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The development and fabrication of integrated circuits for the applicational areas of VLSI such as processing of the signal, medicine tomography, telecommunication turn out to be a novel technology for the upcoming innovations. The fabrication of IC’s is attributable to the methodology in the technology of VLSI and when compared to artificial Neural Network, the genetic performance of these productions is approximately the same and are typically employed for diagnosing the syndrome, compression as well as the decompression of signal used in the medical domain. Techniques such as HMM, DCT, as well as PCA are employed for compression and decompression of signals but these approaches still possess some disadvantages. Therefore, to overcome these issues, a chip-level design for Artificial Neural Network is proposed that makes use of FinFET 32 nm technology and includes sigmoid activation function (SAF), Gilbert cell number, as well as bias circuits to prolong the compressed magnitude relation and accuracy. As a result, with the help of the Cadence Virtuoso analog tool, the Artificial Neural Network has been designed using FinFET 32nm technology along with all the details of sub-units such as Layout vs Schematic (LVS), Design rule check (DRC), RC extraction as well as chip level (GDS-II). Feed Forward Artificial Neural Network (FWANN) is considered as one of the most basic types of ANN and it is implemented using the concept of Back Propagation (BP). The simulation results of the suggested 16-bit 6TRAM cell were found to have 8%, 21%, and 0.9% improvement in consuming power, delay, and compressed data losses respectively.

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Islam, Md Shabiul, M. S. Bhuyan, M. Salim Beg, and Masuri Othman. "DESIGN AND IMPLEMENTATION OF A VHDL PROCESSOR FOR DCT BASED IMAGE COMPRESSION." ASEAN Journal on Science and Technology for Development 24, no. 4 (2017): 393–406. http://dx.doi.org/10.29037/ajstd.211.

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This paper describes the design and implementation of a VHDL processor meant for performing 2D-Discrete Cosine Transform (DCT) to use in image compression applications. The design flow starts from the system specification to implementation on silicon and the entire process is carried out using an advanced workstation based design environment for digital signal processing. The software allows the bit-true analysis to ensure that the designed VLSI processor satisfies the required specifications. The bit-true analysis is performed on all levels of abstraction (behavior, VHDL etc.). The motivation behind the work is smaller size chip area, faster processing, reducing the cost of the chip

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Rajendran, Selvakumar, Arvind Chakrapani, Srihari Kannan, and Abdul Quaiyum Ansari. "A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 14, no. 4 (2021): 377–97. http://dx.doi.org/10.2174/2352096514666210127140831.

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Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in μm and nm technology. The current mirror (CM) is a basic building block used to enhance performance characteristics by constructing complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technologybased current mirror (CM) circuits are discussed with their advantages and disadvantages accompanied by the performance analysis of different parameters. It also briefs various techniques which are employed for improvising the current mirror performance like gain boosting and bandwidth extension. Besides, this paper lists the CMs that use different types of MOS devices like Floating Gate MOS, Bulk-driven MOS, and Quasi-Floating Gate MOS. As a result, the paper performs a detailed review of CMOS Current mirrors and their techniques. Results: Basic CM circuits that can act as building blocks in the VLSI circuits are simulated using 0.25 μm, BSIM and Level 1 technology. In addition, various devices based CMs are investigated and compared. Conclusion: The comprehensive discussion shows that the current mirror plays a significant role in analog/mixed-signal circuits design to realize complex systems for low-power biomedical and wireless applications.

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Kameyama, Michitaka. "Special Issue on Computer Architecture for Robotics." Journal of Robotics and Mechatronics 2, no. 6 (1990): 417. http://dx.doi.org/10.20965/jrm.1990.p0417.

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In the realization of intelligent robots, highly intelligent manipulation and movement techniques are required such as intelligent man-machine interfaces, intelligent information processing for path planning and problem solutions, practical robot vision, and high-speed sensor signal processing. Thus, very high-speed processing to cope with vast amounts of data as well as the development of various algorithms has become important subjects. To fulfill such requirements, the development of high-performance computer architecture using advanced microelectronics technology is required. For these purposes, the development of implementing computer systems’ for robots will be classified as follows: (a) Use of general-purpose computers As the performance of workstations and personal computers is increased year by year, software development is the major task without requiring hardware development except the interfaces with peripheral equipment. Since current high-level languages and software can be applied, the approach is excellent in case of system development, but the processing performance is limited. (b) Use of commercially available (V) LSI chips This is an approach to design a computer system by the combination of commercially available LSIs. Since the development of both hardware and software is involved in this system development, the development period tends to be longer than in (a). These chips include general-purpose microprocessors, memory chips, digital signal processors (DSPs) and multiply-adder LSIs. Though the kinds of available chips are limited to some degree, the approach can cope with a considerably high-performance specifications because a number of chips can be flexibly used. (c) Design, development and system configuration of VLSI chips This is an approach to develop new special-purpose VLSI chips using ASIC (Application Specific Integrated Circuit) technology, that is, semicustom or full-custom technology. If these attain practical use and are marketed, they will be widely used as high-performance VLSI chips of the level (b). Since a very high-performance specification must be satisfied, the study of very high performance VLSI computer architecture becomes very important. But this approach involving chip development requires a very long period in the design-development from the determination of processor specifications to the system configuration using the fabricated chips. For the above three approaches, the order from the viewpoint of ease of development will be (a), (b) and (c), while that from the viewpoint of performance will be (c), (b) and (a). Each approach is not exclusive but is complementary each other. For example, the development of new chips by (c) can also give new impact as the components of (a) and (b). Further, the common point of these approaches is that performance improvement by highly parallel architecture becomes important. This special edition introduces, from the above standpoint, the latest information on the present state and' future prospects of the computer techniques in Japan. We hope that this edition will contribute to the development of this field.

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Walid, Walid, Giorgio Armanno, Sandro Di Paola, Massimo Ruo Roch, Guido Masera, and Maurizio Martina. "VLSI Architectures of a Wiener Filter for Video Coding." Electronics 10, no. 16 (2021): 1961. http://dx.doi.org/10.3390/electronics10161961.

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In the modern age, the use of video has become fundamental in communication and this has led to its use through an increasing number of devices. The higher resolution required for images and videos leads to more memory space and more efficient data compression, obtained by improving video coding techniques. For this reason, the Alliance for Open Media (AOMedia) developed a new open-source and royalty-free codec, named AOMedia Video 1 (AV1). This work focuses on the Wiener filter, a specific loop restoration tool of the AV1 video coding format, which features a significant amount of computational complexity. A new hardware architecture implementing the separable symmetric normalized Wiener filter is presented. Furthermore, the paper details possible optimizations starting from the basic architecture. These optimizations allow the Wiener filter to achieve a 100× reduction in processing time, compared to existing works, and 5× improvement in megasamples per second.

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Kameyama, Michitaka. "Special Issue on Intelligent Integrated Systems for Human-Oriented Information Society." Journal of Robotics and Mechatronics 12, no. 5 (2000): 501. http://dx.doi.org/10.20965/jrm.2000.p0501.

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Recent advance in the information technology makes our society very convenient from the viewpoint of human-to-human information communication. However, our new living style will require not only human-tohuman communication but also autonomous intelligent applications that support human beings such as an intelligent robot system, an intelligent transportation system, and a security/safe system as shown in Figure. These applications will contribute to human-oriented information society.Intelligent vehicle Home service robot Security The use of special-purpose VLSI processors capable of processing a large amount of real-world data is essential to make such applications realistic. In recent industrial trend, the special-purpose processors are called ""System LSIs"". One of the most important environmental informations in real-world applications is a vision information. The factor common to the applications is to catch an environment information moment by moment and to respond quickly with it. Therefore, it is important to make the response time from inputs to outputs very small. In this case, sensor data transfer bottleneck is not allowed as well as memory-to-PE (Processing Element) data transfer bottleneck. An image sensor signal processing VLSI together with image sensor devices is a key issue in such applications. From the above point of views, this special issue was planned to demonstrate the recent results of this area. Finally, I would like to express my appreciation to the authors for their efforts and contributions to this special issue and also the members of the Editorial Board for their cooperation.

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Dissertations / Theses on the topic "Signal processing use of VLSI"

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Cottrell, R. A. "A nibble-serial programmable digital signal processor for VLSI implementation." Thesis, University of Manchester, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.377305.

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Farag, Emad N. "VLSI low-power digital signal processing." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/nq22199.pdf.

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Figueroa, Toro Miguel E. "Adaptive signal processing and correlational learning in mixed-signal VLSI /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6856.

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Dugger, Jeffery Don. "Adaptive Analog VLSI Signal Processing and Neural Networks." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5294.

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Research presented in this thesis provides a substantial leap from the study of interesting device physics to fully adaptive analog networks and lays a solid foundation for future development of large-scale, compact, low-power adaptive parallel analog computation systems. The investigation described here started with observation of this potential learning capability and led to the first derivation and characterization of the floating-gate pFET correlation learning rule. Starting with two synapses sharing the same error signal, we progressed from phase correlation experiments through correlation experiments involving harmonically related sinusoids, culminating in learning the Fourier series coefficients of a square wave cite{kn:Dugger2000}. Extending these earlier two-input node experiments to the general case of correlated inputs required dealing with weight decay naturally exhibited by the learning rule. We introduced a source-follower floating-gate synapse as an improvement over our earlier source-degenerated floating-gate synapse in terms of relative weight decay cite{kn:Dugger2004}. A larger network of source-follower floating-gate synapses was fabricated and an FPGA-controlled testboard was designed and built. This more sophisticated system provides an excellent framework for exploring applications to multi-input, multi-node adaptive filtering applications. Adaptive channel equalization provided a practical test-case illustrating the use of these adaptive systems in solving real-world problems. The same system could easily be applied to noise and echo cancellation in communication systems and system identification tasks in optimal control problems. We envision the commercialization of these adaptive analog VLSI systems as practical products within a couple of years.

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McGovern, Brian Patrick. "The systematic design of VLSI signal processing architectures." Thesis, Queen's University Belfast, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.333841.

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Motamed, Ali. "Low-voltage analog VLSI circuits and signal processing /." The Ohio State University, 1996. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487942182325593.

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Lei, Chi-un, and 李志遠. "VLSI macromodeling and signal integrity analysis via digital signal processing techniques." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45700588.

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Masud, Shahid. "VLSI systems for discrete wavelet transforms." Thesis, Queen's University Belfast, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.300782.

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Smith, Stewart Gresty. "Serial-data computation in VLSI." Thesis, University of Edinburgh, 1987. http://hdl.handle.net/1842/11922.

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Chen, Chiung-Hsing. "Inner-product based signal processing algorithms and VLSI implementation." Ohio : Ohio University, 1994. http://www.ohiolink.edu/etd/view.cgi?ohiou1173764627.

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Books on the topic "Signal processing use of VLSI"

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VLSI signal processing systems. Kluwer Academic Publishers, 1986.

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Bayoumi, Magdy A. VLSI Signal Processing Technology. Springer US, 1994.

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Bayoumi, Magdy A., and Earl E. Swartzlander, eds. VLSI Signal Processing Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2776-3.

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Digital signal processing in VLSI. Prentice Hall, 1990.

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Mohammed, Ismail. Analog VLSI: Signal and information processing. McGraw-Hill, 1994.

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David, Renshaw, ed. VLSI signal processing: Abit-serial approach. Addison-Wesley, 1985.

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Terri, Fiez, ed. Analog VLSI: Signal and information processing. McGraw-Hill, 1994.

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Denyer, P. B. VLSI signal processing: A bit-serial approach. Addison-Wesley, 1985.

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Meng, Teresa H. Asynchronous Circuit Design for VLSI Signal Processing. Springer US, 1994.

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Meng, Teresa H., and Sharad Malik, eds. Asynchronous Circuit Design for VLSI Signal Processing. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2794-7.

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Book chapters on the topic "Signal processing use of VLSI"

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Gowda, Shashank M., and H. N. Suresh. "A Survey on Methodologies and Database Used for Facial Emotion Recognition." In Advances in VLSI, Signal Processing, Power Electronics, IoT, Communication and Embedded Systems. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-0443-0_30.

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Bayoumi, Magdy A. "VLSI DSP Technology: Current Developments." In VLSI Signal Processing Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2776-3_1.

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Konstantinides, Konstantinos, and Vasudev Bhaskaran. "Recent Developments in the Design of Image and Video Processing ICs." In VLSI Signal Processing Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2776-3_2.

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Jullien, G. A. "High Performance Arithmetic for DSP Systems." In VLSI Signal Processing Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2776-3_3.

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Friedman, Eby G., and J. H. Mulligan. "Pipelining and Clocking of High Performance Synchronous Digital Systems." In VLSI Signal Processing Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2776-3_4.

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Chiu, C. T., and K. J. Ray Liu. "High-Speed Transform Coding Architectures for Video Communications." In VLSI Signal Processing Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2776-3_5.

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Smith, Ross, and Gerald Sobelman. "Design and Programming of Systolic Array Cells for Signal Processing." In VLSI Signal Processing Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2776-3_6.

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Soma, Mani. "Analog VLSI Signal Processors: Design and Test Methodologies." In VLSI Signal Processing Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2776-3_7.

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Horio, Yoshihiko, Hiroyuki Takase, and Shogo Nakamura. "Switched-Capacitor Parallel Distributed Processing Network for Speech Recognition." In VLSI Signal Processing Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2776-3_8.

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Messerschmitt, David G. "VLSI Implemented Signal Processing Algorithms." In The Impact of Processing Techniques on Communications. Springer Netherlands, 1985. http://dx.doi.org/10.1007/978-94-009-5113-6_7.

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Conference papers on the topic "Signal processing use of VLSI"

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Abhishek, A. B., Shivapraksah Koliwad, and C. Srikrishna Shastri. "Land Cover/Land Use Classification Based on Decision Tree Approach." In Second International Conference on Signal Processing, Image Processing and VLSI. Research Publishing Services, 2015. http://dx.doi.org/10.3850/978-981-09-6200-5_ip-43.

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M Hegde, Soumya, and K. S. Rashmi. "Mediator in Social Network for User Interest Activity in Big Data." In Second International Conference on Signal Processing, Image Processing and VLSI. Research Publishing Services, 2015. http://dx.doi.org/10.3850/978-981-09-6200-5_d-61.

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Shijian, Guo, Xu Shiyou, Li Po, and Chen Zengping. "Feasibility analysis for VLBI to use bandwidth synthesis in satellite observation." In 2010 10th International Conference on Signal Processing (ICSP 2010). IEEE, 2010. http://dx.doi.org/10.1109/icosp.2010.5656059.

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"VLSI Signal Processing, VIII." In VLSI Signal Processing, VIII. IEEE, 1995. http://dx.doi.org/10.1109/vlsisp.1995.527470.

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"VLSI Signal Processing, IX." In VLSI Signal Processing, IX. IEEE, 1996. http://dx.doi.org/10.1109/vlsisp.1996.558264.

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Wong, Teresa, and Mohammed Ismail. "Analog VLSI signal fuzzifier." In SPIE's 1995 Symposium on OE/Aerospace Sensing and Dual Use Photonics, edited by Steven K. Rogers and Dennis W. Ruck. SPIE, 1995. http://dx.doi.org/10.1117/12.205144.

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"Signal Processing, V." In Workshop on VLSI Signal Processing. IEEE, 1992. http://dx.doi.org/10.1109/vlsisp.1992.639166.

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An-Yeu Wu, K. J. Ray Liu, Zhongying Zhang, Kazuo Nakajima, Arun Raghupathy, and Shang-Chieh Liu. "Algorithm-based low-power DSP system design: methodology and verification." In VLSI Signal Processing, VIII. IEEE, 1995. http://dx.doi.org/10.1109/vlsisp.1995.527499.

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"Workshop Author Index." In VLSI Signal Processing, VIII. IEEE, 1995. http://dx.doi.org/10.1109/vlsisp.1995.527529.

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Kwentus, A., O. Lee, and A. N. Willson. "A 250 Msample/sec programmable cascaded integrator-comb decimation filter." In VLSI Signal Processing, IX. IEEE, 1996. http://dx.doi.org/10.1109/vlsisp.1996.558351.

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Reports on the topic "Signal processing use of VLSI"

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Roberts, Richard A. VLSI Implementations for Digital Signal Processing. Defense Technical Information Center, 1987. http://dx.doi.org/10.21236/ada189612.

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Willson, Jr, and Alan N. VLSI for High-Speed Digital Signal Processing. Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada277617.

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Willson, Jr, and Alan N. VLSI for High-Speed Digital Signal Processing. Defense Technical Information Center, 1994. http://dx.doi.org/10.21236/ada286483.

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Willson, Jr, and Alan N. VLSI for High-Speed Digital Signal Processing. Defense Technical Information Center, 1992. http://dx.doi.org/10.21236/ada256654.

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Willson, Jr, and Alan N. VLSI for High-Speed Digital Signal Processing. Defense Technical Information Center, 1992. http://dx.doi.org/10.21236/ada260754.

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Willson, Jr, and Alan N. VLSI for High-Speed Digital Signal Processing. Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada270406.

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Willson, Alan N., and Jr. VLSI for High-Speed Digital Signal Processing. Defense Technical Information Center, 1992. http://dx.doi.org/10.21236/ada250365.

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Willson, Jr, and Alan N. VLSI for High-Speed Digital Signal Processing. Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada267709.

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Parhi, Keshab K. Concurrent Architectures for VLSI Signal and Image Processing. Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada276124.

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Harris, J. H. Signal Processing Studies Program VLSI Designs for Unary Functions. Defense Technical Information Center, 1987. http://dx.doi.org/10.21236/ada188053.

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