Log in

Relevant bibliographies by topics / Signal VLSI / Dissertations / Theses

To see the other types of publications on this topic, follow the link: Signal VLSI.

Dissertations / Theses on the topic 'Signal VLSI'

Author: Grafiati

Published: 4 June 2021

Last updated: 17 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 dissertations / theses for your research on the topic 'Signal VLSI.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.

1

Farag, Emad N. "VLSI low-power digital signal processing." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/nq22199.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Figueroa, Toro Miguel E. "Adaptive signal processing and correlational learning in mixed-signal VLSI /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6856.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Genov, Roman. "Massively parallel mixed-signal VLSI kernel machines." Available to US Hopkins community, 2002. http://wwwlib.umi.com/dissertations/dlnow/3068153.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Lei, Chi-un, and 李志遠. "VLSI macromodeling and signal integrity analysis via digital signal processing techniques." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45700588.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Smith, Stewart Gresty. "Serial-data computation in VLSI." Thesis, University of Edinburgh, 1987. http://hdl.handle.net/1842/11922.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Masud, Shahid. "VLSI systems for discrete wavelet transforms." Thesis, Queen's University Belfast, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.300782.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Dugger, Jeffery Don. "Adaptive Analog VLSI Signal Processing and Neural Networks." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5294.

Full text

Abstract:

Research presented in this thesis provides a substantial leap from the study of interesting device physics to fully adaptive analog networks and lays a solid foundation for future development of large-scale, compact, low-power adaptive parallel analog computation systems. The investigation described here started with observation of this potential learning capability and led to the first derivation and characterization of the floating-gate pFET correlation learning rule. Starting with two synapses sharing the same error signal, we progressed from phase correlation experiments through correlation experiments involving harmonically related sinusoids, culminating in learning the Fourier series coefficients of a square wave cite{kn:Dugger2000}. Extending these earlier two-input node experiments to the general case of correlated inputs required dealing with weight decay naturally exhibited by the learning rule. We introduced a source-follower floating-gate synapse as an improvement over our earlier source-degenerated floating-gate synapse in terms of relative weight decay cite{kn:Dugger2004}. A larger network of source-follower floating-gate synapses was fabricated and an FPGA-controlled testboard was designed and built. This more sophisticated system provides an excellent framework for exploring applications to multi-input, multi-node adaptive filtering applications. Adaptive channel equalization provided a practical test-case illustrating the use of these adaptive systems in solving real-world problems. The same system could easily be applied to noise and echo cancellation in communication systems and system identification tasks in optimal control problems. We envision the commercialization of these adaptive analog VLSI systems as practical products within a couple of years.

APA, Harvard, Vancouver, ISO, and other styles

8

McGovern, Brian Patrick. "The systematic design of VLSI signal processing architectures." Thesis, Queen's University Belfast, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.333841.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Motamed, Ali. "Low-voltage analog VLSI circuits and signal processing /." The Ohio State University, 1996. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487942182325593.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Papathanasiou, Konstandinos. "Palmo : a novel pulsed based signal processing technique for programmable mixed-signal VLSI." Thesis, University of Edinburgh, 1998. http://hdl.handle.net/1842/12759.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Chen, Chiung-Hsing. "Inner-product based signal processing algorithms and VLSI implementation." Ohio : Ohio University, 1994. http://www.ohiolink.edu/etd/view.cgi?ohiou1173764627.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Trainor, David William. "An architectural synthesis tool for VLSI signal processing chips." Thesis, Queen's University Belfast, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295432.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Yung, H. C. "Recursive and concurrent VLSI architectures for digital signal processing." Thesis, University of Newcastle Upon Tyne, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.481423.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Woods, Roger. "High performance VLSI architectures for recursive filtering." Thesis, Queen's University Belfast, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.335619.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Lau, C. H. "Computational structures for application specific VLSI processors." Thesis, University of Edinburgh, 1989. http://hdl.handle.net/1842/12396.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Cottrell, R. A. "A nibble-serial programmable digital signal processor for VLSI implementation." Thesis, University of Manchester, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.377305.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Bartlett, Viv A. "Exploiting data dependencies in low power asynchronous VLSI signal processors." Thesis, University of Westminster, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.252037.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Haas, Alfred M. "Analog VLSI circuits for biosensors, neural signal processing and prosthetics." College Park, Md.: University of Maryland, 2009. http://hdl.handle.net/1903/9175.

Full text

Abstract:

Thesis (Ph.D.) -- University of Maryland, College Park, 2009.
Thesis research directed by: Dept. of Electrical and Computer Engineering . Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

APA, Harvard, Vancouver, ISO, and other styles

19

Wijekoon, Jayawan. "Mixed signal VLSI circuit implementation of the cortical microcircuit models." Thesis, University of Manchester, 2011. https://www.research.manchester.ac.uk/portal/en/theses/mixed-signal-vlsi-circuit-implementation-of-the-cortical-microcircuit-models(6deb2d34-5811-42ec-a4f1-e11cdb6816f1).html.

Full text

Abstract:

This thesis proposes a novel set of generic and compact biologically plausible VLSI (Very Large Scale Integration) neural circuits, suitable for implementing a parallel VLSI network that closely resembles the function of a small-scale neocortical network. The proposed circuits include a cortical neuron, two different long-term plastic synapses and four different short-term plastic synapses. These circuits operate in accelerated-time, where the time scale of neural responses is approximately three to four orders of magnitude faster than the biological-time scale of the neuronal activities, providing higher computational throughput in computing neural dynamics. Further, a novel biological-time cortical neuron circuit with similar dynamics as of the accelerated-time neuron is proposed to demonstrate the feasibility of migrating accelerated-time circuits into biological-time circuits. The fabricated accelerated-time VLSI neuron circuit is capable of replicating distinct firing patterns such as regular spiking, fast spiking, chattering and intrinsic bursting, by tuning two external voltages. It reproduces biologically plausible action potentials. This neuron circuit is compact and enables implementation of many neurons in a single silicon chip. The circuit consumes extremely low energy per spike (8pJ). Incorporating this neuron circuit in a neural network facilitates diverse non-linear neuron responses, which is an important aspect in neural processing. Two of the proposed long term plastic synapse circuits include spike-time dependent plasticity (STDP) synapse, and dopamine modulated STDP synapse. The short-term plastic synapses include excitatory depressing, inhibitory facilitating, inhibitory depressing, and excitatory facilitating synapses. Many neural parameters of short- and long- term synapses can be modified independently using externally controlled tuning voltages to obtain distinct synaptic properties. Having diverse synaptic dynamics in a network facilitates richer network behaviours such as learning, memory, stability and dynamic gain control, inherent in a biological neural network. To prove the concept in VLSI, different combinations of these accelerated-time neural circuits are fabricated in three integrated circuits (ICs) using a standard 0.35 µm CMOS technology. Using first two ICs, functions of cortical neuron and STDP synapses have been experimentally verified. The third IC, the Cortical Neural Layer (CNL) Chip is designed and fabricated to facilitate cortical network emulations. This IC implements neural circuits with a similar composition to the cortical layer of the neocortex. The CNL chip comprises 120 cortical neurons and 7 560 synapses. Many of these CNL chips can be combined together to form a six-layered VLSI neocortical network to validate the network dynamics and to perform neural processing of small-scale cortical networks. The proposed neuromorphic systems can be used as a simulation acceleration platform to explore the processing principles of biological brains and also move towards realising low power, real-time intelligent computing devices and control systems.

APA, Harvard, Vancouver, ISO, and other styles

20

Lui, Ying-chun. "Lattice algorithms for multidimensional fields suitable for VLSI implementation /." [Hong Kong : University of Hong Kong], 1989. http://sunzi.lib.hku.hk/hkuto/record.jsp?B12373515.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Benaissa, Mohammed. "VLSI algorithms, architectures and design for the Fermat Number Transform." Thesis, University of Newcastle Upon Tyne, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.254020.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Konstandinos, P. "Palmo : a new pulse based technique for programmable mixed-signal VLSI." Thesis, University of Edinburgh, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.653537.

Full text

Abstract:

In this thesis a new signal processing technique is presented. This technique exploits the use of pulses as the signalling mechanism. This Palmo signalling method applied to signal processing is novel, combining the advantages of both digital and analogue techniques. Pulsed signals are robust, inherently low-power, easily regenerated, and easily distributed across and between chips. The Palmo cells used to perform analogue operations on the pulsed signals are compact, fast, simple and programmable. To demonstrate the inherent suitability of the technique to programmable analogue implementations, two chips were fabricated and tested on boards containing a standard FPGA for doing the routing. Results from elementary filter implementations and A/D converters are presented to prove the validity of the approach. Finally a current-mode log-domain BiCMOS Palmo circuit is analysed, which enables much higher sample frequencies than the voltage domain Palmo counterparts.

APA, Harvard, Vancouver, ISO, and other styles

23

Privat, Gilles. "Architectures spécialisées de circuits VLSI pour le traitement numérique du signal." Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37600544c.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Zargaran, Yazd Arash. "Improvement of longevity and signal quality in implantable neural recording systems." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/2650.

Full text

Abstract:

Application of neural prostheses in today's medicine successfully helps patients to increase their activities of daily life and participate in social activities again. These implantable microsystems provide an interface to the nervous system, giving cellular resolution to physiological processes unattainable today with non-invasive methods. The latest developments in genetic engineering, nanotechnologies and materials science have paved the way for these complex systems to interface the human nervous system. The ideal system for neural signal recording would be a fully implantable device which is capable of amplifying the neural signals and transmitting them to the outside world while sustaining a long-term and accurate performance, therefore different sciences from neurosciences, biology, electrical engineering and computer science have to interact and discuss the synergies to develop a practical system which can be used in daily medicine practice. This work investigates the main building blocks necessary to improve the quality of acquired signal from the micro-electronics and MEMS perspectives. While all of these components will be ultimately embedded in a fully implantable recording probe, each of them addresses and deals with a specific obstacle in the neural signal recording path. Specifically we present a low-voltage low-noise low-power CMOS amplifier particularly designed for neural recording applications. This is done by surveying a number of designs and evaluating each design against the requirements for a neural recording system such as power dissipation and noise, and then choosing the most suitable topology for design and implementation of a fully implantable system. In addition a surface modification method is investigated to improve the sacrificial properties and biocompatibility of probe in order to extend the implant life and enhance the signal quality.

APA, Harvard, Vancouver, ISO, and other styles

25

AIKAT, RAJSEKHAR. "DESIGN OF AN OPTICAL INTENSITY COMPARISON PIXEL WITH PROGRAMMABLE INTENSITY OFFSET LEVELS." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1029256740.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Buchanan, Brent E. "A mixed-signal CMOS VLSI image convolution circuit using error spectrum shaping." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15420.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Elnaggar, Ayman Ibrahim. "Scalable parallel VLSI architectures and algorithms for digital signal and video processing." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0032/NQ27134.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Özkaramanli, Hüseyin Mehmet. "Distributed circuits in integrated circuits : signal integrity, crosstalk and delay in VLSI /." Thesis, Connect to Dissertations & Theses @ Tufts University, 1995.

Find full text

Abstract:

Thesis (Ph.D.)--Tufts University, 1995.
Submitted to the Dept. of Electrical Engineering. Includes bibliographical references (leaves 237-253). Access restricted to members of the Tufts University community. Also available via the World Wide Web;

APA, Harvard, Vancouver, ISO, and other styles

29

Goodby, James Laurence. "Test synthesis and self-test in high performance VLSI digital signal processing /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 1997. http://wwwlib.umi.com/cr/ucsd/fullcit?p9811793.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Zhou, Hai. "Signal integrity and low power issues in deep sub-micron VLSI design /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Veerakitti, Paesol. "High Frequency VCO and Frequency Divider in VLSI 90nm Technology." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1278426944.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Davall, Rosemarie Anne Regina. "The application of algorithm-based fault tolerance to VLSI processor arrays." Thesis, University of Newcastle Upon Tyne, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295477.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Khachab, Nabil Ibrahim. "Analog CMOS nonlinear cells and their applications in VLSI signal and information processing /." The Ohio State University, 1990. http://rave.ohiolink.edu/etdc/view?acc_num=osu148768520496624.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

雷應春 and Ying-chun Lui. "Lattice algorithms for multidimensional fields suitable for VLSI implementation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1989. http://hub.hku.hk/bib/B31208757.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Zhang, Wei Zhang. "Wireless receiver designs from information theory to VLSI implementation /." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31817.

Full text

Abstract:

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Ma, Xiaoli; Committee Member: Anderson, David; Committee Member: Barry, John; Committee Member: Chen, Xu-Yan; Committee Member: Kornegay, Kevin. Part of the SMARTech Electronic Thesis and Dissertation Collection.

APA, Harvard, Vancouver, ISO, and other styles

36

Abdelrazik, M. B. E. "Investigation into multidimensional digital signal processing and its implementation using VLSI associative string processors." Thesis, Brunel University, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383064.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Phillips, Desmond Keith. "Algorithms and architectures for the multirate additive synthesis of musical tones." Thesis, Durham University, 1996. http://etheses.dur.ac.uk/5350/.

Full text

Abstract:

In classical Additive Synthesis (AS), the output signal is the sum of a large number of independently controllable sinusoidal partials. The advantages of AS for music synthesis are well known as is the high computational cost. This thesis is concerned with the computational optimisation of AS by multirate DSP techniques. In note-based music synthesis, the expected bounds of the frequency trajectory of each partial in a finite lifecycle tone determine critical time-invariant partial-specific sample rates which are lower than the conventional rate (in excess of 40kHz) resulting in computational savings. Scheduling and interpolation (to suppress quantisation noise) for many sample rates is required, leading to the concept of Multirate Additive Synthesis (MAS) where these overheads are minimised by synthesis filterbanks which quantise the set of available sample rates. Alternative AS optimisations are also appraised. It is shown that a hierarchical interpretation of the QMF filterbank preserves AS generality and permits efficient context-specific adaptation of computation to required note dynamics. Practical QMF implementation and the modifications necessary for MAS are discussed. QMF transition widths can be logically excluded from the MAS paradigm, at a cost. Therefore a novel filterbank is evaluated where transition widths are physically excluded. Benchmarking of a hypothetical orchestral synthesis application provides a tentative quantitative analysis of the performance improvement of MAS over AS. The mapping of MAS into VLSI is opened by a review of sine computation techniques. Then the functional specification and high-level design of a conceptual MAS Coprocessor (MASC) is developed which functions with high autonomy in a loosely-coupled master- slave configuration with a Host CPU which executes filterbanks in software. Standard hardware optimisation techniques are used, such as pipelining, based upon the principle of an application-specific memory hierarchy which maximises MASC throughput.

APA, Harvard, Vancouver, ISO, and other styles

38

McAllister, Christine Joan. "Automated design of high performance digital filter chips." Thesis, Queen's University Belfast, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.318797.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Komari, Prabanjan. "A Novel Simulation Based Approach for Trace Signal Selection in Silicon Debug." University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1468512478.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Parker, Matthew. "Algorithms and architectures for the VLSI implementation of number theoretic transformations, residue and polynomial residue number systems." Thesis, University of Huddersfield, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.281799.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

El-Menhawy, A. El-H. "Computer Aided Design of VLSI algorithms for digital signal processing based on the Residue Number System." Thesis, University of Kent, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.376344.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

KANKIPATI, SUNDER RAJAN. "MACRO MODEL GENERATION FOR SYNTHESIS OF ANALOG AND MIXED SIGNAL CIRCUITS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1077297705.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Chan, Hin-Tat. "VLSI design and implementation of UHF RFID reader digital baseband with mixed-signal channel select filtering receiver /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20CHAN.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Diguet, Jean-Philippe. "Estimation de complexité et transformations d'algorithmes de traitement du signal pour la conception de circuits VLSI." Rennes 1, 1996. http://www.theses.fr/1996REN10118.

Full text

Abstract:

Le cadre de la these est celui de la synthese d'architectures, ce dernier regroupe l'ensemble des techniques mises en uvre pour concevoir de maniere automatique et optimisee des circuits realisant des applications decrites simplement de maniere comportementale. Dans ce domaine est aborde specifiquement le probleme de l'estimation a priori du cout d'une architecture, sous contrainte de temps d'iteration. Deux methodes nouvelles sont presentees, chacune repondant a un objectif different. La premiere est une estimation probabiliste et dynamique, elle fournit au concepteur des metriques lui permettant de juger de la complexite materielle et de la repartition des ressources dans le temps. Son but est de caracteriser les choix de specifications effectues, de maniere a favoriser par la suite le recours a d'eventuelles transformations de types algorithmique, fonctionnel et structurel. Il s'agit d'une etude faisant appel a une notion recente et peu etudiee, celle du guidage dans l'espace des transformations pour l'optimisation de l'adequation algorithme architecture. La seconde technique proposee est consacree a l'estimation precise des ressources materielles requises par l'algorithem traite, pour respecter la contrainte de temps. Elle s'adresse a l'utilisateur et a l'outil de cao. Son originalite provient du calcul dual des besoins en unites fonctionnelles et du pipeline associe, a travers une etude fine des causes de sous et sur-estimation. De cette estimation, ressort egalement une connaissance precise de la mobilite exacte des operations du graphe flot de donnees sans a priori sur l'ordonnancement. Les deux types d'estimations sont integrees dans l'outil de synthese d'architecture gaut

APA, Harvard, Vancouver, ISO, and other styles

45

Yu, Raofeng. "Estimation de haut niveau de placement et des interconnexions de circuits VLSI submicroniques." Rennes 1, 2002. http://www.theses.fr/2001REN10032.

Full text

Abstract:

Dans le premier chapitre nous présentons l'évolution des technologies semiconducteurs, le style et le flot de conception, les technologies submicroniques profondes et leurs conséquences ainsi que quelques solutions proposées. Dans le deuxième chapitre nous présentons la synthèse physique, la synthese d'architectures ainsi que les travaux déjà effectués sur leur integration. Dans le troisième chapitre nous proposons un flot de conception insérant une étape de RTL floorplanning et estimation entre la synthèse d'architectures et la synthèse logique. Nous établissons deux bibliothèques de fonctions de forme pour des composants de base et nous développons deux méthodes de génération de fonctions de forme pour les composants combinatoires. Nous proposons deux approches de RTL floorplanning. Nous adoptons une méthode efficace d'estimation temporelle d'interconnexion. De nombreux tests permettent de valider nos méthodes. Le quatrième chapitre conclut cette étude et présente des perspectives.

APA, Harvard, Vancouver, ISO, and other styles

46

Martinez, Garcia-Moreno Ciro-Andrés. "Conception d'une architecture de processeur de signal VLSI, programmable en langage évolué et optimale dans le traitement d'algorithmes rapides." Paris 11, 1988. http://www.theses.fr/1988PA112341.

Full text

Abstract:

Cette étude présente la conception et la validation d'une architecture de processeur de signal, rapide, et directement programmable en langage évolué, en vue d'une intégration sous la forme d'un circuit intégré à grande échelle (VLSI). Le langage évolué de programmation comprend essentiellement des primitives de traitement numérique du signal implantées en silicium (convolution, adaptation, module biquadratique, etc. . . ) familières aux utilisateurs potentiels de ce circuit. Cette approche permet une implantation facile des principaux algorithmes utilisés dans les applications et en particulier, ceux de filtrage numérique, de déconvolution discrète en temps réel, ou d'égalisation adaptative. Le processeur proposé peut être programmé soit avec des macroinstructions (primitives de traitement du signal), soit avec des microinstructions (pour faciliter la mise au point, par exemple) soit avec une combinaison des deux et ceci sans dégradation des performances. Les problèmes de passage des paramètres nécessaires à de telles macroinstructions sont résolus grâce à l'utilisation de registres internes de paramètres, qui sont configurés une fois pour toutes à la mise sous tension. Toutes les instructions du programme d'application résident en mémoire externe, ce qui rend aisée la programmation. Les instructions étant très puissantes, les cycles d'extraction sont très peu fréquents (la convolution ne demande qu'un cycle d'extraction, et la déconvolution n'en demande que quatre par période d'échantillonnage). La partie opérative est organisée en trois mémoires de données RAM et trois bus de données indépendants, configurables pour optimiser l'exécution des principales opérations de traitement numérique du signal. La structure de multiplieur accumulateur classique, utilisé comme opérateur arithmétique, a été modifiée de façon à effectuer en un seul cycle tant la "somme de sous-produits" nécessaire à la convolution, que la "somme plus sous-produit" nécessaire à l'adaptation. L'utilisation de mots 40 bits dans l'opérateur arithmétique, et de 16 bits ailleurs, nous donne une longueur utile du mot technologique toujours optimale, car le problème de la précision est résolu là où il se présente (dans l'accumulation). Nous avons développé d'une pan, un macrolangage avec des primitives de traitement du signal implantées en ROM sous forme de suites de microinstructions, et d'autre pan, un microlangage et des outils logiciels (un compilateur et un simulateur) pour la validation de l'architecture proposée et le développement des applications
This paper describes the architecture of a VLSI fast digital signal processor, designed to be programmed using a high-level language. This high-level programming language uses embedded signal processing directives (such as convolution, adaptation, order 2 IIR filter sections, etc. . . ) which are familiar to potential users of this IC. This feature makes it much easier to program the principal algorithms used in applications, and specially those used to implement digital filters, the real-time deconvolution and the adaptive equalisation. The processor can be programmed with macroinstructions (signal processing directives), with microinstructions (during program debugging, for example), or with a combination of both, without sacrificing it's performances. Problems related to parameter transmission needed by macroinstructions are solved by using internal registers which are initialized once and for all at power up. Programming is simplified by having all the application program's instructions in external memory. The number of fetch cycles are minimized by creating powerful instructions (for example, the convolution needs only one fetch cycle, and the deconvolution needs only four during each sampling period). The data path has three data RAM memories and three independent data buses, which can be set up to optimize the principal operations used in digital signal processing. The classical multiplier-accumulator structure used as the arithmetic operator has been modified in order to process the "sum of sub products" needed by the convolution, as well as the "sum plus sub-product" needed by the adaptation in a single cycle. The technological word used by the processor, 40 bits wide in the accumulator and 16 bits wide elsewhere, is always optimal because it solves the precision problem only where it's needed (in the multiplieraccumulator). We developed a macrolanguage using signal processing directives embedded in ROM in the form of microinstruction's sequences, a microlanguage, and software tools (a compilator and a simulator) used for validating the proposed architecture as well as for developing application programs

APA, Harvard, Vancouver, ISO, and other styles

47

Altmeyer, Ronald Christopher. "Design, implementation, and testing of a VLSI high performance ASIC for extracting the phase of a complex signal." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2002. http://library.nps.navy.mil/uhtbin/hyperion-image/02sep%5FAltmeyer.pdf.

Full text

Abstract:

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 2002.
Thesis advisor(s): Douglas J. Fouts, Phillip E. Pace. Includes bibliographical references (p. 107-108). Also available online.

APA, Harvard, Vancouver, ISO, and other styles

48

Pourbigharaz, Fariborz. "An investigation into efficient interfacing strategies for VLSI arithmetic processors based on residue number systems utilising diminished and augmented radix-2 moduli." Thesis, Brunel University, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.282927.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Heyne, Benjamin. "Efficient CORDIC based implementation of selected signal processing algorithms." Aachen Shaker, 2008. http://d-nb.info/991790073/04.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Martinez, Garcia-Moreno Ciro-Andrés. "Conception d'une architecture de processeur de signal VLSI, programmable en langage évolué et optimale dans le traitement d'algorithmes rapides." Grenoble 2 : ANRT, 1988. http://catalogue.bnf.fr/ark:/12148/cb37615823n.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!