Journal articles: 'Signal VLSI'

1

Terrell, Trevor. "VLSI signal processing systems." Microprocessors and Microsystems 10, no. 10 (December 1986): 565–66. http://dx.doi.org/10.1016/0141-9331(86)90082-7.

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2

Kung, S. Y., H. J. Whitehouse, and T. Kailath. "VLSI and modern signal processing." Signal Processing 9, no. 2 (September 1985): 137. http://dx.doi.org/10.1016/0165-1684(85)90048-9.

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3

Vetterli, Martin. "VLSI and modern signal processing." Signal Processing 12, no. 4 (June 1987): 411–12. http://dx.doi.org/10.1016/0165-1684(87)90144-7.

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4

Svensson, Christer. "Signal resynchronization in VLSI systems." Integration 4, no. 1 (March 1986): 75–80. http://dx.doi.org/10.1016/0167-9260(86)90039-8.

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5

Landyshev, S., and M. Klimenko. "1879VYA1YA VLSI. PSEUDO-NOISE SIGNAL PROCESSING." ELECTRONICS: Science, Technology, Business, no. 1 (2018): 102–8. http://dx.doi.org/10.22184/1992-4178.2018.172.1.102.108.

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6

Naylor, M. J. "Book Review: VLSI Signal Processing Systems." International Journal of Electrical Engineering & Education 24, no. 3 (July 1987): 280–81. http://dx.doi.org/10.1177/002072098702400317.

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7

HIGUCHI, TATSUO. "VLSI-oriented fast algorithm for signal processing." Journal of the Japan Society for Precision Engineering 52, no. 4 (1986): 631–34. http://dx.doi.org/10.2493/jjspe.52.631.

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8

Kasambe, P. V., and S. S. Rathod. "VLSI Wavelet Based Denoising of PPG Signal." Procedia Computer Science 49 (2015): 282–88. http://dx.doi.org/10.1016/j.procs.2015.04.254.

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9

Hayes, W. P., R. N. Kershaw, L. E. Bays, J. R. Boddie, E. M. Fields, R. L. Freyman, C. J. Garen, et al. "A 32-bit VLSI digital signal processor." IEEE Journal of Solid-State Circuits 20, no. 5 (October 1985): 998–1004. http://dx.doi.org/10.1109/jssc.1985.1052427.

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10

Mustafa, H. A. B., F. Xiao, and K. Alameh. "Opto-VLSI-Based Dynamic RF Signal Combiner." IEEE Microwave and Wireless Components Letters 27, no. 2 (February 2017): 189–91. http://dx.doi.org/10.1109/lmwc.2016.2647004.

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11

Lawson, S. "VLSI Signal Processing: a Bit-Serial Approach." Electronics and Power 32, no. 2 (1986): 169. http://dx.doi.org/10.1049/ep.1986.0096.

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12

Prasanna Kumar, V. K., and S. Sastry. "Efficient signal processing on a VLSI array." IEEE Transactions on Circuits and Systems 35, no. 9 (1988): 1103–13. http://dx.doi.org/10.1109/31.7570.

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13

Wellstead, Peter. "Book Review: VLSI and Modern Signal Processing." International Journal of Electrical Engineering & Education 23, no. 2 (April 1986): 185–86. http://dx.doi.org/10.1177/002072098602300225.

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14

Duluk, J. F., I. R. Linscott, A. M. Peterson, J. Burr, B. Ekroot, and J. Twicken. "VLSI processors for signal detection in SETI." Acta Astronautica 19, no. 11 (November 1989): 927–32. http://dx.doi.org/10.1016/0094-5765(89)90086-6.

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15

Harris, M. S. "Asynchronous circuit design for VLSI signal processing." Microelectronics Journal 25, no. 7 (October 1994): 604. http://dx.doi.org/10.1016/0026-2692(94)90050-7.

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16

G.W.A.D. "VLSI signal processing: A bit-serial approach." Microelectronics Reliability 26, no. 3 (January 1986): 569. http://dx.doi.org/10.1016/0026-2714(86)90506-8.

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17

Ishiguro, Masami, Hiroshi Nakayama, Yuki Shimauchi, Noriyuki Aibe, Ikuo Yoshihara, and Moritoshi Yasunaga. "Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging." Artificial Life and Robotics 15, no. 3 (September 2010): 325–29. http://dx.doi.org/10.1007/s10015-010-0819-2.

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18

Vittoz, Eric A. "Analog VLSI signal processing: Why, where, and how?" Analog Integrated Circuits and Signal Processing 6, no. 1 (July 1994): 27–44. http://dx.doi.org/10.1007/bf01250733.

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19

Jiang, J. F., Q. Y. Cai, H. M. Jiang, Y. S. Tang, and Z. L. Zhong. "Superconducting FET circuits for analogue VLSI signal processing." Superconductor Science and Technology 9, no. 4A (April 1, 1996): A71—A75. http://dx.doi.org/10.1088/0953-2048/9/4a/019.

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20

Jouppi, N. "Derivation of Signal Flow Direction in MOS VLSI." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 3 (May 1987): 480–90. http://dx.doi.org/10.1109/tcad.1987.1270295.

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21

Huang, Ching-Chao, and Leon L. Wu. "Signal degradation through module pins in VLSI packaging." IBM Journal of Research and Development 31, no. 4 (July 1987): 489–98. http://dx.doi.org/10.1147/rd.314.0489.

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22

Hu, Y. H. "CORDIC-based VLSI architectures for digital signal processing." IEEE Signal Processing Magazine 9, no. 3 (July 1992): 16–35. http://dx.doi.org/10.1109/79.143467.

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23

Barazesh, B., J. C. Michalina, and A. Picco. "A VLSI signal processor with complex arithmetic capability." IEEE Transactions on Circuits and Systems 35, no. 5 (May 1988): 495–505. http://dx.doi.org/10.1109/31.1776.

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24

Brauch, J., S. M. Tam, M. A. Holler, and A. L. Shmurun. "Analog VLSI neural networks for impact signal processing." IEEE Micro 12, no. 6 (December 1992): 34–45. http://dx.doi.org/10.1109/40.180245.

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25

Lee, J. C., B. J. Sheu, J. Choi, and R. Chellappa. "A mixed-signal VLSI neuroprocessor for image restoration." IEEE Transactions on Circuits and Systems for Video Technology 2, no. 3 (1992): 319–24. http://dx.doi.org/10.1109/76.157164.

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26

Vittoz, Eric A. "Analog VLSI signal processing: Why, where, and how?" Journal of VLSI signal processing systems for signal, image and video technology 8, no. 1 (February 1994): 27–44. http://dx.doi.org/10.1007/bf02407108.

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27

Casagrande, Giulio, Armando Chiari, Carla Golla, and Salvatore Miceli. "Vlsi programmable digital filter for video signal processing." Journal of VLSI signal processing systems for signal, image and video technology 6, no. 3 (December 1993): 219–31. http://dx.doi.org/10.1007/bf01608535.

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28

Irwin, Mary Jane, and Robert Michael Owens. "A case for digit serial VLSI signal processors." Journal of VLSI signal processing systems for signal, image and video technology 1, no. 4 (April 1990): 321–34. http://dx.doi.org/10.1007/bf00929925.

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29

Varman, P. J., I. V. Ramakrishnan, and D. S. Fussell. "Fault-tolerant VLSI sorters." Circuits, Systems, and Signal Processing 6, no. 2 (June 1987): 153–74. http://dx.doi.org/10.1007/bf01598957.

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30

MOES, E. A. J., R. NOUTA, and G. J. HEKSTRA. "DIVIDER ARCHITECTURES FOR VLSI IMPLEMENTATION." International Journal of High Speed Electronics and Systems 04, no. 01 (March 1993): 1–33. http://dx.doi.org/10.1142/s0129156493000029.

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For the mapping on VLSI of digital signal processing algorithms, fast implementations of the basic arithmetical operations are of great importance. Fast parallel addition and multiplication has received much attention. In this contribution we propose new parallel binary divider structures with favorable properties, such as efficient pipelining, compared with the classical parallel divider architectures.

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31

MOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (September 1, 2021): 505–11. http://dx.doi.org/10.6036/10214.

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Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;

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32

Sellami, Louiza, Kuan Wong, and Robert W. Newcomb. "Semi-State Models for VLSI Hair-Cell Circuits." Journal of Circuits, Systems and Computers 07, no. 05 (October 1997): 505–16. http://dx.doi.org/10.1142/s0218126697000383.

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Cochlea hair-cells act as neural interfaces of sound signals and, therefore, circuit representations are important to signal processing systems based upon characteristics of the ear. Here nonlinear semi-state equations for a bidirectional circuit representing a generic cochlea hair-cell are presented. The circuit can be specialized to inner or outer hair-cells depending upon the choice of circuit parameter values. Also developed are a canonical semi-state description for the hair-cell potassium and sodium channels, and circuits suitable for a transistorized hardware implementation. Circuit simulations are run with numerical data to correlate with the Howard–Hudspeth experiments.

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33

Yuminaka, Yasushi. "High-Speed Data Transmission Techniques Using Raised Cosine Signaling." Key Engineering Materials 459 (December 2010): 252–59. http://dx.doi.org/10.4028/www.scientific.net/kem.459.252.

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In this paper, we propose new pulse-shaping techniques using raised cosine signaling instead of using conventional digital signals (rectangular waves), to reduce Inter-symbol interference (ISI) and crosstalk noise. Unlike a rectangular pulse, the raised cosine pulse takes on the shape of a sinc pulse that minimizes ISI. Also, limited bandwidth of the signal can reduce crosstalk noise. We show the simulation and experimental results of the raised cosine signaling scheme to show the new signaling method plays a critical part in maintaining signal integrity in high-speed VLSI systems.

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34

Bridges, Pries, McLeod, Yunik, Gulak, and Card. "Dual Systolic Architectures for VLSI Digital Signal Processing Systems." IEEE Transactions on Computers C-35, no. 10 (October 1986): 916–23. http://dx.doi.org/10.1109/tc.1986.1676684.

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35

Papathanasiou, K., T. Brandtner, and A. Hamilton. "Palmo: pulse-based signal processing for programmable analog VLSI." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 49, no. 6 (June 2002): 379–89. http://dx.doi.org/10.1109/tcsii.2002.802341.

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36

Ishikawa, M., Y. Tanaka, and T. Kimura. "An adaptive line equalizer VLSI using digital signal processing." IEEE Journal of Solid-State Circuits 23, no. 3 (June 1988): 830–35. http://dx.doi.org/10.1109/4.326.

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37

Rabaey, J. M., W. Gass, R. Brodersen, T. Nishitani, and Tsuhan Chen. "VLSI design and implementation fuels the signal-processing revolution." IEEE Signal Processing Magazine 15, no. 1 (1998): 22–37. http://dx.doi.org/10.1109/79.647040.

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38

Shimada, Hiroki, Shohei Akita, Masami Ishiguro, Noriyuki Aibe, Ikuo Yoshihara, and Moritoshi Yasunaga. "Digital-signal-waveform improvement on VLSI packaging including inductances." Artificial Life and Robotics 16, no. 2 (September 2011): 194–97. http://dx.doi.org/10.1007/s10015-011-0915-y.

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39

Baccolini, G., L. Benetazzo, and C. Offelli. "Problems of phase measurement by VLSI signal processing systems." Measurement 4, no. 2 (April 1986): 63–67. http://dx.doi.org/10.1016/0263-2241(86)90034-5.

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40

Lee, Shin-Wen, and Wen-Shing Hsu. "VLSI systolic multiplier and adder for digital signal processing." Signal Processing 23, no. 2 (May 1991): 205–13. http://dx.doi.org/10.1016/0165-1684(91)90074-s.

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41

Jullien, G. A., N. M. Wigley, and W. C. Miller. "VLSI implementations of number theoretic techniques in signal processing." Integration 16, no. 3 (December 1993): 293–313. http://dx.doi.org/10.1016/0167-9260(93)90026-9.

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42

Armstrong, G. A., and M. L. Simpson. "Designing a custom VLSI moment invariant data signal processor." Computers & Electrical Engineering 19, no. 1 (January 1993): 25–39. http://dx.doi.org/10.1016/0045-7906(93)90030-u.

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43

Dallaire, Stéphane, Marc Tremblay, and Denis Poussart. "Mixed-signal VLSI Architecture for Real-Time Computer Vision." Real-Time Imaging 3, no. 5 (October 1997): 307–17. http://dx.doi.org/10.1006/rtim.1996.0066.

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44

Cheng, H. D., C. Tong, and Y. J. Lu. "VLSI curve detector." Pattern Recognition 23, no. 1-2 (January 1990): 35–50. http://dx.doi.org/10.1016/0031-3203(90)90047-o.

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45

Korneev, V. V., and I. E. Tarasov. "VLSI Architecture with a Configurable Pipeline." Programmnaya Ingeneria 11, no. 5 (October 22, 2020): 270–76. http://dx.doi.org/10.17587/prin.11.270-276.

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The analysis carried out in the article shows the possibility of creating a problem-oriented VLSI, fabricated according to the technological standards of 28 nm or less, for at least one family of digital signal processing problems using similar computing nodes in structure. The use of distributed arithmetic allows one to apply a technique based on performing only those multiplication steps for which non-zero digits are set in the corresponding positions of the filter coefficients. Therefore, the performance of 200 nodes executing 2 steps at 1 GHz is equivalent to approximately 80 GMAC/s/mm2 for 16-bit coefficients. The VLSI architecture view opens up the possibility to study the effectiveness of implementing other families of tasks and refine the architectural parameters for their implementation. The proposed functionality of VLSI computing nodes allows them to be used in various fields of technology, which potentially increases the need for the release of such VLSI.

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46

Vasudeva, G., and Uma B. V. "22nm FINFET Based High Gain Wide Band Differential Amplifier." International Journal of Circuits, Systems and Signal Processing 15 (February 5, 2021): 55–62. http://dx.doi.org/10.46300/9106.2021.15.7.

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Differential Amplifier is a primary building block of analog and mixed signal circuit for pre-processing and signal conditioning of analog signal. FINFET devices with high-k gate oxide at 22nm technology are predominantly used for high speed and low power complex VLSI circuits. FINFET based differential amplifiers are widely used in ADC’s and signal Processing applications due to their advantages in terms of power dissipation. Analog front end of complex VLSI circuits need to offer high gain, higher stability and low noise figure. Designing of FINFET based VLSI sub-circuits requires proper design procedure that can provide designers flexibility in controlling the circuit performances. In this paper, differential amplifier is designed using model parameters of high-k FINFET in 22nm technology. The conventional procedures for designing MOSFET based differential amplifier are modified for designing FINFET based differential amplifier. Schematic capture is carried out in Cadence environment and simulations are obtained considering 22nm FINFET PDK. The performance metrics are evaluated and optimized considering multiple iterations. The designed differential amplifier has slew rate of 6V/µSec and settling time of 0.9 µSec which is a desired metric for ADCs. Power Supply Rejection Ratio (PSRR) is 83 dB and dynamic range is 1.6754 V. Open loop DC gain of DA is achieved to be 103 dB with phase margin of 630 that demonstrates the advantages of DA designed in this work suitable for analog front end

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47

Ibarra, O., and M. Palis. "VLSI algorithms for solving recurrence equations and applications." IEEE Transactions on Acoustics, Speech, and Signal Processing 35, no. 7 (July 1987): 1046–64. http://dx.doi.org/10.1109/tassp.1987.1165233.

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48

Nash, J. Greg. "Concurrent VLSI architectures for image and signal processing: Applications in image and signal processing." IEEE Potentials 5, no. 2 (May 1986): 12–14. http://dx.doi.org/10.1109/mp.1986.6500826.

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49

Sharanabasappa, Sharanabasappa, and Pallikonda Babu. "VLSI Implementation of LFA based Median Filter with Noise Detection Architecture for EMG Denoising." International Journal of Intelligent Engineering and Systems 13, no. 6 (December 31, 2020): 156–67. http://dx.doi.org/10.22266/ijies2020.1231.14.

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Noise Reduction with less computational time and resources of the signal is a major requirement in signal processing. In the real-world scenario, Electromyography (EMG) signals often affect by various noises. The EMG signal requires noise reduction to obtain an accurate diagnosis process. In this study, Ladner-Fischer Adder (LFA) based Median Filter (MF) architecture is used to remove the noise from the EMG signal. The noise evaluation process is included in this proposed method to eliminate the flicker noise from the signal. The proposed LFA-MF method is simulated in the Cadence RTL compiler and Xilinx tool to evaluate the performance in terms of power, delay and Look Up Table (LUT). The objective of this work is to design the noise detection structure to avoid the denoising process for all the samples. This helps to reduce the hardware resources of the entire median filter architecture. The simulation result of LFA-MF architecture showed that it has lower power consumption and delay in noise reduction. The LFA-MF architecture has a power consumption of 1006548 nW in 16-bit sample width, while the existing method has 1537940 nW power consumption.

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50

Ishiguro, Tatsuo. "VLSI in picture coding." Journal of VLSI signal processing systems for signal, image and video technology 5, no. 2-3 (April 1993): 115–20. http://dx.doi.org/10.1007/bf01581288.

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Journal articles on the topic 'Signal VLSI'

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