Academic literature on the topic 'Silicon Controlled Rectifier (SCR)'
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Journal articles on the topic "Silicon Controlled Rectifier (SCR)"
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Stoliar, P., I. Akita, O. Schneegans, M. Hioki, and M. J. Rozenberg. "A spiking neuron implemented in VLSI." Journal of Physics Communications 6, no. 2 (February 1, 2022): 021001. http://dx.doi.org/10.1088/2399-6528/ac4e2a.
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Abstract A VLSI implementation of a Silicon-Controlled Rectifier (SCR)-based Neuron that has the functionality of the leaky-integrate and fire model (LIF) of spiking neurons is introduced. The silicon-controlled rectifier is not straightforward to efficiently migrate to VLSI. Therefore, we propose a MOS transistor-based circuit that provides the same functionality as the SCR. The results of this work are based on Spice simulation using open libraries and on VLSI layout and post layout simulations for a 65 nm CMOS process.
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Prasetia, Vicky, and Roy Aries Permana T. "ANALISA PENGGUNAAN SILICON CONTROLLED RECTIFIER PADA ELEKTROPLATING TEMBAGA/BAJA KARBON RENDAH." Infotekmesin 10, no. 1 (January 30, 2019): 6–11. http://dx.doi.org/10.35970/infotekmesin.v10i1.19.
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Electroplating is one of the engineering improvements in the characteristics of metal materials. Copper coating is a pre-coating before further coating for steel. The surface area of the material is in line with the strong current requirements required for the normal coating process. However, too much current flowing into the cathode results in erosion at the anode. Silicon Controlled Rectifier (SCR) is a component made of semiconductor silicon. It has a function as a controller or switch. Silicon Controlled Rectifiers can be used to reduce coating currents in copper electroplating. The setting of the coating current can be done on copper electroplating of low carbon steel cathodes with a cross-sectional area of 7500 mm2 of 4.5 A; 5 A; 6 A; 6.5 A and 6.7 A. The best copper coating results with a 10 minute coating time are shown in the current 6.5 A with a coating mass of 1.11 grams and 1.06 grams. This proves the need for a reduction in the maximum flow so that optimal coating is achieved.
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Jiang, Yibo, Hui Bi, and Hui Li. "Low trigger voltage bulk FinFET silicon controlled rectifier in nanotechnology." Modern Physics Letters B 32, no. 34n36 (December 30, 2018): 1840072. http://dx.doi.org/10.1142/s0217984918400729.
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The bulk fin field-effect transistor (FinFET) has been the primary semiconductor technology in nanotechnology. To protect low supply voltage circuits based on FinFET, trigger voltage [Formula: see text] of the silicon controlled rectifier (SCR) which acts as electrostatic discharge (ESD) protection device should be lowered further. In this paper, in order to lower the [Formula: see text] an extra implant technique is proposed to form bridging well low trigger voltage FinFET SCR (FinFET BRLVTSCR). The experiments demonstrate that the trigger voltage can be lowered effectively. Moreover, the TCAD simulations bring an in-depth physical understanding of ESD current conduction and failure mechanism during ESD protection. Finally, the turn-on characteristic demonstrates proposed novel SCRs are fast and effective under TLP and very fast TLP (VFTLP) stress.
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Hou, Du, Yang, Liu, and Liu. "Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness." Electronics 8, no. 4 (April 18, 2019): 445. http://dx.doi.org/10.3390/electronics8040445.
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The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW) is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is proposed in this paper. As verified in a 0.3-μm CMOS process, the proposed ERTSCR exhibits lower triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path. Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a larger top metal width.
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Zhu, Xinyu, Shurong Dong, Fangjun Yu, Feifan Deng, Kalya Shubhakar, Kin Leong Pey, and Jikui Luo. "Silicon-Controlled Rectifier Embedded Diode for 7 nm FinFET Process Electrostatic Discharge Protection." Nanomaterials 12, no. 10 (May 19, 2022): 1743. http://dx.doi.org/10.3390/nano12101743.
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A new silicon-controlled rectifier embedded diode (SCR-D) for 7 nm bulk FinFET process electrostatic discharge (ESD) protection applications is proposed. The transmission line pulse (TLP) results show that the proposed device has a low turn-on voltage of 1.77 V. Compared with conventional SCR and diode string, the proposed SCR-D has an additional conduction path constituting by two additional inherent diodes, which results in a 1.8-to-2.2-times current surge capability as compared with the simple diode string and conventional SCR with the same size. The results show that the proposed device meets the 7 nm FinFET process ESD design window and has already been applied in actual circuits.
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Du, Feibo, Fei Hou, Wenqiang Song, Long Chen, Yanlin Nie, Yihong Qing, Yichen Xu, Jizhi Liu, Zhiwei Liu, and Juin J. Liou. "An Improved Silicon-Controlled Rectifier (SCR) for Low-Voltage ESD Application." IEEE Transactions on Electron Devices 67, no. 2 (February 2020): 576–81. http://dx.doi.org/10.1109/ted.2019.2961124.
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Tian, Zhuo, and Bai Cheng Li. "Conduction Uniformity Improvement of ESD Protection Device in 0.35 μm Partially-Depleted SOI Salicided CMOS Technology." Applied Mechanics and Materials 687-691 (November 2014): 3251–54. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3251.
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ComparedtobulkCMOStechnology,Silicon-on-Insulator (SOI) CMOS technology has many advantages, such as low power consumption, low leakage current, low parasitic capacitance and a low soft error rate from both alpha particles and cosmic rays. However,electrostatic discharge (ESD) protection in SOI technology is still a major substantial barrier to overcome for the poor thermal conductivity of isolation oxide and the absence of vertical diode and silicon controlled rectifier (SCR).
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Liu, Zhiwei, Juin J. Liou, and Jim Vinson. "Novel Silicon-Controlled Rectifier (SCR) for High-Voltage Electrostatic Discharge (ESD) Applications." IEEE Electron Device Letters 29, no. 7 (July 2008): 753–55. http://dx.doi.org/10.1109/led.2008.923711.
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Song, Wenqiang, Feibo Du, Fei Hou, and Zhiwei Liu. "A modified low voltage triggered silicon controlled rectifier (SCR) for ESD applications." Semiconductor Science and Technology 35, no. 5 (March 31, 2020): 055015. http://dx.doi.org/10.1088/1361-6641/ab78f8.
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Chen, Ruibo, Hao Wei, Hongxia Liu, Zhiwei Liu, and Yaolin Chen. "Ultra-Low-Voltage-Triggered Silicon Controlled Rectifier ESD Protection Device for 2.5 V Nano Integrated Circuit." Nanomaterials 12, no. 23 (November 29, 2022): 4250. http://dx.doi.org/10.3390/nano12234250.
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In this paper, an improved low-voltage-triggered silicon-controlled rectifier (LVTSCR) called an ultra-low-voltage-triggered SCR (ULVTSCR) is proposed and fabricated in a 40-nm CMOS process. By adding an external NMOSs-chain triggering component to the conventional LVTSCR, the proposed ULVTSCR can realize ~2 V lower trigger voltage. Meanwhile, the trigger voltage of the ULVTSCR is adjustable with the number of its incorporated NMOS transistors. Compared with the existing Diodes-chain Triggered SCR (DTSCR) scheme, the NMOSs-chain triggered ULVTSCR possesses a 25% lowered overshoot voltage in the same area consumption, and thus it is more suitable for 2.5 V circuits ESD protections considering the CDM protection applications.
Dissertations / Theses on the topic "Silicon Controlled Rectifier (SCR)"
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Lou, Lifang. "DESIGN, CHARACTERIZATION AND COMPACT MODELING OF NOVEL SILICON CONTROLLED RECTIFIER (SCR)-BASED DEVICES FOR ELECTROSTATIC DISCHA." Doctoral diss., University of Central Florida, 2008. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2840.
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Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives.Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
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Lou, Lifang. "Design, characterization and compact modeling of novel silicon controlled rectifier (SCR)-based devices for electrostatic discharge (ESD) protection applications in integrated circuits." Orlando, Fla. : University of Central Florida, 2008. http://purl.fcla.edu/fcla/etd/CFE0002374.
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Loayza, Ramirez Jorge Miguel. "Study and characterization of electrical overstress aggressors on integrated circuits and robustness optimization of electrostatic discharge protection devices." Thesis, Lyon, 2017. http://www.theses.fr/2017LYSEI044.
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Cette thèse de doctorat s’inscrit dans la thématique de la fiabilité des circuits intégrés dans l’industrie de la microélectronique. Un circuit intégré peut être exposé à des agresseurs électriques potentiellement dangereux pendant toute sa durée de vie. Idéalement, les circuits devraient pouvoir encaisser ces excès d’énergie sans perdre leur fonctionnalité. En réalité, des défaillances peuvent être observées lors de tests de qualification ou en application finale. Il est donc dans l’intérêt des fabricants de réduire ces défaillances. Actuellement, il existe des circuits de protection sur puce conçus pour dévier l’énergie de ces agresseurs à l’écart des composants fragiles. Le terme anglophone Electrical Overstress (EOS) englobe tous les agresseurs électriques qui dépassent une limite au-delà de laquelle les composants peuvent être détruits. La définition de ce terme est traitée en détail dans la thèse. L’objectif de cette thèse est de comprendre le statut du sujet des EOS dans l’industrie. On propose ensuite une nouvelle méthodologie de caractérisation de circuits pour quantifier leur robustesse face à des formes d’onde représentatives présélectionnées. On propose également des solutions de circuits de protection sur puce que ce soit au niveau de nouveaux composants actifs ou au niveau de la conception des circuits électroniques de protection. Par exemple on propose un nouveau composant basé sur le thyristor qui a la capacité de s’éteindre même si la tension d’alimentation est présente sur l’anode. Une autre proposition est de désactiver les circuits de protection face aux décharges électrostatiques lorsque les puces sont dans un environnement où l’on est sur ou ces agresseurs ne présentent plus de danger. Finalement, des perspectives du travail de thèse sont citéesThis Ph.D. thesis concerns reliability issues in the microelectronics industry for the most advanced technology nodes. In particular, the Electrical OverStress (EOS) issue is studied. Reducing EOS failures in Integrated Circuits (ICs) is becoming more and more important. However, the EOS topic is very complex and involves many different causes, viewpoints, definitions and approaches. In this context, a complete analysis of the current status of the EOS issue is carried out. Then, the Ph.D. objectives can be defined in a clear way. In particular, robustness increase of on-chip protection structures and IC characterization against EOS-like aggressors are two of the main goals. In order to understand and quantify the behavior of ICs against these aggressors, a dedicated EOS test bench is put in place along with the definition of a characterization methodology. A full characterization and comparison is performed on two different Electro- Static Discharge (ESD) power supply clamps. After identifying the potential weaknesses of the promising Silicon-Controlled Rectifier (SCR) device, a new SCR-based device with a turn-off capability is proposed and studied thanks to 3-D Technology Computer-Aided Design (TCAD)simulation. Triggering and turn-off behaviors are studied, as well as its optimization. Finally, three different approaches are proposed for improving the robustness of the IC onchip protection circuits. They are characterized thanks to the EOS test bench which allows identifying their assets as well as their points of improvement
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Mokhtari, Hossein. "High speed silicon controlled rectifier static transfer switch." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0002/NQ41246.pdf.
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Zabihi, Sasan. "Flexible high voltage pulsed power supply for plasma applications." Thesis, Queensland University of Technology, 2011. https://eprints.qut.edu.au/48137/1/Sasan_Zabihi_Sheykhrajeh_Thesis.pdf.
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Demands for delivering high instantaneous power in a compressed form (pulse shape) have widely increased during recent decades. The flexible shapes with variable pulse specifications offered by pulsed power have made it a practical and effective supply method for an extensive range of applications. In particular, the release of basic subatomic particles (i.e. electron, proton and neutron) in an atom (ionization process) and the synthesizing of molecules to form ions or other molecules are among those reactions that necessitate large amount of instantaneous power. In addition to the decomposition process, there have recently been requests for pulsed power in other areas such as in the combination of molecules (i.e. fusion, material joining), gessoes radiations (i.e. electron beams, laser, and radar), explosions (i.e. concrete recycling), wastewater, exhausted gas, and material surface treatments. These pulses are widely employed in the silent discharge process in all types of materials (including gas, fluid and solid); in some cases, to form the plasma and consequently accelerate the associated process.
Due to this fast growing demand for pulsed power in industrial and environmental applications, the exigency of having more efficient and flexible pulse modulators is now receiving greater consideration. Sensitive applications, such as plasma fusion and laser guns also require more precisely produced repetitive pulses with a higher quality. Many research studies are being conducted in different areas that need a flexible pulse modulator to vary pulse features to investigate the influence of these variations on the application. In addition, there is the need to prevent the waste of a considerable amount of energy caused by the arc phenomena that frequently occur after the plasma process. The control over power flow during the supply process is a critical skill that enables the pulse supply to halt the supply process at any stage.
Different pulse modulators which utilise different accumulation techniques including Marx Generators (MG), Magnetic Pulse Compressors (MPC), Pulse Forming Networks (PFN) and Multistage Blumlein Lines (MBL) are currently employed to supply a wide range of applications. Gas/Magnetic switching technologies (such as spark gap and hydrogen thyratron) have conventionally been used as switching devices in pulse modulator structures because of their high voltage ratings and considerably low rising times. However, they also suffer from serious drawbacks such as, their low efficiency, reliability and repetition rate, and also their short life span. Being bulky, heavy and expensive are the other disadvantages associated with these devices. Recently developed solid-state switching technology is an appropriate substitution for these switching devices due to the benefits they bring to the pulse supplies. Besides being compact, efficient, reasonable and reliable, and having a long life span, their high frequency switching skill allows repetitive operation of pulsed power supply. The main concerns in using solid-state transistors are the voltage rating and the rising time of available switches that, in some cases, cannot satisfy the application’s requirements. However, there are several power electronics configurations and techniques that make solid-state utilisation feasible for high voltage pulse generation. Therefore, the design and development of novel methods and topologies with higher efficiency and flexibility for pulsed power generators have been considered as the main scope of this research work. This aim is pursued through several innovative proposals that can be classified under the following two principal objectives.
• To innovate and develop novel solid-state based topologies for pulsed power generation
• To improve available technologies that have the potential to accommodate solid-state technology by revising, reconfiguring and adjusting their structure and control algorithms.
The quest to distinguish novel topologies for a proper pulsed power production was begun with a deep and through review of conventional pulse generators and useful power electronics topologies. As a result of this study, it appears that efficiency and flexibility are the most significant demands of plasma applications that have not been met by state-of-the-art methods. Many solid-state based configurations were considered and simulated in order to evaluate their potential to be utilised in the pulsed power area. Parts of this literature review are documented in Chapter 1 of this thesis.
Current source topologies demonstrate valuable advantages in supplying the loads with capacitive characteristics such as plasma applications. To investigate the influence of switching transients associated with solid-state devices on rise time of pulses, simulation based studies have been undertaken. A variable current source is considered to pump different current levels to a capacitive load, and it was evident that dissimilar dv/dts are produced at the output. Thereby, transient effects on pulse rising time are denied regarding the evidence acquired from this examination. A detailed report of this study is given in Chapter 6 of this thesis.
This study inspired the design of a solid-state based topology that take advantage of both current and voltage sources. A series of switch-resistor-capacitor units at the output splits the produced voltage to lower levels, so it can be shared by the switches. A smart but complicated switching strategy is also designed to discharge the residual energy after each supply cycle. To prevent reverse power flow and to reduce the complexity of the control algorithm in this system, the resistors in common paths of units are substituted with diode rectifiers (switch-diode-capacitor). This modification not only gives the feasibility of stopping the load supply process to the supplier at any stage (and consequently saving energy), but also enables the converter to operate in a two-stroke mode with asymmetrical capacitors. The components’ determination and exchanging energy calculations are accomplished with respect to application specifications and demands. Both topologies were simply modelled and simulation studies have been carried out with the simplified models. Experimental assessments were also executed on implemented hardware and the approaches verified the initial analysis. Reports on details of both converters are thoroughly discussed in Chapters 2 and 3 of the thesis.
Conventional MGs have been recently modified to use solid-state transistors (i.e. Insulated gate bipolar transistors) instead of magnetic/gas switching devices. Resistive insulators previously used in their structures are substituted by diode rectifiers to adjust MGs for a proper voltage sharing. However, despite utilizing solid-state technology in MGs configurations, further design and control amendments can still be made to achieve an improved performance with fewer components. Considering a number of charging techniques, resonant phenomenon is adopted in a proposal to charge the capacitors. In addition to charging the capacitors at twice the input voltage, triggering switches at the moment at which the conducted current through switches is zero significantly reduces the switching losses. Another configuration is also introduced in this research for Marx topology based on commutation circuits that use a current source to charge the capacitors. According to this design, diode-capacitor units, each including two Marx stages, are connected in cascade through solid-state devices and aggregate the voltages across the capacitors to produce a high voltage pulse. The polarity of voltage across one capacitor in each unit is reversed in an intermediate mode by connecting the commutation circuit to the capacitor. The insulation of input side from load side is provided in this topology by disconnecting the load from the current source during the supply process. Furthermore, the number of required fast switching devices in both designs is reduced to half of the number used in a conventional MG; they are replaced with slower switches (such as Thyristors) that need simpler driving modules. In addition, the contributing switches in discharging paths are decreased to half; this decrease leads to a reduction in conduction losses. Associated models are simulated, and hardware tests are performed to verify the validity of proposed topologies. Chapters 4, 5 and 7 of the thesis present all relevant analysis and approaches according to these topologies.
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Liu, Wen. "Design, Characterization and Analysis of Electrostatic Discharge (ESD) Protection Solutions in Emerging and Modern Technologies." Doctoral diss., University of Central Florida, 2012. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5404.
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Electrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices' operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and current density, as well as new failure mechanisms that are not well understood. The endeavor of this research is to develop novel, effective and robust ESD protection solutions for both emerging technologies and modern complementary metal–oxide–semiconductor (CMOS) technologies. The Si nanowire field-effect transistors are projected by the International Technology Roadmap for Semiconductors as promising next-generation CMOS devices due to their superior DC and RF performances, as well as ease of fabrication in existing Silicon processing. Aiming at proposing ESD protection solutions for nanowire based circuits, the dimension parameters, fabrication process, and layout dependency of such devices under Human Body Mode (HBM) ESD stresses are studied experimentally in company with failure analysis revealing the failure mechanism induced by ESD. The findings, including design methodologies, failure mechanism, and technology comparisons should provide practical knowhow of the development of ESD protection schemes for the nanowire based integrated circuits. Organic thin-film transistors (OTFTs) are the basic elements for the emerging flexible, printable, large-area, and low-cost organic electronic circuits. Although there are plentiful studies focusing on the DC stress induced reliability degradation, the operation mechanism of OTFTs subject to ESD is not yet available in the literature and are urgently needed before the organic technology can be pushed into consumer market. In this work, the ESD operation mechanism of OTFT depending on gate biasing condition and dimension parameters are investigated by extensive characterization and thorough evaluation. The device degradation evolution and failure mechanism under ESD are also investigated by specially designed experiments. In addition to the exploration of ESD protection solutions in emerging technologies, efforts have also been placed in the design and analysis of a major ESD protection device, diode-triggered-silicon-controlled-rectifier (DTSCR), in modern CMOS technology (90nm bulk). On the one hand, a new type DTSCR having bi-directional conduction capability, optimized design window, high HBM robustness and low parasitic capacitance are developed utilizing the combination of a bi-directional silicon-controlled-rectifier and bi-directional diode strings. On the other hand, the HBM and Charged Device Mode (CDM) ESD robustness of DTSCRs using four typical layout topologies are compared and analyzed in terms of trigger voltage, holding voltage, failure current density, turn-on time, and overshoot voltage. The advantages and drawbacks of each layout are summarized and those offering the best overall performance are suggested at the end.Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
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Hsu, Wen, and 許. 文. "Power Conditioner for Silicon-Controlled Current-Source Rectifier." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/gcwd57.
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碩士國立高雄應用科技大學
電機工程系
98
Silicon-controlled current-source rectifiers have been widely applied in industries. However, they cause problems of harmonic current and voltage notch, resulting in serious degradation of power quality of the utility. In this paper, the voltage notch is discussed, and several solutions to improve power quality of the silicon-controlled current-source rectifier are analyzed. In this thesis, a hybrid solution, comprising both hybrid and passive power filters, is proposed to mitigate the problems of poor power factor, harmonic current, voltage distortion and voltage notch caused by the silicon-controlled current-source rectifier. Finally, computer simulation is carried out to evaluate the performance of these passive and hybrid solutions to improve the power quality problems caused by the silicon-controlled current-source rectifier.
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Yen, Shiang-Shiou, and 顏祥修. "Investigation of InGaZnO Thin Film Transistors and Stacked Silicon Controlled Rectifier for Liquid Crystal Display Application." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/9ucurd.
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博士國立交通大學
電子工程學系 電子研究所
104
InGaZnO thin-film transistor has attracted much attention for TFT-LCD applications because of its superior characteristics such as high transparency, good uniformity, relatively low cost, and low thermal budget compared to the -Si and poly-Si TFTs. These features is benefit to develop flexible or wearable displays. Even in amorphous phase, the device mobility is insensitive to structure disorder. Its high driving capability is more suitable to apply on OLED, AMLCD, and AMOLED products. In general, the transport properties usually have significantly depend on elements composition in compound semiconductors. The relative cation proportion of the cations directly control the back ground carrier concentration within a broad range. In previous study, we had already employed -TiOx layer capped on IGZO TFTs to improve the device electrical performance. However, the detailed mechanism of gettering effect is still unclear and it should be further investigate in other oxide TFTs. In this thesis, we demonstrate the gettering effect of oxygen-deficient TiOx in -IGZO and IZO TFTs by material analysis. After the TiOx gettering process, the oxygen vacancies in IGZO channel were successfully modified and the carrier concentration and device mobility were increased. The superior transfer characteristics such as low sub-threshold swing of 79 mV/decade, high mobility of 68 cm2/Vs, and good on/off-current ratio of 5.61×106. However, the IZO channel showed unfavorable transistor characteristics due to lack of Ga atom doping. After gettering process. IZO film exhibit a nano-crystallized grains in TEM image. The severe oxidized TiOx capping layer leads to an additional channel parasitic resistance that limits the output driving current. Therefore, we believe that the existence of Ga-O bonds among IGZO channel would be helpful to stabilize oxygen diffusion behavior and electric structure during the gettering process. Furthermore, we investigate the impact of orientated crystalline InGaZnO (IGZO) thin film transistor. To evaluate interface thermodynamic stability of temperature-sensitive IGZO film, the film-structural stabilities of high- and low-indium-content InGaZnO were studied. With increasing annealing temperature up to 700 °C, the crystallinity becomes more pronounced and device electrical characteristics are further improved. The off-state leakage is reduced and it can be attributed to the formation of c-axis-orientated crystalline located at the X-ray diffraction peak of (0 0 16). A superior performance improvements include a very low turn-on voltage close to zero voltage, a small subthreshold swing of 130 mV/dec, and a low off-state current of 2.4x10-14 A/μm at low operating voltage of 4 V. At the end of this thesis, we co-work with a LCD driver IC company to study the ESD power clamp circuit which applied on panel driver. A body-tied blocking layer is inserted into the segmented SCR structure to increase the holding voltage and no tradeoff on triggered boltage. By using resistor triggered technique, we successfully obtain a high holding voltage SCR which has Vhold of 33.4V in 0.11m 32V process. Other characteristics such as the Vt1 and It2 are 51V and 3.3A m, respectively. According to our experiment results, the integration of low-cost a-TiOx film into IGZO TFTs are suitable to develop high speed and high resolution FPDs in the future. Using a divided voltage theorem can help us to design a high latchup immunity stacked SCR device in HV ESD power clamp circuit.
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Hsu, Kuo-Chun, and 徐國鈞. "SILICON-CONTROLLED RECTIFIER WITH SUBSTRATE-TRIGGERED TECHNIQUE FOR ON-CHIP ESD PROTECTION IN CMOS INTEGRATED CIRCUITS." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/45573088056305457482.
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博士國立交通大學
電子工程系
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With the highest electrostatic discharge (ESD) robustness in the smallest layout area, the silicon-controlled rectifier (SCR) device had been used in the on-chip ESD protection circuits for a long time among various ESD protection devices (such as the diode, SCR, BJT, MOS, or field oxide device) in CMOS technologies. The turn-on mechanism of a SCR device is essentially a current triggering event. While a current is applied to the base or substrate of the SCR device, it can be quickly triggered on into its latching state through the positive-feedback regeneration mechanism without involving the original avalanche breakdown mechanism. In this thesis, the dependence of the device characteristics of SCR on the triggering current is investigated in details. Then, based on the current triggering mechanism of SCR device, the corresponding ESD detection circuits are proposed to generate the triggering currents. Finally, the on-chip ESD protection circuit with the SCR devices and current-triggering circuits are realized to protect the CMOS ICs. First, a complementary circuit style with the substrate-triggered SCR (STSCR) devices is designed to discharge both of the pad-to-VSS and pad-to-VDD ESD stresses. The novel complementary STSCR devices have the advantages of controllable switching voltage, lower holding voltage, faster turn-on speed, and fully process-compatible to general CMOS processes without extra process modification such as the silicide-blocking mask and ESD implantation. The switching voltage of the fabricated STSCR device can be reduced from ~22 to only 1.85 V, which almost equals to the holding voltage (~1.35 V) of the STSCR, when the substrate-triggered current is increased to 8 mA in a 0.25-µm fully salicided CMOS process. The turn-on time of the STSCR device can be reduced from 27.4 to 7.8 ns, while the pulse height of the triggering voltage pulse is increased from 1.5 to 4 V. The STSCR device with a small active area of only 20 µm×20 µm can be stacked in the ESD protection circuits to avoid the transient-induced latch-up issue. For the IC application with VDD of 2.5 V, the ESD protection circuit designed with two STSCR devices in stacked configuration has a clamp voltage of ~3.2 V, free from latchup issue, and the human-body-model (HBM) (machine-model (MM)) ESD level of > 8 kV (700 V) in a 0.25-µm fully salicided CMOS process. In addition, the total holding voltage of the STSCR device can be linearly increased by adding the stacked diode string. The on-chip latchup-free ESD protection circuits designed with the proposed complementary STSCR devices and two stacked diode string for the I/O pads and power pad have been successfully verified in a 0.25-µm salicided CMOS process with the HBM (MM) ESD level of ~7.25 kV (500 V) in a small layout area. Turn-on efficiency is the main concern for SCR devices used as on-chip ESD protection circuit, especially in future nanoscale CMOS processes with ultra-thinn gate oxide. The SCR device consists of a lateral NPN and a vertical PNP bipolar transistors, which is inherent in the CMOS processes. In this thesis, a novel double-triggered technique, used to synchronously trigger the NPN and PNP transistors in the SCR structure, is also proposed to further improve the turn-on speed of SCR devices for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide in nanoscale CMOS processes. From the experimental results in a 0.25-µm salicided CMOS process, the switching voltage and turn-on time of such double-triggered SCR (DTSCR) device, which is drawn as 20 µm×20 µm, has been confirmed to be reduced more efficiently by this double-triggered technique. The switching voltage of DTSCR under the N-well triggered current of -3 mA is further reduced from ~21 to ~1.5 V, when the substrate-triggered current is increased from 0 to 2 mA. Under the positive voltage pulse of 1.5 V at p-trigger node, the turn-on time of DTSCR can be reduced from 37.6 to 11.8 ns, while the absolute pulse height of negative voltage pulse applied to the n-trigger node is increased from 0 to 5 V. A novel dummy-gate-blocking SCR device with substrate-triggered technique is also proposed to improve the turn-on speed of SCR device for using in the on-chip ESD protection circuit to effectively protect the much thinner gate oxide. The fabrication of the proposed SCR device with dummy-gate structure is fully process-compatible to general CMOS process, without using extra mask layer or increasing process step. From the experimental results in a 0.25-m CMOS process with the gate-oxide thickness of ~50 Å, the switching voltage, turn-on speed, turn-on resistance, and charged-device-model (CDM) ESD levels of the SCR device with dummy-gate structure have been greatly improved, as compared to the normal SCR with shallow trench isolation (STI) structure. When the substrate-triggered current applied at the p-trigger node is increased from 0 to 6 mA, the switching voltage of STSCR with STI is reduced from ~22 to ~7 V, whereas that of STSCR with dummy-gate structure is greatly reduced from ~18 to ~3 V. In order to quickly discharge the ESD energy and to efficiently protect the ultra-thin gate oxide, a novel native-NMOS-triggered SCR (NANSCR) is proposed for on-chip ESD protection. Native NMOS is an already-on device under ESD events, so it can quickly conduct some ESD current to trigger SCR into latching state. Then, ESD current can be quickly discharged through the turned-on NANSCR device. From the experimental results in a 0.13-m CMOS process with voltage supply of 1.2 V, the switching voltage, holding voltage, turn-on resistance, turn-on speed, and CDM ESD level of NANSCR can be greatly improved to protect the ultra-thin gate oxide against ESD stresses, as compared with the traditional low-voltage triggering SCR (LVTSCR). The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger. A new whole-chip ESD protection scheme realized with the proposed NANSCR devices is also demonstrated with the consideration of pin-to-pin ESD zapping. For ultra large-scale CMOS ICs with multiple power pins, the proposed whole-chip ESD protection scheme with NANSCR and ESD path is an overall solution to quickly discharge all kinds of ESD stresses and to provide efficient protection for the internal circuits. In summary, there are totally 5 different designs on substrate-triggered SCR devices developed in this thesis. Each of the substrate-triggered SCR devices and its corresponding circuit for ESD protection have been successfully verified in the testchips and also published in the International Journals or Transactions. The developed substrate-triggered SCR devices are highly useful for on-chip ESD protection in the sub-quarter-micron CMOS integrated circuits without process modification.
Books on the topic "Silicon Controlled Rectifier (SCR)"
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McNair, Will L. SCR and new technology in electric rig drilling: A safety and efficiency handbook. Tulsa, OK: PennWell Books, 1991.
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Mokhtari, Hossein. High speed silicon controlled rectifier static transfer switch. 1999.
Find full textBook chapters on the topic "Silicon Controlled Rectifier (SCR)"
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Ge, Yaming, and Jun Li. "Design of Trigger Circuit for Series SCR 12-Pulse Phase-Controlled Rectifier." In Lecture Notes in Electrical Engineering, 1847–55. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-4981-2_202.
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Brindley, Keith. "Silicon-controlled rectifier (SCR) and family." In Newnes Electronics Engineers Pocket Book, 26–27. Elsevier, 1993. http://dx.doi.org/10.1016/b978-0-7506-0937-1.50027-6.
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"Silicon-Controlled Rectifier." In Complete Guide to Semiconductor Devices, 361–78. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2010. http://dx.doi.org/10.1002/9781118014769.ch48.
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Kumar, Vinod, Ranjan Kumar Behera, Dheeraj Joshi, and Ramesh Bansal. "Silicon-Controlled Rectifier." In Power Electronics, Drives, and Advanced Applications, 47–101. CRC Press, 2020. http://dx.doi.org/10.1201/9781315161662-4.
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"Silicon-Controlled Rectifier Power Clamps." In ESD, 489–503. Chichester, UK: John Wiley & Sons, Ltd, 2015. http://dx.doi.org/10.1002/9781118954492.ch13.
Full textConference papers on the topic "Silicon Controlled Rectifier (SCR)"
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Yusran, Andi Muhammad Aqsha Azhar Mangkona, and Debi Ahyard Rinaldi. "Power control simulation with silicon controlled rectifier (SCR)." In THE PROCEEDINGS OF THE 4TH EPI INTERNATIONAL CONFERENCE ON SCIENCE AND ENGINEERING (EICSE) 2020. AIP Publishing, 2022. http://dx.doi.org/10.1063/5.0095093.
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Song, Wenqiang, Feibo Du, Fei Hou, Jizhi Liu, Xiaozong Huang, Zhiwei Liu, and Juin J. Liou. "Design of A Novel Low Voltage Triggered Silicon Controlled Rectifier (SCR) for ESD Applications." In 2020 International EOS/ESD Symposium on Design and System (IEDS). IEEE, 2021. http://dx.doi.org/10.23919/ieds48938.2021.9468851.
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Wang, Zhixin, and Juin J. Liou. "Evaluation of geometry layout and metal pattern to optimize ESD performance of silicon controlled rectifier (SCR)." In 2014 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2014. http://dx.doi.org/10.1109/irps.2014.6861133.
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Sherwin, Peter. "A Comparison of Modern Heating Methods to Reduce a Heat Treaters CO2 Carbon Footprint." In HT2021. ASM International, 2021. http://dx.doi.org/10.31399/asm.cp.ht2021exabp0014.
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Abstract Several governments across the world have recently stepped up their action to fight climate change. Initiatives include from clean energy production to efficient buildings and reduced emissions from industry. The manufacturing industry will need to examine methods to reduce its carbon footprint, especially across energy-intensive sectors such as heat treatment. This paper explains and explores the latest developments in energy management in heat treatment with a specific focus on electrical heating and associated digital tools. In this paper, developments in IGBT (insulated-gate bipolar transistor) and SCR (silicon-controlled rectifier) technology will be compared as energy-efficient alternatives to variable reactance transformers (VRT’s) for electric vacuum furnaces.
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Elliott, S., M. LaPierre, and P. Plourde. "Novel Sample Preparation Technique for Backside Analysis of Singulated Die." In ISTFA 2008. ASM International, 2008. http://dx.doi.org/10.31399/asm.cp.istfa2008p0238.
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Abstract A case study of a transient induced latch-up (TLU) problem is presented, which was identified during the development of a 60 V, 0.8 µm BiCMOS power control device. The mechanism was characterized by controlled transient latch-up testing and found to be fairly unusual, being triggered by a fast decreasing not necessarily negative spike or glitch on the positive supply pin. Emission Microscopy (EMMI) and Transient Interferometric Mapping (TIM) successfully located the parasitic silicon controlled rectifiers (SCR) structure. TIM is an infra-red laser beam based technique for back side analysis. TIM analysis enables concurrent imaging of carrier injection and heating in nanosecond timescale providing more detailed information on the SCR action than more often used static photon emission or dynamic TLP / PICA imaging.
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Heer, M., D. Pogany, M. Street, I. Smith, F. Riedlberger, D. Bonfert, and H. A. Gieser. "Transient Latch-Up Analysis of Power Control Device with Combined Light Emission and Backside Transient Interferometric Mapping Methods." In ISTFA 2008. ASM International, 2008. http://dx.doi.org/10.31399/asm.cp.istfa2008p0493.
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Abstract A case study of a transient induced latch-up (TLU) problem is presented, which was identified during the development of a 60 V, 0.8 µm BiCMOS power control device. The mechanism was characterized by controlled transient latch-up testing and found to be fairly unusual, being triggered by a fast decreasing not necessarily negative spike or glitch on the positive supply pin. Emission Microscopy (EMMI) and Transient Interferometric Mapping (TIM) successfully located the parasitic silicon controlled rectifiers (SCR) structure. TIM is an infra-red laser beam based technique for back side analysis. TIM analysis enables concurrent imaging of carrier injection and heating in nanosecond timescale providing more detailed information on the SCR action than more often used static photon emission or dynamic TLP / PICA imaging.
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Swidan, A. M., S. M. El‐Ghanam, and F. A. S. Soliman. "Operation of Bidirectional Switches (DIAC) and Silicon Controlled Rectifiers (SCR) in Gamma‐Radiation Environment." In MODERN TRENDS IN PHYSICS RESEARCH: First International Conference on Modern Trends in Physics Research; MTPR-04. American Institute of Physics, 2005. http://dx.doi.org/10.1063/1.1896503.
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Lee, Jian-Hsing, Shao-Chang Huang, Yu-Huei Lee, and Ke-Horng Chen. "Two-stage trigger silicon-controller rectifier (SCR) for radio-frequency (RF) ESD protection in the nanometer technologies." In ESSDERC 2011 - 41st European Solid State Device Research Conference. IEEE, 2011. http://dx.doi.org/10.1109/essderc.2011.6044155.
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Henry, Leo G., Jon Barth, John Richner, and Koen Verhaege. "Transmission Line Pulse Testing of the ESD Protection Structures in ICs – A Failure Analyst’s Perspective." In ISTFA 2000. ASM International, 2000. http://dx.doi.org/10.31399/asm.cp.istfa2000p0203.
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Abstract The IC industry continues to find ways to improve the ability to correlate the electrical failure signature of devices with the physical failure location using different techniques. The purpose of this work is to show that improved transmission line pulse (TLP) testing technique of ESD (ElectroStatic Discharge) protection structures can provide accurate identification of leakage current to better identify where ESD stress testing should stop and failure analysis should begin. Besides the traditional current and voltage measurements at the Device Under Test (DUT), this new TLP testing technique includes the ability to correct for the measurement system losses for improved accuracy. The pulse width of the TLP is chosen to provide the same current amplitude damage level (electrical) as is found in the Human Body Model (HBM) ESD stress testing. This allows a one to one correlation between the two methods and hence the means to correlate the electrical damage of the device and the physical location of the failure site. An SCR (Silicon Controlled Rectifier) device is used as an example.
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Griffoni, A., S. H. Chen, S. Thijs, D. Linten, M. Scholz, and G. Groeseneken. "Charged device model (CDM) ESD challenges for laterally diffused nMOS (nLDMOS) silicon controlled rectifier (SCR) devices for high-voltage applications in standard low-voltage CMOS technology." In 2010 IEEE International Electron Devices Meeting (IEDM). IEEE, 2010. http://dx.doi.org/10.1109/iedm.2010.5703483.
Full textReports on the topic "Silicon Controlled Rectifier (SCR)"
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McCarty, C. Characterization and development report for the SA2859: A silicon controlled rectifier. Office of Scientific and Technical Information (OSTI), February 1990. http://dx.doi.org/10.2172/7005428.
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